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71. 发明申请

US20070247186A1 SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM 失效
标题翻译：具有功率降低机制的半导体集成电路
公开(公告)号：US20070247186A1
公开(公告)日：2007-10-25
申请号：US11768981
申请日：2007-06-27
申请人： Takeshi SAKATA , Kiyoo Itoh , Masashi Horiguchi
发明人： Takeshi SAKATA , Kiyoo Itoh , Masashi Horiguchi
IPC分类号： H03K17/16
CPC分类号： H03K19/0016 , G11C5/147 , G11C7/065 , G11C8/08 , G11C8/12 , H03K19/00361
摘要： A semiconductor integrated circuit with an operating voltage having an absolute value is 2.5 V or below includes circuit blocks to which operation voltage is supplied by first and second power lines and a first switching element for each circuit block. Each circuit block includes a first MOS transistor in which a leakage current flows even under a condition that a gate voltage is equal to a source voltage. Each of the first switching elements controls the leakage current flowing through a corresponding first MOS transistor of each circuit block. Also, while one of the first switching elements is controlled to reduce the leakage current flowing through the circuit block relating to one of the first switching elements, another one of the first switching elements is controlled to allow current to flow through the circuit block relating to another one of the first switching elements. In addition, current which is allowed to flow by the another one of the first switching elements is sufficient to permit the circuit block relating to another one of the first switching elements to logically operate.
摘要翻译：具有绝对值的工作电压的半导体集成电路为2.5V以下，包括由第一和第二电力线提供工作电压的电路块和每个电路块的第一开关元件。每个电路块包括即使在栅极电压等于源极电压的条件下漏电流也流过的第一MOS晶体管。每个第一开关元件控制流过每个电路块的对应的第一MOS晶体管的漏电流。此外，虽然控制第一开关元件中的一个以减少流过与第一开关元件之一相关的电路块的漏电流，但是第一开关元件中的另一个被控制以允许电流流过与另一个是第一个开关元件。此外，允许通过另一个第一开关元件流动的电流足以允许与另一个第一开关元件相关的电路块逻辑操作。

72. 发明授权

US07242214B2 Semiconductor integrated circuits with power reduction mechanism 失效
公开(公告)号：US07242214B2
公开(公告)日：2007-07-10
申请号：US11599275
申请日：2006-11-15
申请人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
发明人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
IPC分类号： H03K17/16 , G05F1/10
CPC分类号： G11C8/18 , G11C5/147 , G11C7/065 , G11C8/08 , G11C8/12 , G11C11/4074 , H03K19/0016 , H03K19/0027 , H03K19/00361
摘要： Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

73. 发明申请

US20070057696A1 Semiconductor integrated circuits with power reduction mechanism 失效
标题翻译：半导体集成电路具有功率降低机制
公开(公告)号：US20070057696A1
公开(公告)日：2007-03-15
申请号：US11599275
申请日：2006-11-15
申请人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
发明人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
IPC分类号： H03K19/0175
CPC分类号： G11C8/18 , G11C5/147 , G11C7/065 , G11C8/08 , G11C8/12 , G11C11/4074 , H03K19/0016 , H03K19/0027 , H03K19/00361
摘要： Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching-elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.
摘要翻译：半导体集成电路芯片的功耗在2.5V或更低的工作电压下工作时，功耗降低。开关元件设置在芯片内的每个电路块中。开关元件的常数被设定为使得其断开状态下的每个开关元件中的漏电流小于相应电路块内的MOS晶体管的亚阈值电流。有源电流被提供给有源电路块，而非有效电路块的开关元件被关断。因此，非有源电路块的耗散电流被限制为相应的开关元件的漏电流值。因此，非有源电路块的耗散电流的总和小于有源电路块中的有功电流。结果，即使在活动状态下，半导体集成电路芯片的功率消耗也可以减小。

74. 发明申请

US20060139052A1 Semiconductor integrated circuits with power reduction mechanism 有权
公开(公告)号：US20060139052A1
公开(公告)日：2006-06-29
申请号：US11356100
申请日：2006-02-17
申请人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
发明人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
IPC分类号： H03K19/003
CPC分类号： G11C8/18 , G11C5/147 , G11C7/065 , G11C8/08 , G11C8/12 , G11C11/4074 , H03K19/0016 , H03K19/0027 , H03K19/00361
摘要： Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

75. 发明授权

US06621292B2 Semiconductor integrated circuits with power reduction mechanism 失效
公开(公告)号：US06621292B2
公开(公告)日：2003-09-16
申请号：US10103966
申请日：2002-03-25
申请人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
发明人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
IPC分类号： H03K1716
CPC分类号： G11C8/18 , G11C5/147 , G11C7/065 , G11C8/08 , G11C8/12 , G11C11/4074 , H03K19/0016 , H03K19/0027 , H03K19/00361
摘要： Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

76. 发明授权

US06384623B1 Semiconductor integrated circuits with power reduction mechanism 有权
标题翻译：半导体集成电路具有功率降低机制
公开(公告)号：US06384623B1
公开(公告)日：2002-05-07
申请号：US09832853
申请日：2001-04-12
申请人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
发明人： Takeshi Sakata , Kiyoo Itoh , Masashi Horiguchi
IPC分类号： H03K1716
CPC分类号： G11C8/18 , G11C5/147 , G11C7/065 , G11C8/08 , G11C8/12 , G11C11/4074 , H03K19/0016 , H03K19/0027 , H03K19/00361
摘要： Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.
摘要翻译：半导体集成电路芯片的功耗在2.5V或更低的工作电压下工作时，功耗降低。开关元件设置在芯片内的每个电路块中。开关元件的常数被设定为使得其断开状态下的每个开关元件中的漏电流小于相应电路块内的MOS晶体管的亚阈值电流。有源电流被提供给有源电路块，而非有效电路块的开关元件被关断。因此，非有源电路块的耗散电流被限制为相应的开关元件的漏电流值。因此，非有源电路块的耗散电流的总和小于有源电路块中的有功电流。结果，即使在活动状态下，半导体集成电路芯片的功率消耗也可以减小。

77. 发明授权

US06337817B1 Semiconductor device having redundancy circuit 失效
标题翻译：具有冗余电路的半导体器件
公开(公告)号：US06337817B1
公开(公告)日：2002-01-08
申请号：US09633271
申请日：2000-08-04
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
IPC分类号： G11C700
CPC分类号： G11C29/80 , G11C29/785 , G11C29/808
摘要： A semiconductor memory such as a dynamic random access memory (DRAM), having a memory array which is divided into memory mats and a storage capacity of 16 M bits or more, features a defect recovery scheme through employing a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes a comparing circuit having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. In accordance with this, each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected
摘要翻译：诸如动态随机存取存储器（DRAM）的半导体存储器具有分割成存储器存储器的存储器阵列和16M位或更多存储容量的特征，通过采用冗余电路来形成缺陷恢复方案。存储器中的存储器阵列具有多个字线，多个位线，备用位线和多个存储器单元。冗余电路包括具有可编程元件的比较电路，其作为用于在其中存储存储器阵列中存在的缺陷地址的存储器。冗余电路的可编程元件可以根据多种不同类型的缺陷模式中的任何一种进行编程。根据这一点，冗余电路的每个比较电路比较输入其中的信息（数据），例如可能在地址多路复用系统的控制下的列和行地址与在比较的可编程元件中编程的电路。在此比较的基础上，进行适当的缺陷恢复

78. 发明授权

US6104647A Semiconductor device having redundancy circuit 失效
标题翻译：具有冗余电路的半导体器件
公开(公告)号：US6104647A
公开(公告)日：2000-08-15
申请号：US363000
申请日：1999-07-30
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
IPC分类号： G11C5/00 , G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C29/80 , G11C29/785 , G11C29/808
摘要： A redundancy technique is introduced for a semiconductor memory and, more particularly, a redundancy technique for a memory, for example, a dynamic random access memory (DRAM) having a memory array which is divided into memory mats and a storage capacity of 16 mega bits or more. According to the present redundancy technique, for a semiconductor memory including a memory array which has a plurality of word lines, a plurality of bit lines arranged so that two-level crossings are formed between the word lines and the bit lines, memory cells disposed at desired ones of the two-level crossings, and spare bit lines, there is provided a redundancy circuit having a memory for storing therein a defective address existing in the memory array and comparing an address to be accessed with the stored defective address. Each of the address comparing circuits as stored therein the column address of a defective bit line and a part of the row address indicating the memory mat corresponding to the defective bit line.
摘要翻译：为半导体存储器引入冗余技术，更具体地说，涉及一种用于存储器的冗余技术，例如具有存储器阵列的动态随机存取存储器（DRAM），该存储器阵列被分成存储器阵列，存储容量为16兆比特或者更多。根据本技术的冗余技术，对于包含具有多个字线的存储器阵列的半导体存储器，配置成在字线和位线之间形成2级交叉的多位位线，位于提供了两级交叉中的期望的和备用位线，提供了一种冗余电路，其具有用于在其中存储存在于存储器阵列中的缺陷地址并将要访问的地址与存储的缺陷地址进行比较的存储器。每个地址比较电路存储有缺陷位线的列地址和表示与缺陷位线对应的存储器堆的行地址的一部分。

79. 发明授权

US5376839A Large scale integrated circuit having low internal operating voltage 失效
标题翻译：具有低内部工作电压的大规模集成电路
公开(公告)号：US5376839A
公开(公告)日：1994-12-27
申请号：US104340
申请日：1993-08-09
申请人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin'ichi Ikenaga
发明人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin'ichi Ikenaga
IPC分类号： G05F1/46 , G05F3/24 , G11C5/14 , G11C11/4074 , H01L27/02 , H03K3/01 , H03K3/26
CPC分类号： G05F1/465 , G05F3/245 , G05F3/247 , G11C11/4074 , G11C5/147 , H01L27/0203
摘要： Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.
摘要翻译：涉及超大规模半导体集成（ULSI）电路的实际结构，特别是16M位以上的动态随机存取存储器。 ULSI电路使用内部工作电压，并且如何构造参考电压发生电路，并且ULSI电路中的限压器电路是重要的。可以使参考电压发生电路和限压器电路的动作稳定，提高这些电路的特性，能够提高应用于存储单元阵列，外围电路等的这些电路的布局。提供了改进的测试这些电路的方法。

80. 发明授权

US5262993A Semiconductor memory having redundancy circuit with means to switch power from a normal memory block to a spare memory block 失效
标题翻译：具有冗余电路的半导体存储器，具有将功率从正常存储块切换到备用存储块的装置
公开(公告)号：US5262993A
公开(公告)日：1993-11-16
申请号：US789024
申请日：1991-11-06
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Yoshinobu Nakagome , Hitoshi Tanaka , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Yoshinobu Nakagome , Hitoshi Tanaka , Kiyoo Itoh
IPC分类号： G11C11/413 , G11C5/14 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C29/83 , G11C29/832 , G11C5/14
摘要： In a semiconductor memory, switch circuits are provided so as to inhibit voltage and signal supplies to each of the normal memory blocks when so required. On the other hand, a ROM is provided on the chip so as to store the address of a defective memory block which consumes an excessively large stand-by current when the semiconductor memory is in the stand-by mode. The switch circuits are controlled by the output of the ROM so as to inhibit the voltage and signal supply to the defective memory block. Then, a spare memory block which is substituted for the defective normal memory block receives the voltage and signal supply.
摘要翻译：在半导体存储器中，提供开关电路，以便当需要时，禁止向每个正常存储器块提供电压和信号。另一方面，在半导体存储器处于待机模式时，在芯片上提供ROM以存储消耗过大待机电流的缺陷存储块的地址。开关电路由ROM的输出控制，以便阻止向缺陷存储器块提供电压和信号。然后，代替有缺陷的正常存储块的备用存储块接收电压和信号供应。

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