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71. 发明授权

US5522084A Method and system for invalidating instructions utilizing validity and write delay flags in parallel processing apparatus 失效
标题翻译：在并行处理装置中使用有效和写延迟标志使指令无效的方法和系统
公开(公告)号：US5522084A
公开(公告)日：1996-05-28
申请号：US310508
申请日：1994-09-22
申请人： Hideki Ando
发明人： Hideki Ando
IPC分类号： G06F9/38 , G06F15/80
CPC分类号： G06F9/3885 , G06F9/30072
摘要： A superscalar-type processor includes an instruction memory, a fetch stage fetching simultaneously a plurality of instructions from the instruction memory, functional units respectively executing predetermined functions, and a decode state decoding the fetched instructions to issue parallel-processable instructions to related functional units. The decode stage includes a decoder determining whether a branch instruction is included in the received instructions and whether a branch is generated according to the branch instruction. The decoder links a write delaying flag indicating whether the instruction is after a branch instruction and a validity flag indicating whether the instruction is valid to the instruction on issuing the instruction to a functional unit. The functional unit includes an execution stage executing an instruction and a write back stage changing a machine state according to the result of execution in the execution stage. The superscalar-type processor comprises a control circuit forbidding changing of the machine state by a write back stage when a branch is generated according to the branch instruction. The control circuit sets the write back stage in a state of delaying changing of the machine state when it is not yet determined whether a branch is generated according to the branch instruction and executes changing of the machine state with the write back stage when it is determined that no branch is generated according to the branch instruction.
摘要翻译：超标量型处理器包括指令存储器，取指阶段从指令存储器同时获取多个指令，分别执行预定功能的功能单元，以及解码所取出的指令以对相关功能单元发布可并行处理的指令的解码状态。解码级包括解码器，确定分支指令是否包括在接收到的指令中以及根据分支指令是否生成分支。解码器将表示指示是否在分支指令之后的写入延迟标志和表示指令是否对发出对功能单元的指令的指令有效的有效标志进行链接。功能单元包括执行指令的执行阶段和在执行阶段中根据执行结果改变机器状态的回写阶段。超标量型处理器包括控制电路，当根据分支指令生成分支时，禁止通过回写阶段改变机器状态。当尚未确定是否根据分支指令生成分支时，控制电路将回写阶段设置为延迟机器状态的变化的状态，并且在确定时执行具有回写阶段的机器状态的改变根据分支指令不生成分支。

72. 发明授权

US5396640A Boosting method and apparatus in a parallel computer 失效
标题翻译：并行计算机中的升压方法和装置
公开(公告)号：US5396640A
公开(公告)日：1995-03-07
申请号：US883948
申请日：1992-05-15
申请人： Chikako Ikenaga , Hideki Ando
发明人： Chikako Ikenaga , Hideki Ando
IPC分类号： G06F9/38 , G06F15/16
CPC分类号： G06F9/3804 , G06F9/3842
摘要： A parallel computer having a boosting function in which an instruction belonging to a later basic block is moved to a precedent basic block in an instruction group, the moved basic block being a branch instruction. The moved instruction and an instruction in the precedent basic block are arranged in parallel in the order of an instruction code. Therefore, the number of boosted instructions which can be executed in parallel is increased and the degree of parallelization of instruction is increased so that the function of the computer is improved.
摘要翻译：具有升压功能的并行计算机，其中属于稍后的基本块的指令被移动到指令组中的先前的基本块，所移动的基本块是分支指令。移动的指令和先前基本块中的指令按照指令代码的顺序并行排列。因此，可以并行执行的升压指令的数量增加，指令的并行程度增加，从而提高了计算机的功能。

73. 发明授权

US5386528A Address translator having a high speed data comparator 失效
标题翻译：具有高速数据比较器的地址转换器
公开(公告)号：US5386528A
公开(公告)日：1995-01-31
申请号：US874921
申请日：1992-04-29
申请人： Hideki Ando , Hirohisa Machida
发明人： Hideki Ando , Hirohisa Machida
IPC分类号： G06F7/02 , G06F12/10 , G06F12/12 , G11C15/00
CPC分类号： G11C15/00 , G06F12/123 , G06F7/02 , G06F12/1027
摘要： An address translator has an improved data comparison circuit for comparing two pieces of data having n bits, e.g., 12 bits. In the data comparison circuit, cell circuits compare two pieces of data for every corresponding 4 bits. When a match is detected in the comparison of a set of 4 bits, a signal representative of the comparison result of the lower-order bits is bypassed. Hence, delay of signal propagation which may occur in the cell circuit in which the match is detected is reduced.
摘要翻译：地址转换器具有改进的数据比较电路，用于比较具有n位的两个数据，例如12位。在数据比较电路中，单元电路对每个相应的4位数据进行比较。当在一组4比特的比较中检测到匹配时，旁路表示低位比特的比较结果的信号。因此，可以在检测到匹配的单元电路中发生的信号传播的延迟减小。

74. 发明授权

US4933892A Integrated circuit device for orthogonal transformation of two-dimensional discrete data and operating method thereof 失效
标题翻译：用于二维离散数据正交变换的集成电路装置及其操作方法
公开(公告)号：US4933892A
公开(公告)日：1990-06-12
申请号：US390997
申请日：1989-08-09
申请人： Masao Nakaya , Hideki Ando
发明人： Masao Nakaya , Hideki Ando
IPC分类号： G06F17/14 , G06T1/20 , G06T3/00 , G06T5/20
CPC分类号： G06F17/147
摘要： The device, for performing an orthogonal transformation of two dimensional discrete data array of n x n matrix at a high speed, includes a first block including storage elements for storing individual elements of a matrix for orthogonal transformation, a second block including storage elements for storing a data array therein, and a third block including a plurality of storage elements for storing a result of a multiplication therein, and n x n pointer registers each making a shifting operation in the row direction. When the pointer registers are reset, only diagonal elements thereof produce an activating signal. The device further includes circuitry for selecting a response to a signal from the pointer block, particular ones of the elements of the first, second and third blocks, multiplying contents of the selected elements of the first and second blocks, and adding a result of the multiplication to contents of the selected element of the third block and writing a result of the addition back into the selected elements of the third block. The device further includes a shifting clock generator which sets the shifting direction of the first and second storage blocks. After completion of the first matrix multiplication, result of the multiplication is transferred from the third storage block to the second storage block. Upon second matrix multiplication, shifting operations of the first and second blocks are performed in directions different from the directions in the first matrix multiplication.
摘要翻译：用于以高速执行n×n矩阵的二维离散数据阵列的正交变换的装置包括：第一块，包括用于存储用于正交变换的矩阵的各个元素的存储元件;第二块，包括用于存储数据的存储元件并且包括用于存储乘法结果的多个存储元件的第三块以及在行方向上进行移位操作的nxn个指针寄存器。当指针寄存器被复位时，只有其对角元件产生激活信号。所述设备还包括用于选择对来自所述指针块的信号的响应的电路，所述第一，第二和第三块的元素中的特定元素乘以所述第一和第二块的所选择的元素的内容，与第三块的所选择的元素的内容相乘，并将加法的结果写回到所选择的第三块的元素中。该装置还包括设置第一和第二存储块的移动方向的移位时钟发生器。在完成第一矩阵乘法之后，乘法结果从第三存储块传送到第二存储块。在第二矩阵乘法时，在与第一矩阵乘法中的方向不同的方向上执行第一和第二块的移位操作。

75. 发明授权

US4860235A Arithmetic unit with alternate mark inversion (AMI) coding 失效
标题翻译：具有交替标记反转（AMI）编码的算术单元
公开(公告)号：US4860235A
公开(公告)日：1989-08-22
申请号：US132644
申请日：1987-12-08
申请人： Harufusa Kondou , Hideki Ando
发明人： Harufusa Kondou , Hideki Ando
IPC分类号： G06F7/504 , G06F7/508 , H03M5/18 , H04L25/49
CPC分类号： H03M5/18 , H04L25/4925
摘要： An arithmetic unit having true and false deciding circuits (21 to 24) for receiving a first input signal A and a second input signal B to output the second input signal or complement of the same in response to the sign (most significant bit value) of the second input signal. The arithmetic unit further includes an adder (31 to 34) for receiving the first input signal A and output (M) from the true and false deciding circuits to output either A+M or A+M+1 in response to the sign (most significant bit value) of the second input signal B and an AND gate (50) for receiving the most significant bit F.sub.4 of output F from the adder and the most significant bit value B.sub.4 of the second input signal B. The arithmetic unit thus outputs the alternate mark inversion (AMI) code of the input signal B having the output of the AND gate (50) as a high order bit and the most significant bit F.sub.4 of the output F of the adder as a low order bit, with a threshold value of the input signal A.
摘要翻译：具有用于接收第一输入信号A和第二输入信号B的真和假判定电路（21至24）的运算单元，以响应于第二输入信号的符号（最高有效位值）输出第二输入信号或第二输入信号第二个输入信号。算术单元还包括一个加法器（31至34），用于从真和假判定电路接收第一输入信号A和输出（M），以响应于符号输出A + M或A + M + 1 第二输入信号B的有效位值）和用于从加法器接收输出F的最高有效位F4和第二输入信号B的最高有效位值B4的与门（50）。因此，运算器输出具有与门（50）的输出作为高阶位的输入信号B的交替标记反转（AMI）代码，加法器的输出F的最高有效位F4作为低位位，具有阈值的输入信号A.

76. 发明授权

US4821225A Arithmetic and logic unit with prior state dependent logic operations 失效
标题翻译：具有先前状态相关逻辑运算的算术逻辑单元
公开(公告)号：US4821225A
公开(公告)日：1989-04-11
申请号：US042532
申请日：1987-04-27
申请人： Hideki Ando , Hirohisa Machida
发明人： Hideki Ando , Hirohisa Machida
IPC分类号： G06F7/00 , G06F7/575 , G06F7/38
CPC分类号： G06F7/575
摘要： The present invention is an arithmetic and logic unit of a microprocessor having hardware improved to execute specified operation such as operation of MAD (modified addition) by a small number of instruction steps.The arithmetic and logic unit of the present invention has a control portion provided with a control circuit for performing the specified operation such as operation of MAD by a small number of instruction steps.
摘要翻译：本发明是具有改进的硬件的微处理器的算术和逻辑单元，以通过少量指令步骤执行诸如MAD（修改加法）的操作的指定操作。本发明的算术和逻辑单元具有控制部分，该控制部分设置有用于通过少量指令步骤执行诸如MAD的操作的指定操作的控制电路。

77. 发明授权

US08705138B2 Image forming apparatus including an image calibration system 失效
标题翻译：图像形成装置，包括图像校准系统
公开(公告)号：US08705138B2
公开(公告)日：2014-04-22
申请号：US13078451
申请日：2011-04-01
申请人： Hideki Ando , Katsuhisa Ono
发明人： Hideki Ando , Katsuhisa Ono
IPC分类号： H04N1/407 , B41J2/00
CPC分类号： H04N1/00002 , B41J2/32 , B41J2/36 , H04N1/00015 , H04N1/00031 , H04N1/00045 , H04N1/121 , H04N1/193 , H04N1/6044 , H04N2201/044
摘要： There is provided an image forming apparatus including a print head adapted to form an image on a recording medium, a transport path for the recording medium, the transport path being provided on at least one of a feed side and a discharge side of the recording medium with respect to the print head, an image reading device provided on the transport path, the image reading device being adapted to read an image formed by the print head, a correction chart provided opposite the image reading device with the transport path interposed in between, the correction chart being read by the image reading device in order to correct a reading result of the image reading device, based on information obtained from reading the correction chart, and a distance adjustment device adapted to increase or decrease the distance between the correction chart and the image reading device.
摘要翻译：提供了一种图像形成装置，其包括适于在记录介质上形成图像的打印头，用于记录介质的传送路径，传送路径设置在记录介质的进给侧和排出侧中的至少一个相对于打印头，设置在传送路径上的图像读取装置，所述图像读取装置适于读取由所述打印头形成的图像;校正图，设置在所述图像读取装置的与所述图像读取装置的相对的位置之间，所述校正图表由所述图像读取装置读取，以便根据读取所述校正图形而获得的信息校正所述图像读取装置的读取结果;以及距离调整装置，其适于增加或减少所述校正图表与图像读取装置。

78. 发明授权

US08326128B2 Conversion apparatus and conversion method 有权
标题翻译：转换装置及转换方法
公开(公告)号：US08326128B2
公开(公告)日：2012-12-04
申请号：US10665090
申请日：2003-09-18
申请人： Satoshi Katsuo , Hideki Ando , Hisao Tanaka , Takashi Furukawa , Masaki Hirose , Takayoshi Kawamura , Motohiro Terao
发明人： Satoshi Katsuo , Hideki Ando , Hisao Tanaka , Takashi Furukawa , Masaki Hirose , Takayoshi Kawamura , Motohiro Terao
IPC分类号： H04N5/93
CPC分类号： G11B27/034 , G11B27/024 , G11B27/032 , G11B2220/20 , G11B2220/90 , H04N5/765 , H04N5/85
摘要： A conversion apparatus and method is disclosed by which a file including data multiplexed therein can be edited or handled readily while maintaining the compatibility. A standard/independent conversion section converts a file of a standard AV multiplex format wherein video data and audio data are placed in a multiplexed state in a body into a file of an AV independent format wherein video data or audio data are placed collectively in a body. Meanwhile, an independent/standard conversion section converts a file of the AV independent formation into a file of the standard AV multiplex format.
摘要翻译：公开了一种转换装置和方法，通过该转换装置和方法，可以容易地编辑或处理包含其中多路复用的数据的文件，同时保持兼容性。标准/独立转换部分将视频数据和音频数据以身体中的多路复用状态放置在AV独立格式的文件中，将视频数据或音频数据集体放置在身体中的标准AV多路复用格式的文件。同时，独立/标准转换部分将AV独立编组的文件转换为标准AV多路复用格式的文件。

79. 发明申请

US20120050485A1 METHOD AND APPARATUS FOR GENERATING A STEREOSCOPIC IMAGE 审中-公开
标题翻译：用于产生立体图像的方法和装置
公开(公告)号：US20120050485A1
公开(公告)日：2012-03-01
申请号：US13174978
申请日：2011-07-01
申请人： Jonathan Richard THORPE , Hideki Ando
发明人： Jonathan Richard THORPE , Hideki Ando
IPC分类号： H04N13/02
CPC分类号： H04N13/156 , H04N2213/005
摘要： A method of producing a first stereoscopic image is described. The first stereoscopic image has a first left eye component and a first right eye component, by mixing a second stereoscopic image having a second left eye component and a second right eye component wherein depth information is associated with the second left eye component and depth information is associated with the second right eye component with a third image having depth information associated therewith, the method comprising the steps of: at each pixel position of the first left eye component, comparing the depth information associated with the second left eye component and the third image at that pixel position, and at each pixel position of the first right eye component, comparing the depth information associated with the second right eye component and the third image at that pixel position; and determining the foreground pixel for the first left eye component and the first right eye component at the pixel position on the basis of said comparisons.
摘要翻译：描述了产生第一立体图像的方法。第一立体图像具有第一左眼分量和第一右眼分量，通过混合具有第二左眼分量的第二立体图像和第二右眼分量，其中深度信息与第二左眼分量相关联，并且深度信息是与第二右眼分量相关联，具有与其相关联的深度信息的第三图像，该方法包括以下步骤：在第一左眼分量的每个像素位置处，比较与第二左眼分量和第三图像相关联的深度信息在该像素位置处，并且在第一右眼分量的每个像素位置，将与该第二右眼分量相关联的深度信息与该像素位置处的第三图像进行比较; 以及基于所述比较确定在像素位置处的第一左眼分量和第一右眼分量的前景像素。

80. 发明授权

US08024363B2 Information processing apparatus, information processing method, program and program recording medium 失效
标题翻译：信息处理装置，信息处理方法，程序和程序记录介质
公开(公告)号：US08024363B2
公开(公告)日：2011-09-20
申请号：US11975847
申请日：2007-10-22
申请人： Takahiro Araki , Kevin Mark Whiting , Hideki Ando
发明人： Takahiro Araki , Kevin Mark Whiting , Hideki Ando
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F17/30233
摘要： An information processing apparatus adapted to be connected for use to a media drive apparatus for recording data on or reproduced data from a recording medium having a file system includes a real file system acquiring section that acquires the file system of the recording medium from the media drive apparatus and a virtual file system providing section that converts the file system acquired by the file system acquiring section into a virtual file system having a directory/file structure different from the directory/file structure on the recording medium and provides it to an application program.
摘要翻译：一种信息处理装置，适用于连接到用于从具有文件系统的记录介质上记录数据或从其重放数据的媒体驱动装置，包括：真实文件系统获取部分，从媒体驱动器获取记录介质的文件系统装置和虚拟文件系统提供部分，其将由文件系统获取部分获取的文件系统转换成具有与记录介质上的目录/文件结构不同的目录/文件结构的虚拟文件系统，并将其提供给应用程序。

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