专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20060051934A1 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20060051934A1
公开(公告)日：2006-03-09
申请号：US10544491
申请日：2004-02-02
申请人： Tadahiro Ohmi , Akinobu Teramoto
发明人： Tadahiro Ohmi , Akinobu Teramoto
IPC分类号： H01L21/30
CPC分类号： H01L21/76256
摘要： An insulating film is formed as a pore-wall protective film (103) on pore walls in a porous layer (102) by the use of a mixed gas plasma of a noble gas and an insulating film forming gas generated by microwave excitation. As a result, the pore-wall protective film can have film properties as a protective film.
摘要翻译：通过使用惰性气体的混合气体等离子体和通过微波激发产生的形成绝缘膜的气体，在多孔层（102）的孔壁上形成绝缘膜作为孔壁保护膜（103）。结果，孔壁保护膜可以具有作为保护膜的膜性质。

72. 发明授权

US09157681B2 Surface treatment method for atomically flattening a silicon wafer and heat treatment apparatus 有权
标题翻译：用于使硅晶片和热处理设备原子平坦化的表面处理方法
公开(公告)号：US09157681B2
公开(公告)日：2015-10-13
申请号：US13565868
申请日：2012-08-03
申请人： Tadahiro Ohmi , Akinobu Teramoto , Tomoyuki Suwa
发明人： Tadahiro Ohmi , Akinobu Teramoto , Tomoyuki Suwa
IPC分类号： H01L29/06 , F27B17/00 , H01L21/02 , H01L21/302 , H01L21/67 , H01L21/677 , H01L21/324
CPC分类号： H01L21/3247 , F27B17/0025 , H01L21/02052 , H01L21/02238 , H01L21/02252 , H01L21/302 , H01L21/67017 , H01L21/67109 , H01L21/67126 , H01L21/67757
摘要： In a silicon wafer which has a surface with a plurality of terraces formed stepwise by single-atomic-layer steps, respectively, no slip line is formed.
摘要翻译：在具有分别通过单原子层阶梯逐步形成的多个台阶的表面的硅晶片中，不形成滑移线。

73. 发明授权

US08399862B2 Ion implanting apparatus and ion implanting method 有权
标题翻译：离子注入装置和离子注入方法
公开(公告)号：US08399862B2
公开(公告)日：2013-03-19
申请号：US12521019
申请日：2007-12-20
申请人： Tadahiro Ohmi , Tetsuya Goto , Akinobu Teramoto , Takaaki Matsuoka
发明人： Tadahiro Ohmi , Tetsuya Goto , Akinobu Teramoto , Takaaki Matsuoka
IPC分类号： G21K5/10 , H01S3/00 , H05H3/02 , A61N5/00 , G21G5/00 , G21G4/00
CPC分类号： H01L21/265 , H01J37/3222 , H01J37/32412 , H01J37/32706 , H01J2237/20 , H01J2237/26 , H01L21/26513 , H01L21/2658 , H01L29/30 , H01L29/7833
摘要： When positively charged ions are implanted into a target substrate, charge-up damage may occur on the target substrate. In order to suppress charge-up caused by secondary electrons emitted from the target substrate when positively charged ions are implanted, a conductive member is installed at a position facing the target substrate and electrically grounded with respect to a high frequency. Further, a field intensity generated in the target substrate may be reduced by controlling an RF power applied to the target substrate in pulse mode.
摘要翻译：当将带正电荷的离子注入目标衬底时，目标衬底上可能会发生充电损伤。为了抑制当注入正电荷的离子时从目标衬底发射的二次电子引起的充电，导电构件安装在面向目标衬底并相对于高频电接地的位置。此外，可以通过以脉冲模式控制施加到目标衬底的RF功率来减小在目标衬底中产生的场强。

74. 发明授权

US08217270B2 Multilayer circuit board and electronic device 失效
标题翻译：多层电路板和电子设备
公开(公告)号：US08217270B2
公开(公告)日：2012-07-10
申请号：US11990860
申请日：2006-08-18
申请人： Tadahiro Ohmi , Akinobu Teramoto , Akihiro Morimoto
发明人： Tadahiro Ohmi , Akinobu Teramoto , Akihiro Morimoto
IPC分类号： H05K1/03
CPC分类号： H05K1/024 , H05K3/4602 , H05K3/4626 , H05K3/4673 , H05K2201/0116 , H05K2201/0195 , H05K2201/0209 , H05K2201/0254
摘要： A multilayered circuit board which is provided with a low-permittivity interlayer insulating film, and which can significantly improve the performance such as signal transmission characteristics of the multilayered circuit board such as a package and a printed board, because the surface in contact with the interlayer insulating film of the circuit board has no unevenness to eliminate the lowering of production yield and the deterioration of high-frequency signal transmission characteristics; and electronic equipment using the circuit board. The multilayered circuit board comprises, mounted on a substrate, plural wiring layers and plural insulating layers positioned between the plural wiring layers, wherein at least part of the plural insulating layers are composed of a porous insulating layer containing at least any of materials selected from a porous material group consisting of porous material, aerogel, porous silica, porous polymer, hollow silica and hollow polymer, and a non-porous insulating layer formed on at least one surface of the porous insulating layer and not containing the porous material group.
摘要翻译：具有低介电常数层间绝缘膜的多层电路板，能够显着地提高诸如封装和印刷电路板的多层电路板的信号传输特性等性能，因为与中间层电路板的绝缘膜没有不均匀性，消除了生产成本的降低和高频信号传输特性的恶化; 和使用电路板的电子设备。多层电路板包括安装在基板上的多个布线层和位于多个布线层之间的多个绝缘层，其中多个绝缘层的至少一部分由多孔绝缘层组成，多孔绝缘层至少含有选自由多孔材料，气凝胶，多孔二氧化硅，多孔聚合物，中空二氧化硅和中空聚合物组成的多孔材料组和形成在多孔绝缘层的至少一个表面上并且不包含多孔材料组的无孔绝缘层。

75. 发明授权

US08067809B2 Semiconductor storage device including a gate insulating film with a favorable nitrogen concentration profile and method for manufacturing the same 失效
标题翻译：包括具有有利的氮浓度分布的栅极绝缘膜的半导体存储装置及其制造方法
公开(公告)号：US08067809B2
公开(公告)日：2011-11-29
申请号：US11576499
申请日：2005-09-30
申请人： Junichi Kitagawa , Shigenori Ozaki , Akinobu Teramoto , Tadahiro Ohmi
发明人： Junichi Kitagawa , Shigenori Ozaki , Akinobu Teramoto , Tadahiro Ohmi
IPC分类号： H01L21/02
CPC分类号： H01L29/792 , H01L21/28202 , H01L21/28273 , H01L29/513
摘要： A semiconductor storage device with excellent electrical characteristics (write/erase characteristics) by favorable nitrogen concentration profile of a gate insulating film, and a method for manufacturing the semiconductor device. The semiconductor device fabricating method operates by transferring charges through a gate insulating film formed between a semiconductor substrate and a gate electrode, including introducing an oxynitriding species previously diluted by plasma excitation gas into a plasma processing apparatus, generating an oxynitriding species by a plasma, and forming an oxynitride film on the semiconductor substrate as the gate insulating film. The oxynitriding species contains NO gas at a ratio of 0.00001 to 0.01% to the total volume of gas introduced into the plasma processing apparatus.
摘要翻译：具有优异的栅极绝缘膜的氮浓度分布的电特性（写/擦除特性）的半导体存储装置及其制造方法。半导体器件制造方法通过将形成在半导体衬底和栅电极之间的栅极绝缘膜转移电荷，包括将先前由等离子体激发气体稀释的氮氧化物质引入到等离子体处理装置中，通过等离子体产生氮氧化物质，以及在半导体衬底上形成氧氮化物膜作为栅极绝缘膜。氮氧化物质相对于引入等离子体处理装置的气体的总体积含有0.00001〜0.01％的NO气体。

76. 发明授权

US07994063B2 Method for manufacturing semiconductor device and method for cleaning semiconductor substrate 有权
标题翻译：半导体装置的制造方法及半导体基板的清洗方法
公开(公告)号：US07994063B2
公开(公告)日：2011-08-09
申请号：US12988007
申请日：2009-04-10
申请人： Tadahiro Ohmi , Akinobu Teramoto , Rui Hasebe , Masayuki Miyashita
发明人： Tadahiro Ohmi , Akinobu Teramoto , Rui Hasebe , Masayuki Miyashita
IPC分类号： H01L21/30
CPC分类号： H01L21/02052 , H01L21/02054 , H01L21/0206 , Y10S438/906
摘要： Disclosed is a method for cleaning a semiconductor substrate that can solve a problem of a conventional cleaning method which should include at least five steps for cleaning a substrate such as a semiconductor substrate. The method for cleaning a semiconductor substrate comprises a first step of cleaning a substrate with ultrapure water containing ozone, a second step of cleaning the substrate with ultrapure water containing a surfactant, and a third step of removing an organic compound derived from the surfactant, with a cleaning liquid containing ultrapure water and 2-propanol. After the third step, plasma of noble gas such as krypton is applied to the substrate to further remove the organic compound derived from the surfactant.
摘要翻译：公开了一种能够解决现有的清洗方法的问题的半导体基板的清洗方法，该清洗方法应至少包括五个步骤，用于清洗半导体基板等基板。用于清洗半导体衬底的方法包括用含有臭氧的超纯水清洗衬底的第一步骤，用含有表面活性剂的超纯水清洗衬底的第二步骤以及从表面活性剂中除去有机化合物的第三步骤，含有超纯水和2-丙醇的清洗液。在第三步之后，将诸如氪的惰性气体的等离子体施加到基底上以进一步除去源自表面活性剂的有机化合物。

77. 发明授权

US07968470B2 Plasma nitriding method, method for manufacturing semiconductor device and plasma processing apparatus 失效
标题翻译：等离子体氮化方法，半导体装置及等离子体处理装置的制造方法
公开(公告)号：US07968470B2
公开(公告)日：2011-06-28
申请号：US11917013
申请日：2006-06-07
申请人： Tadahiro Ohmi , Akinobu Teramoto , Minoru Honda , Toshio Nakanishi
发明人： Tadahiro Ohmi , Akinobu Teramoto , Minoru Honda , Toshio Nakanishi
IPC分类号： H01L21/31
CPC分类号： H01L21/3185
摘要： A nitriding process is performed at a process temperature of 500° C. or more by causing microwave-excited high-density plasma of a nitrogen-containing gas to act on silicon in the surface of a target object, inside a process container of a plasma processing apparatus. The plasma is generated by supplying microwaves into the process container from a planar antenna having a plurality of slots.
摘要翻译：通过使含氮气体的微波激发的高密度等离子体作用在目标物体的表面的硅上，等离子体的处理容器内，在500℃以上的过程温度下进行氮化处理处理装置。通过从具有多个槽的平面天线向处理容器提供微波产生等离子体。

78. 发明授权

US07928018B2 Plasma processing method and method for manufacturing an electronic device 失效
标题翻译：等离子体处理方法及其制造方法
公开(公告)号：US07928018B2
公开(公告)日：2011-04-19
申请号：US10594895
申请日：2005-03-31
申请人： Tadahiro Ohmi , Akinobu Teramoto , Hiroshi Yamauchi , Yukio Hayakawa
发明人： Tadahiro Ohmi , Akinobu Teramoto , Hiroshi Yamauchi , Yukio Hayakawa
IPC分类号： H01L21/31 , H01L21/469 , H01L21/02 , C23C16/00
CPC分类号： H01L21/3105 , H01J2237/3387 , H01L21/28273 , H01L21/28282 , H01L21/3143 , H01L27/115 , H01L27/11521 , H01L27/11568
摘要： The application of oxynitriding treatment to electronic appliances involve the problem that N2 ions are formed to thereby damage any oxynitride film. It is intended to provide a method of plasma treatment capable of realizing high-quality oxynitriding and to provide a process for producing an electronic appliance in which use is made of the method of plasma treatment. There is provided a method of plasma treatment, comprising generating plasma with a gas for plasma excitation and introducing a treating gas in the plasma to thereby treat a treatment subject, wherein the treating gas contains nitrous oxide gas, this nitrous oxide gas introduced in a plasma of
摘要翻译：氧化氮化处理对电子设备的应用涉及形成N2离子从而损坏任何氮氧化物膜的问题。旨在提供能够实现高质量氮氧化的等离子体处理方法，并提供一种使用等离子体处理方法的电子设备的制造方法。提供了一种等离子体处理方法，包括用等离子体激发的气体产生等离子体并在等离子体中引入处理气体，从而处理处理对象，其中处理气体含有一氧化二氮气体，这种一氧化二氮气体引入等离子体的<2.24eV电子温度，从而降低了任何绝缘膜损伤的离子的产生，从而实现高质量的氮氧化。此外，提供了一种使用等离子体处理方法的电子设备的制造方法。

79. 发明授权

US07887385B2 Organic EL light emitting element, manufacturing method thereof, and display device 有权
标题翻译：有机EL发光元件及其制造方法以及显示装置
公开(公告)号：US07887385B2
公开(公告)日：2011-02-15
申请号：US11663560
申请日：2004-09-24
申请人： Tadahiro Ohmi , Akinobu Teramoto , Akihiro Morimoto
发明人： Tadahiro Ohmi , Akinobu Teramoto , Akihiro Morimoto
IPC分类号： H01J9/24
CPC分类号： H05B33/28 , H01L51/5206 , H01L51/5253 , H01L51/529 , H01L2251/5361 , H05B33/04
摘要： An organic EL light emitting element is provided with a conductive transparent electrode 3, a counter electrode 8 opposing the conductive transparent electrode 3, an organic EL light emitting layer 6 provided between the conductive transparent electrode 3 and the counter electrode 8, an insulating protection layer 9 provided to cover at least the organic EL light emitting layer 6, and a heat dissipating layer 11 which is brought into contact with the insulating protection layer 9. The conductive transparent electrode has an ITO film including at least one of Hf, V and Zr at least on the surface part on the side of the organic EL light emitting layer 6, and the insulating protection layer 9 includes a nitride film having a thickness of 100 nm or less.
摘要翻译：有机EL发光元件设置有导电透明电极3，与导电透明电极3相对的对置电极8，设置在导电性透明电极3和对置电极8之间的有机EL发光层6，绝缘保护层设置为至少覆盖有机EL发光层6，以及与绝缘保护层9接触的散热层11.导电性透明电极具有含有Hf，V，Zr中的至少一种的ITO膜至少在有机EL发光层6侧的表面部分上，绝缘保护层9包括厚度为100nm以下的氮化物膜。

80. 发明授权

US07863713B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07863713B2
公开(公告)日：2011-01-04
申请号：US12086886
申请日：2006-12-20
申请人： Tadahiro Ohmi , Akinobu Teramoto , Kazufumi Watanabe
发明人： Tadahiro Ohmi , Akinobu Teramoto , Kazufumi Watanabe
IPC分类号： H01L29/04
CPC分类号： H01L27/1211 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L29/045 , H01L29/785 , H01L2029/7857
摘要： For equalizing the rising and falling operating speeds in a CMOS circuit, it is necessary to make the areas of a p-type MOS transistor and an n-type MOS transistor different from each other due to a difference in carrier mobility therebetween. This area unbalance prevents an improvement in integration degree of semiconductor devices. The NMOS transistor and the PMOS transistor each have a three-dimensional structure with a channel region on both the (100) plane and the (110) plane so that the areas of the channel regions and gate insulating films of both transistors are equal to each other. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other. Further, the integration degree on a substrate can be improved twice as much as that in the conventional technique.
摘要翻译：为了均衡CMOS电路中的上升和下降操作速度，由于它们之间的载流子迁移率的差异，需要使p型MOS晶体管和n型MOS晶体管的面积彼此不同。该区域不平衡防止了半导体器件的集成度的提高。 NMOS晶体管和PMOS晶体管各自具有在（100）面和（110）面上具有沟道区的三维结构，使得两个晶体管的沟道区和栅绝缘膜的面积等于其他。因此，可以使栅极绝缘膜等的面积相等并且使栅极电容彼此相等。此外，基板上的积分度可以提高到常规技术的两倍。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式