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71. 发明授权

US5587668A Semiconductor devices utilizing neuron MOS transistors 失效
标题翻译：利用神经元MOS晶体管的半导体器件
公开(公告)号：US5587668A
公开(公告)日：1996-12-24
申请号：US119157
申请日：1993-09-20
申请人： Tadashi Shibata , Tadahiro Ohmi
发明人： Tadashi Shibata , Tadahiro Ohmi
IPC分类号： G06F7/49 , G06F7/50 , G06F7/501 , G06N3/063 , G11C11/56 , G11C16/04 , G11C27/00 , H01L29/788 , H03K19/0944 , H03K19/017
CPC分类号： G06F7/5013 , G06F7/49 , G06N3/0635 , G11C11/5621 , G11C16/0408 , G11C27/005 , H01L29/7881 , H03K19/0944 , G06F2207/482 , G06F2207/4826 , G11C11/54 , G11C2211/5611
摘要： A semiconductor device by which a circuit having the same functions as those of the conventional circuit is realized with a very small number of elements, and complex logical functions can be designed simply, and further, its layout is also possible. A semiconductor device made up of at least one neuron MOS transistor having a gate electrode provided in a potentially floating state in a portion for isolating a source and drain region via a first insulation film, and plural control electrodes which are capacitively coupled to the floating gate electrode via a second insulation film, is characterized in that the first signal is inputted to a first control gate electrode of the first neuron MOS transistor, the first signal is inputted to a first inverter comprising one or more stages, and the output of the first inverter is inputted to a second control gate electrode which is one of the plural control gate electrodes other than the first control gate electrode.
摘要翻译： PCT No.PCT / JP92 / 00347 Sec。 371日期：1993年9月20日 102（e）1993年9月20日PCT 1993年3月21日PCT公布。公开号WO92 / 16971 日期：1992年10月1日具有与现有电路相同功能的电路的半导体器件通过非常少的元件实现，并且可以简单地设计复杂的逻辑功能，此外，其布局也是可能的。一种由至少一个神经元MOS晶体管组成的半导体器件，所述至少一个神经元MOS晶体管具有经由第一绝缘膜隔离源极和漏极区域的部分中以潜在浮动状态设置的栅电极，以及电容耦合到浮置栅极的多个控制电极电极经由第二绝缘膜，其特征在于，第一信号被输入到第一神经元MOS晶体管的第一控制栅电极，第一信号被输入到包括一级或多级的第一反相器，第一信号的输出反相器被输入到除了第一控制栅电极之外的多个控制栅电极之一的第二控制栅电极。

72. 发明授权

US5110438A Reduced pressure surface treatment apparatus 失效
标题翻译：减压表面处理设备
公开(公告)号：US5110438A
公开(公告)日：1992-05-05
申请号：US536548
申请日：1990-07-10
申请人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
发明人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
IPC分类号： H01L21/28 , C23C14/22 , C23C14/34 , C23C14/40 , H01J37/32 , H01J37/34 , H01L21/00 , H01L21/285 , H01L29/47 , H01L29/872
CPC分类号： H01L21/67017 , H01J37/32082 , H01J37/32706 , H01J37/34 , H01J2237/32 , H01J2237/3348
摘要： The reduced pressure surface treatment apparatus according the present invention comprises at least one vacuum chamber and an exhaust unit and a gas supply unit connected thereto, and it is characterized in that it is provided with a holder to hold the specimen, means to bombard the specimen with ions without depositing a thin film on said specimen surface, and means to control kinetic energy of said ions to a small value. The reduced pressure surface treatment method of this invention is characterized in that substances adsorbed on the wafer surface or natural oxide film layers are removed by impinging ions on the wafer surface under a vacuum condition.
摘要翻译： PCT No.PCT / JP89 / 00026 Sec。 371日期1990年7月10日 102（e）日1990年7月10日PCT 1990年1月12日提交PCT。根据本发明的减压表面处理装置包括至少一个真空室和排气单元以及与其连接的气体供应单元，其特征在于由于设置有用于保持试样的保持器，用离子轰击试样而不在所述试样表面上沉积薄膜的装置，以及将所述离子的动能控制在较小值的装置。本发明的减压表面处理方法的特征在于，通过在真空条件下在晶片表面上冲击离子来去除吸附在晶片表面或自然氧化物膜层上的物质。

73. 发明授权

US4984060A Semiconductor device wirings with hillocks 失效
标题翻译：半导体器件与小丘配线
公开(公告)号：US4984060A
公开(公告)日：1991-01-08
申请号：US359764
申请日：1989-07-21
申请人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
发明人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
IPC分类号： H01L23/52 , H01L21/3205 , H01L23/522 , H01L23/528
CPC分类号： H01L23/5226 , H01L23/5283 , H01L2924/0002
摘要： A semiconductor device comprises metal wirings with its minimum line width of 1 .mu.m or less and on the surface of said metal wiring there is no hillock which has its height equal to or more than 1/4 of the minimum line width of said metal wiring. The main portion of said metal wiring is formed with pure metal, and is supplied in connection portion between the metal wiring and a semiconductor substrate with a barrier layer for preventing any atoms involved in said metal parts from diffusing into the semiconductor substrate.
摘要翻译： PCT No.PCT / JP88 / 00972 Sec。 371日期：1989年7月21日 102（e）日期1989年7月21日PCT PCT日期为1988年9月24日。一种半导体器件包括其最小线宽为1μm或更小的金属布线，并且在所述金属布线的表面上没有小丘高度等于或大于所述金属布线的最小线宽度的1/4。所述金属布线的主要部分由纯金属形成，并且在金属布线和具有阻挡层的半导体基板之间的连接部分中供应，以防止参与所述金属部件的任何原子扩散到半导体基板中。

74. 发明授权

US06691145B1 Computing circuit, computing apparatus, and semiconductor computing circuit 失效
标题翻译：计算电路，计算设备和半导体计算电路
公开(公告)号：US06691145B1
公开(公告)日：2004-02-10
申请号：US09615754
申请日：2000-07-13
申请人： Tadashi Shibata , Masahiro Konda , Tadahiro Ohmi
发明人： Tadashi Shibata , Masahiro Konda , Tadahiro Ohmi
IPC分类号： G06G700
CPC分类号： G11C11/5621 , G06G7/14 , G11C27/005 , H04N19/94
摘要： A computing circuit capable of computing an absolute difference with high-speed analog computation, a computing apparatus capable of computing the sum of absolute differences and a semiconductor computing circuit achievable with simple circuitry and suitable for use in such a computing circuit or apparatus. The computing circuit capable of computing the absolute difference includes a large input selection circuit 1 which outputs either a first signal or a second signal whichever is larger, a small input selection circuit 2 which outputs either the first and second signals whichever signal is smaller, and a subtraction circuit 3 which subtracts the output of the small input selection circuit 2 from the output of the large input selection circuit 1. The subtraction circuit 3 includes a capacitor 6, a first switch 4 provided between a first terminal of the capacitor 6 and the output of the large input selection circuit 1, a second switch 5 provided between the first terminal of the capacitor 6 and the output of the small input selection circuit 2, and a third switch 7 provided between a second terminal of the capacitor 6 and a terminal connected to a prescribed potential. The computing apparatus capable of computing the sum of absolute differences includes a plurality of such computing circuits, and computes the sum of the outputs of the computing circuits by using a summing circuit.
摘要翻译：一种能够计算与高速模拟计算的绝对差异的计算电路，能够计算绝对差的和的计算装置以及适用于这种计算电路或装置的简单电路可实现的半导体计算电路。能够计算绝对差的计算电路包括大输入选择电路1，其输出第一信号或第二信号（较大者），小输入选择电路2，其输出第一信号和第二信号，其中较小的信号;以及减法电路3，其从大输入选择电路1的输出中减去小输入选择电路2的输出。减法电路3包括电容器6，设置在电容器6的第一端和第一开关4之间的第一开关4，大输入选择电路1的输出，设置在电容器6的第一端子和小输入选择电路2的输出端之间的第二开关5以及设置在电容器6的第二端子与端子之间的第三开关7 连接到规定的电位。能够计算绝对差的和的计算装置包括多个这样的计算电路，并且通过使用求和电路来计算计算电路的输出之和。

75. 发明授权

US06259393B1 Semiconductor integrated circuit and driving method using comparator feedback loop to switch subtraction bypass circuit 失效
标题翻译：半导体集成电路和驱动方法使用比较器反馈回路来切换减法旁路电路
公开(公告)号：US06259393B1
公开(公告)日：2001-07-10
申请号：US09105258
申请日：1998-06-26
申请人： Katsuhisa Ogawa , Tadahiro Ohmi , Tadashi Shibata
发明人： Katsuhisa Ogawa , Tadahiro Ohmi , Tadashi Shibata
IPC分类号： H03M138
CPC分类号： H03M1/403
摘要： In order to solve the problem of increase in circuit scale and increase in power consumption due to use of a DA converter, a semiconductor integrated circuit comprises a signal amplifier 2, 10 capable of switching of a gain to 1 or 2, an arithmetic processor 7, 9 for performing a subtraction process of a reference voltage from an input signal to output a result thereof or for outputting the input signal without performing the subtraction process, a switch 8 whose one switch terminal is connected to a signal input terminal, whose other switch terminal is connected to an output side of sample hold circuits 5, 6, and whose common terminal is connected to an input side of the arithmetic processor, a comparator 3 for comparing an output from the signal amplifier with the reference voltage to binarize the output, and a switch 11 for connecting an output side of the signal amplifier to an input side of the sample hold circuits, wherein the arithmetic processor carries out a changeover between the operation of performing the subtraction process of the reference voltage from the input signal to output the result and the operation of outputting the input signal without performing the subtraction process, based on an output from the comparator, thereby decreasing the circuit scale and substantially eliminating occurrence of an error.
摘要翻译：为了解决由于使用DA转换器导致的电路规模增加和功耗增加的问题，半导体集成电路包括能够将增益切换为1或2的信号放大器2,10，运算处理器7 9，用于从输入信号执行参考电压的减法处理以输出其结果或用于在不执行减法处理的情况下输出输入信号;开关8，其一个开关端子连接到信号输入端子，其另一个开关端子连接到采样保持电路5,6的输出侧，并且其公共端连接到算术处理器的输入侧;比较器3，用于将来自信号放大器的输出与参考电压进行比较，以二值化输出; 以及用于将信号放大器的输出侧连接到采样保持电路的输入侧的开关11，其中，算术处理器执行基于比较器的输出，从输入信号执行参考电压的减法处理以输出结果和输出输入信号的操作而不执行减法处理的操作，从而减小电路规模并基本上消除发生的错误。

76. 发明授权

US6100741A Semiconductor integrated circuit utilizing insulated gate type transistors 失效
标题翻译：采用绝缘栅型晶体管的半导体集成电路
公开(公告)号：US6100741A
公开(公告)日：2000-08-08
申请号：US110012
申请日：1998-07-02
申请人： Katsuhisa Ogawa , Tadahiro Ohmi , Tadashi Shibata
发明人： Katsuhisa Ogawa , Tadahiro Ohmi , Tadashi Shibata
IPC分类号： G06G7/16 , G06G7/163 , G06F7/44
CPC分类号： G06G7/163
摘要： For raising the accuracy of analog multiplication, a gate-drain (G-D) connection point of transistor (Tr) whose gate-drain (G-D) are shorted and whose source is connected to ground potential is connected to a source of second Tr whose G-D are shorted, a first input signal current source is connected to a G-D connection point of the second Tr, a G-D connection point of third Tr whose G-D are shorted and whose source is connected to the ground potential is connected to a source of fourth Tr whose G-D are shorted, a second input signal current source is connected to a G-D connection point of the fourth Tr, the G-D connection points of the second and fourth Tr's are connected to first and second capacitors respectively, outputs of the first and second capacitors are connected to each other and to a gate of fifth Tr to form a floating point, a source of the fifth Tr is connected to the ground potential, and a drain current of the fifth Tr is an operation output.
摘要翻译：为了提高模拟倍增的精度，其栅极漏极（GD）短路并且其源极连接到地电位的晶体管（Tr）的栅极 - 漏极（GD）连接点连接到第二Tr的源极，其中GD为短路时，第一输入信号电流源连接到第二Tr的GD连接点，GD短路的第三Tr的GD连接点和其源极连接到地电位，连接到第四Tr的源，其中GD 短路，第二输入信号电流源连接到第四Tr的GD连接点，第二和第四Tr的GD连接点分别连接到第一和第二电容器，第一和第二电容器的输出连接到彼此并且连接到第五Tr的栅极以形成浮点，第五Tr的源极连接到地电位，并且第五Tr的漏极电流是操作输出。

77. 发明授权

US06074538A Thin film forming equipment 失效
标题翻译：薄膜成型设备
公开(公告)号：US06074538A
公开(公告)日：2000-06-13
申请号：US872467
申请日：1997-06-10
申请人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
发明人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
IPC分类号： C23C8/14 , C23C14/34 , C23C14/35 , C23C14/56 , C23C16/44 , F16K31/02 , F16K51/02 , H01J37/32 , C23C14/00
CPC分类号： H01J37/32174 , C23C14/34 , C23C14/35 , C23C14/56 , C23C14/564 , C23C16/4404 , C23C8/14 , F16K31/02 , F16K51/02 , H01J37/32082 , H01J2237/186
摘要： A gate valve for a thin film forming apparatus. The gate valve includes two adjoining low-pressure chambers and a wall separating the two chambers. The wall includes an aperture and a thin plate for covering the aperture. The thin plate is movable in a direction substantially parallel to the plate surface. The gate valve further includes a voltage supply for applying a direct current between the thin plate and the wall.
摘要翻译：一种用于薄膜形成装置的闸阀。闸阀包括两个相邻的低压室和分隔两个室的壁。该壁包括孔和用于覆盖孔的薄板。薄板可以在基本上平行于板表面的方向上移动。闸阀还包括用于在薄板和壁之间施加直流电的电压源。

78. 发明授权

US6011714A Semiconductor circuit capable of storing a plurality of analog or multi-valued data 失效
标题翻译：能够存储多个模拟或多值数据的半导体电路
公开(公告)号：US6011714A
公开(公告)日：2000-01-04
申请号：US19270
申请日：1998-02-05
申请人： Tadashi Shibata , Tadahiro Ohmi , Yuichiro Yamashita
发明人： Tadashi Shibata , Tadahiro Ohmi , Yuichiro Yamashita
IPC分类号： G11C16/04 , G11C11/56 , G11C27/00 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C11/5621 , G11C11/5628 , G11C27/005 , G11C2211/5612
摘要： A semiconductor circuit assembly is capable of accurately storing a plurality of analog or multi-valued data using circuitry having a small surface area. The circuit assembly includes a first circuit provided in the form of a target memory cell device comprising memory cells which conduct the writing and storage of analog signals. The first circuit has output terminals for outputting stored values to the exterior as voltage signals. Mechanisms supply at least two index voltages. A second circuit performs the function of halting the writing of the analog signals when the output signal at the first circuit output terminals reaches a value representing a desired voltage plus the difference between the two index voltages.
摘要翻译：半导体电路组件能够使用具有小表面积的电路来精确地存储多个模拟或多值数据。电路组件包括以目标存储单元装置的形式提供的第一电路，其包括进行模拟信号的写入和存储的存储单元。第一电路具有用于将存储的值作为电压信号输出到外部的输出端子。机制提供至少两个指标电压。当第一电路输出端的输出信号达到表示期望电压的值加上两个指标电压之间的差时，第二电路执行停止模拟信号写入的功能。

79. 发明授权

US5982462A Inverse stagger or planar type thin-film transistor device and liquid-crystal display apparatus having floating gate electrode which is capacitively coupled with one or more input electrodes 失效
标题翻译：具有浮动栅电极的反交错或平面型薄膜晶体管器件和液晶显示装置，其具有与一个或多个输入电极电容耦合
公开(公告)号：US5982462A
公开(公告)日：1999-11-09
申请号：US812776
申请日：1997-03-06
申请人： Akira Nakano , Tadashi Shibata , Tadahiro Ohmi
发明人： Akira Nakano , Tadashi Shibata , Tadahiro Ohmi
IPC分类号： G02F1/136 , G02F1/1345 , G02F1/1362 , G02F1/1368 , H01L21/77 , H01L21/84 , H01L27/12 , H01L29/786 , H01L29/04
CPC分类号： H01L27/1214 , G02F1/1368 , G02F1/13454 , H01L29/78669
摘要： A thin film transistor device with its leakage current being controlled is provided. With such a thin film transistor device incorporated, a liquid crystal display apparatus presents a high-contrast image at a reduced power consumption. The thin film transistor is formed on an insulating substrate. The gate electrode of the transistor is electrically floating gate electrode, which is capacitance coupled to one or more input electrodes. The liquid crystal display apparatus incorporates the thin film transistor in its switching element and/or driving circuit.
摘要翻译：提供了一种其漏电流被控制的薄膜晶体管器件。通过并入这种薄膜晶体管器件，液晶显示装置以降低的功耗呈现高对比度图像。薄膜晶体管形成在绝缘基板上。晶体管的栅电极是电浮置栅电极，其电容耦合到一个或多个输入电极。液晶显示装置在其开关元件和/或驱动电路中并入薄膜晶体管。

80. 发明授权

US5923205A Semiconductor arithmetic circuit 失效
标题翻译：半导体运算电路
公开(公告)号：US5923205A
公开(公告)日：1999-07-13
申请号：US930372
申请日：1997-11-07
申请人： Tadashi Shibata , Tadahiro Ohmi , Masahiro Konda
发明人： Tadashi Shibata , Tadahiro Ohmi , Masahiro Konda
IPC分类号： G06G7/26 , G06G7/42
CPC分类号： G06G7/26
摘要： A semiconductor arithemetic circuit which performs calculation of an analog vector with a high accuracy at a high speed. A semiconductor arithemetic circuit having a plurality of MOS type transistors, wherein the source electrodes are connected to one another, the gate electrodes of the MOS type transistors are connected to a signal line having a prescribed potential via switching elements, and at least one input electrode is capacitively coupled with the gate electrodes; wherein circuitry is provided for applying first and second input voltages, respectively, to the input electrodes of at least one pair of first and second MOS type transistors among the plurality of MOS type transistors, and for equalizing potentials of the gate electrodes to the potential of the signal line by allowing the switching elements to conduct, and further circuitry means is provided for inputting the second and first input voltages into, respectively, the input electrodes of the first and second MOS type transistors after placing said gate electrodes in an electrically floating state by turning the switching elements off.
摘要翻译： PCT No.PCT / JP96 / 00882 Sec。 371日期：1997年11月7日 102（e）日期1997年11月7日PCT 1996年4月1日PCT PCT。 WO96 / 30853 PCT出版物日期：1996年10月3日一种以高速度高精度地进行模拟矢量的计算的半导体仿真电路。一种具有多个MOS型晶体管的半导体仿真电路，其中源极彼此连接，MOS型晶体管的栅电极通过开关元件连接到具有规定电位的信号线，并且至少一个输入电极与栅电极电容耦合; 其中提供电路，用于将多个MOS型晶体管中的至少一对第一和第二MOS型晶体管的输入电极分别施加第一和第二输入电压，并将栅电极的电位与信号线通过允许开关元件导通，并且还提供另外的电路装置，用于在将所述栅电极置于电浮动状态之后将第二和第一输入电压分别输入到第一和第二MOS型晶体管的输入电极中通过关闭开关元件。

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