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71. 发明授权

US5598108A High-density erasable programmable logic device architecture using multiplexer interconnections, and registered macrocell with product term allocation and adjacent product term stealing 失效
标题翻译：使用多路复用器互连的高密度可擦除可编程逻辑器件架构，以及具有产品术语分配和相邻产品术语窃取的注册宏单元
公开(公告)号：US5598108A
公开(公告)日：1997-01-28
申请号：US605445
申请日：1996-02-26
申请人： Bruce B. Pedersen
发明人： Bruce B. Pedersen
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/1776 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17764 , H03K19/17784 , H03K19/17792
摘要： A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories. A macrocell with product term allocation and adjacent product term stealing is also disclosed. Programmable configuration switches provide product term allocation by directing input product terms to an OR gate or to the secondary inputs to a register. Adjacent product term stealing is accomplished by providing the output of the OR gate of each macrocell as an input to the OR gate of an adjacent macrocell. By using the output of the OR gate of the first macrocell, the adjacent macrocell steals the product terms and the OR gate of the first macrocell for use in its own OR gate. An arbitrarily wide OR function can be implemented by daisy chaining the OR gates of adjacent macrocells. Because programmable configuration switches can direct individual input product terms to the register logic instead of the OR gate, the register logic can be used even when an adjacent macrocell steals the OR gate.
摘要翻译：提出了一种可编程逻辑器件，其包括全局互连阵列，其线路经由可编程多路复用器馈送到逻辑阵列块。全局互连阵列线以特定模式馈送到多路复用器，其最大化用户将所选线路路由到所选择的多路复用器的输出的能力，同时保持更高的速度和更低的功耗，并且使用更少的芯片阵列比使用基于可擦除可编程只读存储器的可编程互连阵列的现有技术的可编程逻辑器件。还公开了具有产品期限分配和相邻产品期限窃取的宏单元。可编程配置开关通过将输入产品术语指向或门或辅助输入到寄存器来提供产品术语分配。通过将每个宏单元的或门的输出作为相邻宏单元的或门的输入作为输入来实现相邻的产品期限窃取。通过使用第一宏单元的或门的输出，相邻的宏单元窃取产品项和第一宏单元的或门以在其自己的或门中使用。可以通过菊花链链接相邻宏单元的或门来实现任意宽的OR功能。因为可编程配置开关可以将各个输入产品项引导到寄存器逻辑而不是OR门，所以即使相邻的宏单元窃取或门，也可以使用寄存器逻辑。

72. 发明授权

US5565793A Programmable logic array integrated circuit devices with regions of enhanced interconnectivity 失效
标题翻译：具有增强互连区域的可编程逻辑阵列集成电路器件
公开(公告)号：US5565793A
公开(公告)日：1996-10-15
申请号：US517596
申请日：1995-08-22
申请人： Bruce B. Pedersen
发明人： Bruce B. Pedersen
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17796
摘要： A programmable logic array integrated circuit device which includes a plurality of regions of programmable logic and interconnection resources for selectively conveying logic signals between various ones of said regions has at least one portion of its interconnection resources enhanced or augmented relative to other similar portions. Any portions of a user's logic that requires more than a usual amount of interconnectivity can be placed in the portion of the device which has the augmented interconnection resources. Examples of augmented interconnection resources are extra conductors for conveying logic signals along one or more rows and/or one or more columns of logic regions on the device.
摘要翻译：可编程逻辑阵列集成电路器件包括多个可编程逻辑区域和互连资源区域，用于选择性地传送各个区域之间的逻辑信号，其互连资源的至少一部分相对于其它相似部分增强或增强。需要超过通常量的互连性的用户逻辑的任何部分可以被放置在具有增强的互连资源的设备的部分中。增强的互连资源的示例是用于沿设备上的一行或多行和/或一列或多列逻辑区传送逻辑信号的额外导体。

73. 发明授权

US5220214A Registered logic macrocell with product term allocation and adjacent product term stealing 失效
标题翻译：注册逻辑宏单元，产品术语分配和相邻产品术语窃取
公开(公告)号：US5220214A
公开(公告)日：1993-06-15
申请号：US879908
申请日：1992-05-08
申请人： Bruce B. Pedersen
发明人： Bruce B. Pedersen
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/1736 , H03K19/17712
摘要： A macrocell with product term allocation and adjacent product term stealing is disclosed. Programmable configuration switches provide product term allocation by directing input product terms to an OR gate or to the secondary inputs to a register. Adjacent product term stealing is accomplished by providing the output of the OR gate of each macrocell as an input to the OR gate of an adjacent macrocell. By using the output of the OR gate of the first macrocell, the adjacent macrocell steals the product terms and the OR gate of the first macrocell for use in its own OR gate. An arbitrarily wide OR function can be implemented by daisy chaining the OR gates of adjacent macrocells. Because programmable configuration switches can direct individual input product terms to the register logic instead of the OR gate, the register logic can be used even when an adjacent macrocell steals the OR gate.
摘要翻译：公开了具有产品期限分配和相邻产品期限窃取的宏单元。可编程配置开关通过将输入产品术语定向到或门或辅助输入到寄存器来提供产品术语分配。通过将每个宏单元的或门的输出作为相邻宏单元的或门的输入作为输入来实现相邻的产品期限窃取。通过使用第一宏单元的或门的输出，相邻的宏单元窃取产品项和第一宏单元的或门以在其自己的或门中使用。可以通过菊花链链接相邻宏小区的或门来实现任意宽的OR功能。因为可编程配置开关可以将各个输入产品项引导到寄存器逻辑而不是OR门，所以即使相邻的宏单元窃取或门，也可以使用寄存器逻辑。

74. 发明授权

US09646177B2 Systems and methods for preventing data remanence in memory systems 有权
公开(公告)号：US09646177B2
公开(公告)日：2017-05-09
申请号：US13098012
申请日：2011-04-29
申请人： Bruce B. Pedersen , Dirk A. Reese
发明人： Bruce B. Pedersen , Dirk A. Reese
IPC分类号： G06F7/38 , G06F21/79 , G06F21/76 , G11C7/20 , G11C11/419
CPC分类号： G06F21/79 , G06F21/76 , G11C7/20 , G11C11/419
摘要： Methods, circuits, and systems for preventing data remanence in memory systems are provided. Original data is stored in a first memory, which may be a static random access memory (SRAM). Data is additionally stored in a second memory. Data in the first memory is periodically inverted, preventing data remanence in the first memory. The data in the second memory is periodically inverted concurrently with the data in the first memory. The data in the second memory is used to keep track of the inversion state of the data in the first memory. The original data in the first memory can be reconstructed performing a logical exclusive-OR operation between the data in the first memory and the data in the second memory.

75. 发明授权

US08812869B1 Programmable logic device with improved security 有权
标题翻译：可编程逻辑器件具有改进的安全性
公开(公告)号：US08812869B1
公开(公告)日：2014-08-19
申请号：US13557005
申请日：2012-07-24
申请人： Bruce B. Pedersen
发明人： Bruce B. Pedersen
IPC分类号： G06F11/30 , G06F21/76
CPC分类号： G06F21/76 , G06F21/75
摘要： Techniques of the present invention impede power consumption measurements of an encryption engine on a logic device by running the encryption engine with an independent clock. This clock produces a signal that is decoupled from and asynchronous to clock signals feeding other circuits on the device. The clock feeding the encryption engine is not accessible externally to the device. Circuits may be employed to intentionally slow down or add jitter to one or more of the clock signals.
摘要翻译：本发明的技术通过运行具有独立时钟的加密引擎来阻碍逻辑设备上的加密引擎的功耗测量。该时钟产生与馈送设备上的其他电路的时钟信号去耦和异步的信号。馈送加密引擎的时钟不能从设备外部访问。可以采用电路有意地将抖动减慢或增加到一个或多个时钟信号。

76. 发明授权

US08638122B2 Apparatus for metastability-hardened storage circuits and associated methods 有权
标题翻译：用于亚硬化存储电路和相关方法的装置
公开(公告)号：US08638122B2
公开(公告)日：2014-01-28
申请号：US13089221
申请日：2011-04-18
申请人： Bruce B. Pedersen , Sivaraman Chokkalingam
发明人： Bruce B. Pedersen , Sivaraman Chokkalingam
IPC分类号： H03K19/00
CPC分类号： H03K3/0375 , H03K3/356121 , H03K3/356139
摘要： A metastability-hardened storage circuit includes at least one inverting circuit. The inverting circuit has a logical input. The logical input of the inverting circuit is split into a pair of physical inputs.
摘要翻译：亚稳态硬化存储电路包括至少一个反相电路。反相电路具有逻辑输入。反相电路的逻辑输入被分成一对物理输入。

77. 发明授权

US08572538B2 Reconfigurable logic block 有权
公开(公告)号：US08572538B2
公开(公告)日：2013-10-29
申请号：US13369226
申请日：2012-02-08
申请人： David W. Mendel , Gary Lai , Lu Zhou , Bruce B. Pedersen
发明人： David W. Mendel , Gary Lai , Lu Zhou , Bruce B. Pedersen
IPC分类号： G06F17/50 , H03K19/173
CPC分类号： G06F17/5054 , G06F11/1008 , H03K19/17756 , H03K19/17776
摘要： A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors.

78. 发明授权

US08434044B1 Specifying placement and routing constraints for security and redundancy 有权
标题翻译：指定安全和冗余的布局和路由约束
公开(公告)号：US08434044B1
公开(公告)日：2013-04-30
申请号：US12968128
申请日：2010-12-14
申请人： David Samuel Goldman , Bruce B. Pedersen , Gabriel Quan , Yuen Ho Choi
发明人： David Samuel Goldman , Bruce B. Pedersen , Gabriel Quan , Yuen Ho Choi
IPC分类号： G06F17/50 , G06F13/14
CPC分类号： G06F17/5072
摘要： A programmable chip design tool is provided to enumerate and specify the security and/or redundancy constraints of a programmable chip design. A design is implemented with a high-level security or redundancy scheme, and the programmable chip design tool applies the scheme while simultaneously optimizing for desired metrics (logic density, routability, timing, power, etc.). An underlying assignment scheme as well as user interface components used to enter this assignment scheme are provided.
摘要翻译：提供了一种可编程芯片设计工具来枚举和指定可编程芯片设计的安全和/或冗余约束。设计采用高级安全或冗余方案实现，而可编程芯片设计工具则应用该方案同时优化所需度量（逻辑密度，可布线性，时序，功率等）。提供了一个底层分配方案以及用于输入此分配方案的用户界面组件。

79. 发明申请

US20130002287A1 APPARATUS FOR IMPROVING RELIABILITY OF ELECTRONIC CIRCUITRY AND ASSOCIATED METHODS 有权
标题翻译：提高电子电路可靠性和相关方法的设备
公开(公告)号：US20130002287A1
公开(公告)日：2013-01-03
申请号：US13174599
申请日：2011-06-30
申请人： Bruce B. Pedersen , Irfan Rahim
发明人： Bruce B. Pedersen , Irfan Rahim
IPC分类号： H03K19/003 , H01L35/00 , H01L41/00 , H01L25/00
CPC分类号： H03K19/17752 , H03K19/003
摘要： In an exemplary embodiment, an apparatus includes a first set of circuit elements and a second set of circuit elements. The first set of circuit elements is used in a first configuration of the apparatus, and the second set of circuit elements is used in a second configuration of the apparatus. The first configuration of the apparatus is switched to the second configuration of the apparatus in order to improve reliability of the apparatus.
摘要翻译：在示例性实施例中，装置包括第一组电路元件和第二组电路元件。第一组电路元件用于装置的第一配置，并且第二组电路元件用于装置的第二配置。该设备的第一配置被切换到设备的第二配置，以便提高设备的可靠性。

80. 发明授权

US08321773B1 Hardware true random number generator in integrated circuit with tamper detection 有权
标题翻译：硬件真实随机数发生器集成电路中的篡改检测
公开(公告)号：US08321773B1
公开(公告)日：2012-11-27
申请号：US12262666
申请日：2008-10-31
申请人： Bruce B. Pedersen
发明人： Bruce B. Pedersen
IPC分类号： G06F11/00
CPC分类号： G06F7/588 , G06F21/554 , G06F21/71 , G06F21/86
摘要： Circuits and methods to generate a True Random Number Generator (TRNG) with tamper-detection are presented. In one embodiment, the circuit includes two identical TRNG circuits and logic circuitry that combines and correlates the outputs of the two TRNG circuits. The two identical TRNG circuits are located in close proximity to each other inside an Integrated Circuit (IC). The logic circuitry analyzes the outputs of the two TRNG circuits and the historical values of the relation between the outputs of the two TRNG circuits to determine if the outputs are correlated. If the outputs are not correlated, the logic circuitry outputs a true random number sequence based on the combination of the two TRNG circuits. As a result, circuit tampering, such as changes in temperature or voltage supplies, is detected in the IC.
摘要翻译：介绍了使用篡改检测来生成真随机数发生器（TRNG）的电路和方法。在一个实施例中，电路包括两个相同的TRNG电路和逻辑电路，其组合和相关两个TRNG电路的输出。两个相同的TRNG电路位于集成电路（IC）内彼此靠近的位置。逻辑电路分析两个TRNG电路的输出和两个TRNG电路的输出之间的关系的历史值，以确定输出是否相关。如果输出不相关，则逻辑电路基于两个TRNG电路的组合输出真正的随机数序列。结果，在IC中检测到电路篡改，例如温度变化或电压供应。

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