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71. 发明申请

US20060239072A1 Nonvolatile memory device and semiconductor device 有权
标题翻译：非易失性存储器件和半导体器件
公开(公告)号：US20060239072A1
公开(公告)日：2006-10-26
申请号：US11472993
申请日：2006-06-23
申请人： Toshihiro Tanaka , Takashi Yamaki , Yutaka Shinagawa , Daisuke Okada , Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru
发明人： Toshihiro Tanaka , Takashi Yamaki , Yutaka Shinagawa , Daisuke Okada , Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/10 , G11C16/0433
摘要： Disclosed here is a method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1 iA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1 iA to flow a current in the memory cell.
摘要翻译：这里公开了一种通过在数据写入时减小每个非易失性存储单元的阈值电压的变化来加速数据写入并降低功耗的方法。当在存储单元中写入数据时，约8V的电压被施加到存储器栅极线，大约5V的电压被施加到源极线，大约1.5V的电压分别施加到所选择的栅极线。此时，在写入电路中，写入脉冲为0，写入锁存器输出高电平信号，NAND电路输出低电平信号。并且，在恒定电流源晶体管中流动约1IA的恒定电流，并且通过约1iA的恒定电流放电位线以使存储单元中的电流流动。

72. 发明授权

US07115943B2 Nonvolatile semiconductor memory device and manufacturing method thereof 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07115943B2
公开(公告)日：2006-10-03
申请号：US11013406
申请日：2004-12-17
申请人： Toshiyuki Mine , Natsuki Yokoyama , Kan Yasui
发明人： Toshiyuki Mine , Natsuki Yokoyama , Kan Yasui
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L27/11568 , H01L29/792
摘要： A MONOS nonvolatile memory of a split gate structure, wherein writing and erasing are performed by hot electrons and hot holes respectively, is prone to cause electrons not to be erased and to remain in an Si nitride film on a select gate electrode sidewall and that results in the deterioration of rewriting durability. When long time erasing is applied as a measure to solve the problem, drawbacks appear, such as the increase of a circuit area caused by the increase of the erasing current and the deterioration of retention characteristics. In the present invention, an Si nitride film is formed by the reactive plasma sputter deposition method that enables oriented deposition and the Si nitride film on a select gate electrode sidewall is removed at the time when a top Si oxide film is formed.
摘要翻译：分离栅结构的MONOS非易失性存储器，其中由热电子和热孔分别执行写入和擦除容易导致电子不被擦除并且保留在选择栅极电极侧壁上的氮化硅膜中，并且结果在改写耐久性的恶化。当长时间擦除作为解决该问题的措施时，会出现缺点，例如由擦除电流的增加引起的电路面积的增加和保留特性的劣化。在本发明中，通过能够进行取向沉积的反应等离子体溅射沉积方法形成氮化硅膜，并且在形成顶部Si氧化物膜时，在选择栅电极侧壁上除去Si氮化物膜。

73. 发明申请

US20060035435A1 Semiconductor device and manufacturing method for semiconductor device to reduce the lithography masks 有权
标题翻译：用于半导体器件的半导体器件和制造方法来减少光刻掩模
公开(公告)号：US20060035435A1
公开(公告)日：2006-02-16
申请号：US11189078
申请日：2005-07-26
申请人： Kan Yasui , Digh Hisamoto , Tetsuya Ishimaru
发明人： Kan Yasui , Digh Hisamoto , Tetsuya Ishimaru
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , G11C16/0466 , H01L27/115 , H01L27/11519 , H01L27/11568 , H01L29/42344
摘要： Semiconductor device and manufacturing method for reducing the number of required lithography masks added to the nonvolatile memory in the standard CMOS process to shorten the production period and reduce costs. In a split-gate memory cell with silicided gate electrodes utilizing a sidewall structure, a separate auxiliary pattern is formed adjoining the selected gate electrodes. A contact is set on a wiring layer self-aligned by filling side-wall gates of polysilicon in the gap between the electrodes and auxiliary pattern. The contact may overlap onto the auxiliary pattern and device isolation region, in an optimal design considering the size of the occupied surface area. If the distance to the selected gate electrode is x, the ONO film deposit thickness is t, and the polysilicon film deposit thickness is d, then the auxiliary pattern may be separated just by a distance x such that x
摘要翻译：用于减少在标准CMOS工艺中添加到非易失性存储器中的所需光刻掩模的数量的半导体器件和制造方法，以缩短生产周期并降低成本。在具有利用侧壁结构的硅化栅电极的分裂栅极存储单元中，形成邻接所选择的栅电极的单独的辅助图案。通过填充电极和辅助图案之间的间隙中的多晶硅的侧壁栅极，将接触设置在自对准的布线层上。考虑到占用的表面积的大小，接触可以以最佳设计重叠在辅助图案和设备隔离区域上。如果到选定的栅电极的距离为x，则ONO膜沉积厚度为t，多晶硅膜沉积厚度为d，则辅助图案可以仅分开距离x，使得x <2x（t + d）。

74. 发明申请

US20060028868A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060028868A1
公开(公告)日：2006-02-09
申请号：US11198191
申请日：2005-08-08
申请人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
发明人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
IPC分类号： G11C11/34 , G11C5/06
CPC分类号： H01L27/1157 , G11C16/0425 , H01L21/28282 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/0649 , H01L29/4234 , H01L29/42344 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： Memory cells are disposed in plural array form. Select gate electrodes of the memory cells arranged in an X direction are connected to one another by select gate lines respectively. Memory gate electrodes are connected by memory gate lines respectively. The memory gate lines respectively connected to the memory gate electrodes of the memory cells adjacent to one another through source regions interposed therebetween are not electrically connected to one another. Each of the select gate lines has a first portion that extends in the X direction, and a second portion 9b of which one end is connected to the first portion and extends in a Y direction. The memory gate line is formed on its corresponding sidewall of the select gate line with an insulating film interposed therebetween. The memory gate line has a contact section that extends in the X direction from over a second portion of the select gate line to over an element isolation region, and is connected to its corresponding wiring through a plug that buries a contact hole formed over the contact section.
摘要翻译：存储单元以多个阵列形式布置。选择沿X方向布置的存储单元的选择栅电极分别通过选择栅极线彼此连接。存储器栅极电极分别由存储器栅极线连接。分别连接到彼此相邻的存储单元的存储器栅极的存储栅极线通过其间的源极区域彼此不电连接。每个选择栅极线具有在X方向上延伸的第一部分和其一端连接到第一部分并沿Y方向延伸的第二部分9b。存储栅极线在其选择栅线的相应侧壁上形成有介于其间的绝缘膜。存储栅极线具有接触部分，该接触部分在选择栅极线的第二部分上方在X方向上延伸到元件隔离区域上方，并且通过塞子连接到其对应的布线，所述插头埋设形成在触点上的接触孔部分。

75. 发明申请

US20060022260A1 Semiconductor device and manufacturing method of semiconductor device 失效
公开(公告)号：US20060022260A1
公开(公告)日：2006-02-02
申请号：US11182013
申请日：2005-07-15
申请人： Digh Hisamoto , Kan Yasui , Shinichiro Kimura , Tetsuya Ishimaru
发明人： Digh Hisamoto , Kan Yasui , Shinichiro Kimura , Tetsuya Ishimaru
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , G11C16/0433 , H01L21/2815 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/1203 , H01L29/66825 , H01L29/66833 , H01L29/792
摘要： Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down.

76. 发明申请

US20050285181A1 Non-volatil semiconductor memory device and writing method thereof 有权
标题翻译：非挥发性半导体存储器件及其写入方法
公开(公告)号：US20050285181A1
公开(公告)日：2005-12-29
申请号：US11147243
申请日：2005-06-08
申请人： Kan Yasui , Digh Hisamoto , Toshihiro Tanaka , Takashi Yamaki
发明人： Kan Yasui , Digh Hisamoto , Toshihiro Tanaka , Takashi Yamaki
IPC分类号： G11C16/02 , G11C16/04 , G11C16/34 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3418 , G11C16/0466 , G11C16/3427 , H01L27/115 , H01L29/4232 , H01L29/792
摘要： In a non-volatile semiconductor memory device using a charge storage film, it is intended to prevent a sequence disturb such as an erroneous write or erase of another memory cell on one and same word line which occurs depending on a bias transition path in stand-by state and write state. In connection with rise and fall of a word line bias, the present invention adopts a procedure such that a diffusion region voltage Vs on a memory transistor side is changed, and after the voltage Vs passes a certain intermediate value Vsx, a gate voltage Vmg of the memory transistor is changed. Alternatively, there is adopted a procedure such that the gate voltage Vmg of the memory transistor is changed, and after the voltage Vmg passes a certain intermediate value Vmgx, the diffusion layer voltage Vs on the memory transistor side is changed. The values of Vsx and Vmgx are determined from the magnitude of the electric field in a gate insulating film not causing FN tunneling electron injection that causes a change in threshold voltage and the magnitude of a potential barrier against holes not causing BTBT hot hole injection.
摘要翻译：在使用电荷存储膜的非易失性半导体存储器件中，旨在防止在根据独立的偏置过渡路径发生的同一字线上的另一个存储单元的错误写入或擦除的序列干扰，按状态和写状态。关于字线偏差的上升和下降，本发明采用使存储晶体管侧的扩散区电压Vs变化的过程，在电压Vs经过一定的中间值Vsx之后，栅极电压Vmg为存储晶体管被改变。或者，采用使存储晶体管的栅极电压Vmg改变的过程，并且在电压Vmg经过一定的中间值Vmgx之后，存储晶体管侧的扩散层电压Vs被改变。 Vsx和Vmgx的值由栅极绝缘膜中不引起FN隧穿电子注入的电场的大小确定，导致阈值电压的变化以及针对未引起BTBT热空穴注入的孔的势垒的大小。

77. 发明授权

US08810946B2 Energy-assisted magnetic recording head and magnetic recording device 有权
标题翻译：能量磁记录头和磁记录装置
公开(公告)号：US08810946B2
公开(公告)日：2014-08-19
申请号：US13641239
申请日：2011-03-28
申请人： Kan Yasui , Harukazu Miyamoto , Masukazu Igarashi
发明人： Kan Yasui , Harukazu Miyamoto , Masukazu Igarashi
IPC分类号： G11B5/127
CPC分类号： G11B5/3146 , G11B5/1278 , G11B5/3116 , G11B5/314 , G11B5/315 , G11B2005/0024
摘要： A microwave-assisted magnetic recording system configured to perform magnetic recording with high density, including a high-frequency magnetic field generation element whose width is narrower than a track width of a main pole. A magnetic field vector from the main pole is perpendicularly incident on a film surface of the high-frequency magnetic field generating unit, by a shield material arranged to have a high magnetic permeability so that the main pole magnetic field is corrected and induced, and a hard bias layer to which a desired static magnetic field is added. Areas having high magnetic field gradients overlap each other by performing an offset of the high-frequency magnetic field generating unit of the magnetic head from the central line of the main pole.
摘要翻译：一种被配置为执行高密度磁记录的微波辅助磁记录系统，包括宽度窄于主极的轨道宽度的高频磁场产生元件。来自主极的磁场矢量垂直入射在高频磁场产生单元的膜表面上，通过屏蔽材料被布置成具有高导磁率，使得主极磁场被校正和感应，并且添加了期望的静磁场的硬偏压层。通过从主极的中心线执行磁头的高频磁场产生单元的偏移，具有高磁场梯度的区域彼此重叠。

78. 发明申请

US20130140622A1 NONVOLATILE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20130140622A1
公开(公告)日：2013-06-06
申请号：US13755348
申请日：2013-01-31
申请人： Kenichi Akita , Daisuke Okada , Keisuke Kuwahara , Yasufumi Morimoto , Yasuhiro Shimamoto , Kan Yasui , Tsuyoshi Arigane , Tetsuya Ishimaru
发明人： Kenichi Akita , Daisuke Okada , Keisuke Kuwahara , Yasufumi Morimoto , Yasuhiro Shimamoto , Kan Yasui , Tsuyoshi Arigane , Tetsuya Ishimaru
IPC分类号： H01L29/792 , H01L29/66
CPC分类号： H01L29/66833 , H01L27/115 , H01L27/11563 , H01L27/11568 , H01L29/792
摘要： A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.

79. 发明授权

US08390053B2 Nonvolatile semiconductor device including a field effect transistor having a charge storage layer of predetermined length 失效
标题翻译：包括具有预定长度的电荷存储层的场效应晶体管的非易失性半导体器件
公开(公告)号：US08390053B2
公开(公告)日：2013-03-05
申请号：US12188412
申请日：2008-08-08
申请人： Kenichi Akita , Daisuke Okada , Keisuke Kuwahara , Yasufumi Morimoto , Yasuhiro Shimamoto , Kan Yasui , Tsuyoshi Arigane , Tetsuya Ishimaru
发明人： Kenichi Akita , Daisuke Okada , Keisuke Kuwahara , Yasufumi Morimoto , Yasuhiro Shimamoto , Kan Yasui , Tsuyoshi Arigane , Tetsuya Ishimaru
IPC分类号： H01L29/792
CPC分类号： H01L29/66833 , H01L27/115 , H01L27/11563 , H01L27/11568 , H01L29/792
摘要： A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.
摘要翻译：插入在存储栅电极和半导体衬底之间的电荷存储层形成为比存储栅电极的栅极长度或绝缘膜的长度短，以使电荷存储层和源极区域的重叠量成为小于40nm。因此，在写入状态下，由于在电荷存储层中局部存在的电子和空穴的横向的移动减少，因此可以降低保持高温时的阈值电压的变化。此外，有效沟道长度为30nm以下，以减少空穴的表观量，使得电子与电荷存储层中的空穴的耦合减小; 因此，可以降低在室温下保持时的阈值电压的变化。

80. 发明授权

US08193053B2 Integrated semiconductor nonvolatile storage device 有权
标题翻译：集成半导体非易失性存储装置
公开(公告)号：US08193053B2
公开(公告)日：2012-06-05
申请号：US12763402
申请日：2010-04-20
申请人： Digh Hisamoto , Shin'ichiro Kimura , Daiske Okada , Kan Yasui
发明人： Digh Hisamoto , Shin'ichiro Kimura , Daiske Okada , Kan Yasui
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0425 , H01L21/28282 , H01L27/11568 , H01L29/792
摘要： An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times.In the case of conventional nonvolatile semiconductor storage devices having a split-gate structure, there is a tradeoff between the read current and the maximum allowable number of reprogramming operations. To overcome this problem, an integrated semiconductor nonvolatile storage device of the present invention is configured such that memory cells having different memory gate lengths are integrated on the same chip. This allows the device to be read at high speed and reprogrammed an increased number of times.
摘要翻译：本发明的目的是提供一种可以高速读取并重新编程次数增加的集成半导体非易失性存储装置。在具有分割栅结构的常规非易失性半导体存储器件的情况下，读取电流和最大可允许重编程操作次数之间存在权衡。为了克服这个问题，本发明的集成半导体非易失性存储装置被配置为使得具有不同存储器栅极长度的存储单元集成在同一芯片上。这允许以高速读取设备并重新编程增加的次数。

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