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71. 发明申请

US20080288725A1 METHOD AND APPARATUS FOR CACHE TRANSACTIONS IN A DATA PROCESSING SYSTEM 审中-公开
公开(公告)号：US20080288725A1
公开(公告)日：2008-11-20
申请号：US11748353
申请日：2007-05-14
申请人： William C. Moyer , Michael D. Snyder
发明人： William C. Moyer , Michael D. Snyder
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F11/3656
摘要： A plurality of new snoop transaction types are described. Some include address information in the requests, and others include cache entry information in the requests. Some responses include tag address information, and some do not. Some provide tag address content on the data bus lines during the data portion of the transaction. These new snoop transaction types are very helpful during debug of a data processing system.

72. 发明授权

US07415558B2 Communication steering for use in a multi-master shared resource system 有权
标题翻译：用于多主共享资源系统的通信指导
公开(公告)号：US07415558B2
公开(公告)日：2008-08-19
申请号：US11610956
申请日：2006-12-14
申请人： Arnaldo R. Cruz , John J. Vaglica , William C. Moyer , Tuongvu V. Nguyen
发明人： Arnaldo R. Cruz , John J. Vaglica , William C. Moyer , Tuongvu V. Nguyen
IPC分类号： G06F13/24 , G06F13/00
CPC分类号： G06F13/385 , G06F13/24 , G06F2213/0042
摘要： New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.
摘要翻译：需要用于在多个主机（12,14）和一个或多个共享资源（24,30,100）之间提供通信的新方法。可能需要共享的资源的一个例子是符合通用串行总线（USB）标准（100）的电路。 USB规范将USB端点定义为位于USB设备中的数据和控制通道。在一些情况下，期望具有由一个处理器控制的一定数量的端点以及由不同处理器控制的其他端点，从而提供对所有端点的共享控制。电路（402,417,480）可用于为诸如中断的附加信号提供转向。其他共享资源（24,30）可以使用更集中的电路（36）来执行附加信号的转向功能。

73. 发明授权

US07404019B2 Method and apparatus for endianness control in a data processing system 有权
标题翻译：数据处理系统中字节序控制的方法和装置
公开(公告)号：US07404019B2
公开(公告)日：2008-07-22
申请号：US10857208
申请日：2004-05-26
申请人： William C. Moyer , Michael D. Fitzsimmons
发明人： William C. Moyer , Michael D. Fitzsimmons
IPC分类号： G06F13/12 , G06F3/00 , G06F13/00
CPC分类号： G06F13/4013 , G06F21/85 , G06F2221/2113 , G06F2221/2141
摘要： A method for providing endianness control in a data processing system includes initiating an access which accesses a peripheral, providing a first endianness control that corresponds to the peripheral, and completing the access using the endianness control to affect the endianness order of the information transferred during the access. In one embodiment, the first endianness control overrides a default endianness corresponding to the access. The default endianness may be provided by a master endianness control corresponding to a master requesting the current access. A data processing system includes a first bus master, first and second peripherals, first endianness control corresponding to the first peripheral and second endianness control corresponding to the second peripheral, and control circuitry which uses the first endianness control to control endianness for an access between the first bus master and the first peripheral. In one embodiment, the data processing system may include multiple masters.
摘要翻译：一种用于在数据处理系统中提供字节序控制的方法包括发起访问外围设备的访问，提供与外设相对应的第一字节序列控制，并使用字节序控制来完成访问，以影响在该时间间隔期间传送的信息的字节顺序访问。在一个实施例中，第一字节序列控制覆盖对应于访问的默认字节顺序。默认字节顺序可以由对应于请求当前访问的主机的主字节顺序控制来提供。数据处理系统包括第一总线主机，第一和第二外围设备，对应于与第二外围设备相对应的第一外设和第二终端控制的第一字节序列控制;以及控制电路，其使用第一字节序列控制来控制字节顺序第一个总线主人和第一个外围设备。在一个实施例中，数据处理系统可以包括多个主器件。

74. 发明授权

US07376807B2 Data processing system having address translation bypass and method therefor 有权
标题翻译：具有地址转换旁路的数据处理系统及其方法
公开(公告)号：US07376807B2
公开(公告)日：2008-05-20
申请号：US11360926
申请日：2006-02-23
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0292
摘要： In a data processing system a processor including processing logic performs data processing. An address translator that is coupled to the processing logic performs address translation and a method thereof. The address translator receives a logical address and converts the logical address to both a physical address and one or more address attributes. Bypass circuitry that is coupled to the address translator selectively provides the logical address as a translated address of the logical address which was received. In order to speed up the memory address translation, the logical address is selectively provided as the translated address prior to providing the one or more address attributes associated with the logical address.
摘要翻译：在数据处理系统中，包括处理逻辑的处理器执行数据处理。耦合到处理逻辑的地址转换器执行地址转换及其方法。地址转换器接收逻辑地址并将逻辑地址转换为物理地址和一个或多个地址属性。耦合到地址转换器的旁路电路选择性地将逻辑地址提供为所接收的逻辑地址的翻译地址。为了加速存储器地址转换，在提供与逻辑地址相关联的一个或多个地址属性之前，逻辑地址被选择性地提供为转换的地址。

75. 发明授权

US07315932B2 Data processing system having instruction specifiers for SIMD register operands and method thereof 有权
标题翻译：具有用于SIMD寄存器操作数的指令说明符的数据处理系统及其方法
公开(公告)号：US07315932B2
公开(公告)日：2008-01-01
申请号：US10657331
申请日：2003-09-08
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F15/80 , G06F15/82
CPC分类号： G06F9/30043 , G06F9/30036 , G06F9/30109 , G06F9/30112
摘要： Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be used to indicate a maximum number of vector elements that may be transferred to or from a single register within a register file. Also, the instructions may use a variety of different addressing modes. The memory element size may be specified independently from the register element size such that source and destination sizes may differ within an instruction. With some instructions, a vector stream may be initiated and conditionally enqueued or dequeued. Truncation or rounding fields may be provided such that source data elements may be truncated or rounded when transferred. Also, source data elements may be sign- or unsigned-extended when transferred.
摘要翻译：可以使用各种加载和存储指令来在寄存器文件和存储器中的寄存器之间传送多个向量元素。可以使用cnt参数来指示要传送到存储器或从存储器传送的元素的总数，并且可以使用rcnt参数来指示可以传送到寄存器文件中的单个寄存器的向量元素的最大数量。此外，指令可以使用各种不同的寻址模式。可以独立于寄存器元件大小指定存储器元件大小，使得源和目标大小在指令内可能不同。通过一些指令，可以启动向量流并有条件地排队或出队。可以提供截断或舍入字段，使得源数据元素在被传送时可以被截断或舍入。此外，源数据元素在传输时可以是符号或无符号扩展的。

76. 发明申请

US20070300044A1 METHOD AND APPARATUS FOR INTERFACING A PROCESSOR AND COPROCESSOR 有权
公开(公告)号：US20070300044A1
公开(公告)日：2007-12-27
申请号：US11426633
申请日：2006-06-27
申请人： William C. Moyer , Kevin B. Traylor
发明人： William C. Moyer , Kevin B. Traylor
IPC分类号： G06F15/00
CPC分类号： G06F9/3877 , G06F9/3001 , G06F9/3824
摘要： A coprocessor (14) may be used to perform one or more specialized operations that can be off-loaded from a primary or general purpose processor (12). It is important to allow efficient communication and interfacing between the processor (12) and the coprocessor (14). In one embodiment, a coprocessor (14) generates and provides instructions (200, 220) to an instruction pipe (20) in the processor (12). Because the coprocessor (14) generated instructions are part of the standard instruction set of the processor (12), cache (70) coherency is easy to maintain. Also, circuitry (102) in coprocessor (14) may perform an operation on data while circuitry (106) in coprocessor (14) is concurrently generating processor instructions (200, 220).

77. 发明授权

US07228401B2 Interfacing a processor to a coprocessor in which the processor selectively broadcasts to or selectively alters an execution mode of the coprocessor 有权
标题翻译：将处理器连接到协处理器，其中处理器选择性地广播或选择性地改变协处理器的执行模式
公开(公告)号：US07228401B2
公开(公告)日：2007-06-05
申请号：US10054577
申请日：2001-11-13
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F15/163
CPC分类号： G06F9/3877
摘要： The present invention relates generally to interfacing a processor with at least one coprocessor. One embodiment relates to a processor having a set of broadcast specifiers which it uses to selectively broadcast an operand that is being written to a register within the processor to a coprocessor communication bus. Each broadcast specifier may therefore include a broadcast indicator corresponding to each general purpose register of the processor. An alternate embodiment may also use the concept of broadcast regions where each broadcast region may have a corresponding broadcast specifier where one broadcast specifier may correspond to multiple broadcast regions. Alternatively, in one embodiment, the processor may use broadcast regions independent of the broadcast specifiers where the coprocessor is able to alter its functionality in response to the current broadcast region. In one embodiment, the processor may provide a region specifier via the coprocessor communication bus to indicate the current broadcast region.
摘要翻译：本发明一般涉及将处理器与至少一个协处理器进行接口。一个实施例涉及具有一组广播说明符的处理器，其用于选择性地将正在写入处理器内的寄存器的操作数广播到协处理器通信总线。因此，每个广播说明符可以包括对应于处理器的每个通用寄存器的广播指示符。替代实施例也可以使用广播区域的概念，其中每个广播区域可以具有相应的广播说明符，其中一个广播说明符可以对应于多个广播区域。或者，在一个实施例中，处理器可以使用独立于广播指定符的广播区域，其中协处理器能够响应于当前广播区域而改变其功能。在一个实施例中，处理器可以经由协处理器通信总线提供区域说明符以指示当前广播区域。

78. 发明授权

US07185148B2 Read access and storage circuitry read allocation applicable to a cache 有权
标题翻译：读访问和存储电路读取分配适用于缓存
公开(公告)号：US07185148B2
公开(公告)日：2007-02-27
申请号：US11197830
申请日：2005-08-05
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F11/3648 , G06F12/0888 , G06F12/126
摘要： A read allocation indicator (e.g. read allocation signal 30) is provided to storage circuitry (e.g. cache 22) to selectively determine whether read allocation will be performed for the read access. Read allocation may include modification of the information content of the cache (22) and/or modification of the read replacement algorithm state implemented by the read allocation circuitry (70) in cache (22). For certain types of debug operations, it may be very useful to provide a read allocation indicator that ensures that no unwanted modification are made to the storage circuitry during a read access. Yet other types of debug operations may want the storage circuitry to be modified in the standard manner when a read access occurs.
摘要翻译：将读分配指示符（例如，读分配信号30）提供给存储电路（例如，高速缓存22），以选择性地确定是否将对读访问执行读分配。读分配可以包括对高速缓存（22）中的读分配电路（70）实现的对高速缓存（22）的信息内容的修改和/或修改读取的替换算法状态。对于某些类型的调试操作，提供读取分配指示符可能是非常有用的，该读取分配指示符确保在读取访问期间不对存储电路进行不需要的修改。当读取访问发生时，其他类型的调试操作可能希望以标准方式修改存储电路。

79. 发明授权

US07099973B2 Method and system of bus master arbitration 有权
标题翻译：总线主控仲裁的方法和系统
公开(公告)号：US07099973B2
公开(公告)日：2006-08-29
申请号：US10402165
申请日：2003-03-26
申请人： William C. Moyer , Michael D. Fitzsimmons , Brett W. Murdock
发明人： William C. Moyer , Michael D. Fitzsimmons , Brett W. Murdock
IPC分类号： G06F13/36 , G06F3/00
CPC分类号： G06F13/364
摘要： A system (100) having a plurality of bus masters (111–113) coupled to an arbiter (150) is disclosed. An arbiter (150) is coupled to a first storage location (151) and a second storage location (152), where the first and second storage locations store bus master parking information for a system bus (141). The arbiter (150) receives a parking context indicator (131) that is used to select one of the first and second storage locations (151, 152) to provide bus master parking information to the arbiter (150).
摘要翻译：公开了具有耦合到仲裁器（150）的多个总线主机（111-113）的系统（100）。仲裁器（150）耦合到第一存储位置（151）和第二存储位置（152），其中第一和第二存储位置存储用于系统总线（141）的总线主站停车信息。仲裁器（150）接收用于选择第一和第二存储位置（151,152）之一以便向仲裁器（150）提供总线主机停车信息的停车上下文指示器（131）。

80. 发明授权

US06832280B2 Data processing system having an adaptive priority controller 有权
标题翻译：数据处理系统具有自适应优先级控制器
公开(公告)号：US06832280B2
公开(公告)日：2004-12-14
申请号：US09927123
申请日：2001-08-10
申请人： Afzal M. Malik , William C. Moyer , William C. Bruce, Jr.
发明人： Afzal M. Malik , William C. Moyer , William C. Bruce, Jr.
IPC分类号： G06F1200
CPC分类号： G06F13/18 , G06F13/36
摘要： The present invention relates generally to data processors and more specifically, to data processors having an adaptive priority controller. One embodiment relates to a method for prioritizing requests in a data processor (12) having a bus interface unit (32). The method includes receiving a first request from a first bus requesting resource (e.g. 30) and a second request from a second bus requesting resource (e.g. 28), and using a threshold corresponding to the first or second bus requesting resource to prioritize the first and second requests. The first and second bus requesting resources may be a push buffer (28) for a cache, a write buffer (30), or an instruction prefetch buffer (24). According to one embodiment, the bus interface unit (32) includes a priority controller (34) that receives the first and second requests, assigns the priority, and stores the threshold in a threshold register (66). The priority controller (34) may also include one or more threshold registers (66), subthreshold registers (68), and control registers (70).
摘要翻译：本发明一般涉及数据处理器，更具体地说，涉及具有自适应优先级控制器的数据处理器。一个实施例涉及一种用于在具有总线接口单元（32）的数据处理器（12）中对请求进行优先级排序的方法。该方法包括从第一总线接收请求资源（例如30）的第一请求和来自第二总线请求资源（例如28）的第二请求，以及使用对应于第一或第二总线请求资源的阈值来优先处理第一和/ 第二个请求第一和第二总线请求资源可以是用于高速缓冲存储器的缓冲器（28），写入缓冲器（30）或指令预取缓冲器（24）。根据一个实施例，总线接口单元（32）包括优先级控制器（34），其接收第一和第二请求，分配优先级，并将阈值存储在阈值寄存器（66）中。优先级控制器（34）还可以包括一个或多个阈值寄存器（66），子阈值寄存器（68）和控制寄存器（70）。

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