专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US08479085B2 Memory system with error correction decoder architecture having reduced latency and increased throughput 有权
标题翻译：具有纠错解码器架构的存储器系统具有降低的延迟和增加的吞吐量
公开(公告)号：US08479085B2
公开(公告)日：2013-07-02
申请号：US12191458
申请日：2008-08-14
申请人： Nam Phil Jo , Jun Jin Kong , Chan Ho Yoon , Dong Hyuk Chae , Kyoung Lae Cho
发明人： Nam Phil Jo , Jun Jin Kong , Chan Ho Yoon , Dong Hyuk Chae , Kyoung Lae Cho
IPC分类号： G06F11/00
CPC分类号： G06F11/1068 , G11C7/1006 , G11C2029/0411
摘要： A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.
摘要翻译：存储器系统包括：包括纠错解码器的存储器控制器。纠错解码器包括：解复用器，适于接收数据并将数据解复用为第一组数据和第二组数据; 用于分别存储第一和第二组数据的第一和第二缓冲存储器; 误差检测器; 误差校正器以及多路复用器，其适于多路复用第一组数据和第二组数据，并将复用的数据提供给误差校正器。当误差校正器校正第一组数据中的错误时，误差检测器检测存储在第二缓冲存储器中的第二组数据中的错误。

72. 发明申请

US20120131266A1 MEMORY CONTROLLER, DATA STORAGE SYSTEM INCLUDING THE SAME, METHOD OF PROCESSING DATA 审中-公开
标题翻译：存储器控制器，包括其的数据存储系统，处理数据的方法
公开(公告)号：US20120131266A1
公开(公告)日：2012-05-24
申请号：US13301961
申请日：2011-11-22
申请人： Kyoung Lae CHO , Kwang Ho Kim , Jun Jin Kong , Jin Kyu Kim
发明人： Kyoung Lae CHO , Kwang Ho Kim , Jun Jin Kong , Jin Kyu Kim
IPC分类号： G06F12/00
CPC分类号： G06F12/04 , G06F2212/401
摘要： A data storage system includes a controller configured to receive data and data information about the data from a host, analyze the data information, detect whether the data has been compressed, and compress the data according to a detection result; and a nonvolatile memory device configured to store the data compressed by the controller and information about whether the data has been compressed. The controller includes a buffer configured to temporarily store the data and the data information received from the host, an analyzer configured to output, based on an analysis result, a compression control flag that indicates whether the data has been compressed, and a compressor configured to selectively compress or bypass the data based on the compression control flag, and to transmit the data to the nonvolatile memory device.
摘要翻译：数据存储系统包括控制器，被配置为从主机接收关于数据的数据和数据信息，分析数据信息，检测数据是否已被压缩，并根据检测结果压缩数据; 以及非易失性存储装置，被配置为存储由所述控制器压缩的数据以及关于所述数据是否被压缩的信息。所述控制器包括被配置为临时存储从所述主机接收到的数据和数据信息的缓冲器，分析器，被配置为基于分析结果输出指示所述数据是否已被压缩的压缩控制标志，以及压缩器，基于压缩控制标志选择性地压缩或旁路数据，并将数据发送到非易失性存储器件。

73. 发明授权

US07706181B2 Multi-bit programming device and method using single-bit memory cells 有权
标题翻译：多位编程设备和使用单位存储单元的方法
公开(公告)号：US07706181B2
公开(公告)日：2010-04-27
申请号：US11896349
申请日：2007-08-31
申请人： Sung-Jae Byun , Dong Hyuk Chae , Kyoung Lae Cho , Jun Jin Kong , Young Hwan Lee , Seung Jae Lee , Nam Phil Jo , Dong Ku Kang
发明人： Sung-Jae Byun , Dong Hyuk Chae , Kyoung Lae Cho , Jun Jin Kong , Young Hwan Lee , Seung Jae Lee , Nam Phil Jo , Dong Ku Kang
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5628 , G11C2211/5621 , G11C2211/5641
摘要： A multi-bit programming device and method for a non-volatile memory are provided. In one example embodiment, a multi-bit programming device may include a multi-bit programming unit configured to multi-bit program original multi-bit data to a target memory cell in a memory cell array, and a backup programming unit configured to select backup memory cells in the memory cell array with respect to each bit of the original multi-bit data, and program each bit of the original multi-bit data to a respective one of the selected backup memory cells.
摘要翻译：提供了一种用于非易失性存储器的多位编程设备和方法。在一个示例实施例中，多位编程设备可以包括多位编程单元，其被配置为将原始多位数据多位地编程到存储单元阵列中的目标存储器单元，以及备份编程单元，被配置为选择备份相对于原始多位数据的每个位存储单元阵列中的存储器单元，以及将原始多位数据的每个位编程到所选择的备份存储器单元中的相应一个。

74. 发明授权

US08179718B2 Memory device and memory programming method 有权
标题翻译：存储器和存储器编程方法
公开(公告)号：US08179718B2
公开(公告)日：2012-05-15
申请号：US12318560
申请日：2008-12-31
申请人： Kyoung Lae Cho , Yoon Dong Park , Jun Jin Kong , Yong June Kim
发明人： Kyoung Lae Cho , Yoon Dong Park , Jun Jin Kong , Yong June Kim
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C29/00 , G11C2211/5621
摘要： Provided are memory devices and memory programming methods. A memory device may include: a multi-level cell array that includes a plurality of multi-level cells; a programming unit that programs a first data page in the plurality of multi-level cells and programs a second data page in a multi-level cell from among the plurality of multi-level cells in which the first data page is programmed; an error analysis unit that analyzes read error information corresponding to the first data page based on a read voltage level to determine whether to correct a read error based on the analyzed read error information; and a controller that adjusts the read voltage level of the first data page depending on the determination result. Through this, it is possible to reduce an error occurrence when reading and/or programming a data page.
摘要翻译：提供的是存储器件和存储器编程方法。存储器件可以包括：多级单元阵列，其包括多个多电平单元; 编程单元，其对所述多个多电平单元中的第一数据页进行编程，并从所述第一数据页被编程的所述多个多电平单元中编程多电平单元中的第二数据页; 误差分析单元，其基于读取电压电平分析与所述第一数据页相对应的读取错误信息，以基于所分析的读取错误信息来确定是否校正读取错误; 以及控制器，其根据确定结果调整第一数据页的读取电压电平。通过这种方式，可以在读取和/或编程数据页时减少错误发生。

75. 发明申请

US20090091991A1 Apparatuses and methods for multi-bit programming 失效
标题翻译：多位编程的设备和方法
公开(公告)号：US20090091991A1
公开(公告)日：2009-04-09
申请号：US12073100
申请日：2008-02-29
申请人： Kyoung Lae Cho , Jun Jin Kong , Jong Han Kim , Seung Hoon Lee , Young Hwan Lee , Sung-Jae Byun , Ju Hee Park
发明人： Kyoung Lae Cho , Jun Jin Kong , Jong Han Kim , Seung Hoon Lee , Young Hwan Lee , Sung-Jae Byun , Ju Hee Park
IPC分类号： G11C7/00
CPC分类号： G11C11/5628 , G11C2211/5647
摘要： Multi-bit programming apparatuses and methods are provided. A multi-bit programming apparatus includes a page buffer configured to store first data of the page programming operation, an input control unit configured to determine whether to invert the first data based on a number of bits having a first value and a number of bits having a second value. The input control unit is further configured to invert the first data to generate second data if the number of bits having a first value is greater than the number of bits having a second value and store the second data in the page buffer. The multi-bit programming apparatus further includes a page programming unit configured to program the second data stored in the page buffer in at least one multi-bit cell.
摘要翻译：提供了多位编程设备和方法。一种多位编程装置，包括：页缓冲器，被配置为存储页编程操作的第一数据;输入控制单元，被配置为基于具有第一值的比特数和具有多个比特的比特数来确定是否反转第一数据第二个值。输入控制单元还被配置为如果具有第一值的比特数大于具有第二值的比特数，并且将第二数据存储在页面缓冲器中，则反转第一数据以产生第二数据。该多位编程装置还包括：页面编程单元，被配置为在至少一个多位单元中对存储在页缓冲器中的第二数据进行编程。

76. 发明授权

US09009390B2 Method for changing read parameter for improving read performance and apparatuses using the same 有权
标题翻译：用于改变读取参数以提高读取性能的方法和使用其的装置
公开(公告)号：US09009390B2
公开(公告)日：2015-04-14
申请号：US13238749
申请日：2011-09-21
申请人： Seong Hyeog Choi , Hong Rak Son , Kyoung Lae Cho , Jun Jin Kong , Sang Hoon Lee
发明人： Seong Hyeog Choi , Hong Rak Son , Kyoung Lae Cho , Jun Jin Kong , Sang Hoon Lee
IPC分类号： G06F13/00 , G06F13/28 , G11C16/02 , G11C16/06 , G11C29/42 , G11C16/00 , G11C11/56 , G11C16/34
CPC分类号： G11C16/02 , G06F13/00 , G11C11/5642 , G11C16/00 , G11C16/06 , G11C16/3418 , G11C16/349 , G11C29/42
摘要： A memory system including a non-volatile memory device and a memory controller is provided. When a read operation on a first data initially output from the non-volatile memory device during a first read operation is successful, the memory controller may change a read voltage for reading a second data stored in the non-volatile memory device during a second read operation.
摘要翻译：提供了包括非易失性存储器件和存储器控制器的存储器系统。当在第一次读取操作期间最初从非易失性存储器件输出的第一数据的读取操作成功时，存储器控制器可以在第二次读取期间改变用于读取存储在非易失性存储器件中的第二数据的读取电压操作。

77. 发明申请

US20120182163A1 DATA COMPRESSION DEVICES, OPERATING METHODS THEREOF, AND DATA PROCESSING APPARATUSES INCLUDING THE SAME 有权
标题翻译：数据压缩装置，其操作方法和包括其的数据处理装置
公开(公告)号：US20120182163A1
公开(公告)日：2012-07-19
申请号：US13353984
申请日：2012-01-19
申请人： Kyoung Lae Cho , Chan Ho Yoon , Jun Jin Kong , Pil Sang Yoon
发明人： Kyoung Lae Cho , Chan Ho Yoon , Jun Jin Kong , Pil Sang Yoon
IPC分类号： H03M7/30
CPC分类号： H03M7/30 , H03M7/6088
摘要： A method of operating a data compression device includes analyzing data using an analyzer and generating a result of the analysis, while the data is buffered by an input buffer, and selectively compressing the buffered data according to the result of the analysis. A data compression device includes a data pattern analyzer configured to analyze data transmitted to an input buffer, and generate an analysis code based on the analysis of the data; and a data compression manager configured to selectively compress the data in the input buffer based on the analysis code.
摘要翻译：操作数据压缩装置的方法包括使用分析器分析数据并产生分析结果，同时数据由输入缓冲器缓冲，并根据分析结果选择性地压缩缓冲的数据。数据压缩装置包括数据模式分析器，被配置为分析发送到输入缓冲器的数据，并且基于数据的分析生成分析代码; 以及数据压缩管理器，被配置为基于分析代码选择性地压缩输入缓冲器中的数据。

78. 发明授权

US07903459B2 Memory devices and methods for determining data of bit layers based on detected error bits 有权
标题翻译：用于基于检测到的错误位来确定位层的数据的存储器件和方法
公开(公告)号：US07903459B2
公开(公告)日：2011-03-08
申请号：US12232150
申请日：2008-09-11
申请人： Donghun Yu , Kyoung Lae Cho , Dongku Kang , Dong Hyuk Chae , Jun Jin Kong
发明人： Donghun Yu , Kyoung Lae Cho , Dongku Kang , Dong Hyuk Chae , Jun Jin Kong
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C29/00 , G11C2029/0411 , G11C2211/5621
摘要： Disclosed are a memory device and a memory data reading method. The memory device may include a multi-bit cell array, a threshold voltage detecting unit configured to detect first threshold voltage intervals including threshold voltages of multi-bit cells of the multi-bit cell array from among a plurality of threshold voltage intervals, a determination unit configured to determine data of a first bit layer based on the detected first threshold voltage intervals, and an error detection unit configured to detect an error bit of the data of the first bit layer. In this instance, the determination unit may determine data of a second bit layer using a second threshold voltage interval having a value of the first bit layer different from the detected error bit and being nearest to a threshold voltage of a multi-bit cell corresponding to the detected error bit.
摘要翻译：公开了一种存储器件和存储器数据读取方法。存储器件可以包括多位单元阵列，阈值电压检测单元，被配置为从多个阈值电压间隔中检测包括多位单元阵列的多位单元的阈值电压的第一阈值电压间隔，单元，被配置为基于检测到的第一阈值电压间隔来确定第一位层的数据;以及错误检测单元，被配置为检测第一位层的数据的错误位。在这种情况下，确定单元可以使用具有与检测到的错误位不同的第一位层的值的第二阈值电压间隔来确定第二位层的数据，并且最接近对应于多个位单元的阈值电压检测到错误位。

79. 发明授权

US07885108B2 Memory programming method 有权
标题翻译：内存编程方法
公开(公告)号：US07885108B2
公开(公告)日：2011-02-08
申请号：US12382176
申请日：2009-03-10
申请人： Kyoung Lae Cho , Dong Hyuk Chae , Jun Jin Kong
发明人： Kyoung Lae Cho , Dong Hyuk Chae , Jun Jin Kong
IPC分类号： G11C16/00
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3418
摘要： A memory programming method may include identifying at least one of a plurality of memory cells with a threshold voltage to be changed based on a pattern of data to be programmed in the at least one of the plurality of memory cells, applying a program condition voltage to the at least one identified memory cell until the threshold voltage of the at least one identified memory cell is included in a first threshold voltage interval, to thereby adjust the threshold voltage of the at least one identified memory cell, and programming the data in the at least one identified memory cell with the adjusted threshold voltage.
摘要翻译：存储器编程方法可以包括基于要在所述多个存储器单元中的至少一个存储器单元中编程的数据的模式来改变要改变的阈值电压的多个存储器单元中的至少一个，将程序条件电压施加到所述至少一个所识别的存储器单元，直到所述至少一个所识别的存储单元的阈值电压被包括在第一阈值电压间隔内，从而调整所述至少一个识别的存储单元的阈值电压，并且对所述存储单元中的数据进行编程具有调整的阈值电压的至少一个识别的存储器单元。

80. 发明申请

US20090285022A1 Memory programming method 有权
标题翻译：内存编程方法
公开(公告)号：US20090285022A1
公开(公告)日：2009-11-19
申请号：US12382176
申请日：2009-03-10
申请人： Kyoung Lae Cho , Dong Hyuk Chae , Jun Jin Kong
发明人： Kyoung Lae Cho , Dong Hyuk Chae , Jun Jin Kong
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3418
摘要： A memory programming method may include identifying at least one of a plurality of memory cells with a threshold voltage to be changed based on a pattern of data to be programmed in the at least one of the plurality of memory cells, applying a program condition voltage to the at least one identified memory cell until the threshold voltage of the at least one identified memory cell is included in a first threshold voltage interval, to thereby adjust the threshold voltage of the at least one identified memory cell, and programming the data in the at least one identified memory cell with the adjusted threshold voltage.
摘要翻译：存储器编程方法可以包括基于要在所述多个存储器单元中的至少一个存储器单元中编程的数据的模式来改变要改变的阈值电压的多个存储器单元中的至少一个，将程序条件电压施加到所述至少一个所识别的存储器单元，直到所述至少一个所识别的存储单元的阈值电压被包括在第一阈值电压间隔内，从而调整所述至少一个识别的存储单元的阈值电压，并且对所述存储单元中的数据进行编程具有调整的阈值电压的至少一个识别的存储器单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式