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71. 发明授权

US08027644B2 Transceiver system including dual low-noise amplifiers 有权
标题翻译：收发系统包括双低音放大器
公开(公告)号：US08027644B2
公开(公告)日：2011-09-27
申请号：US12881226
申请日：2010-09-14
申请人： Xiaodong Jin , Sehat Sutardja , Lawrence Tse
发明人： Xiaodong Jin , Sehat Sutardja , Lawrence Tse
IPC分类号： H04B1/38
CPC分类号： H04B1/0064 , H04B7/0805
摘要： A transceiver system includes a first receive path with a first antenna configured to receive first signals, a first configuration switch, a first low noise amplifier configured to amplify the first signals, a second configuration switch, and a receiver. The first receive path is selectively configured to supply the amplified first signals to the receiver via the first antenna, the first configuration switch, the first low noise amplifier, and the second configuration switch. A second receive path includes a second antenna configured to receive second signals, a second low noise amplifier configured to amplify the second signals, the second configuration switch, and the receiver. The second receive path (i) includes fewer configuration switches than the first receive path and (ii) is selectively configured to supply the amplified second signals to the receiver via the second antenna, the second low noise amplifier, and the second configuration switch.
摘要翻译：收发机系统包括具有被配置为接收第一信号的第一天线的第一接收路径，第一配置开关，被配置为放大第一信号的第一低噪声放大器，第二配置开关和接收器。第一接收路径被选择性地配置为经由第一天线，第一配置开关，第一低噪声放大器和第二配置开关将放大的第一信号提供给接收器。第二接收路径包括被配置为接收第二信号的第二天线，配置成放大第二信号的第二低噪声放大器，第二配置开关和接收器。第二接收路径（i）包括比第一接收路径更少的配置开关，以及（ii）被选择性地配置为经由第二天线，第二低噪声放大器和第二配置开关将经放大的第二信号提供给接收机。

72. 发明申请

US20110175218A1 PACKAGE ASSEMBLY HAVING A SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：具有半导体基板的封装组件
公开(公告)号：US20110175218A1
公开(公告)日：2011-07-21
申请号：US12973249
申请日：2010-12-20
申请人： Shiann-Ming Liou , Sehat Sutardja , Albert Wu , Chuan-Cheng Cheng , Chien-Chuan Wei
发明人： Shiann-Ming Liou , Sehat Sutardja , Albert Wu , Chuan-Cheng Cheng , Chien-Chuan Wei
IPC分类号： H01L23/34 , H01L21/60
CPC分类号： H01L23/42 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L23/60 , H01L24/11 , H01L24/16 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2224/1403 , H01L2224/14181 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12035 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/15321 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供了一种方法，其包括提供包括半导体材料的半导体衬底，在半导体衬底上形成电介质层，在电介质层上形成互连层，将半导体管芯附着到半导体衬底上，半导体管芯的有源侧到互连层，互连层以引导半导体管芯的电信号。可以描述和/或要求保护其他实施例。

73. 发明授权

US07979224B2 Configurable voltage regulator 有权
标题翻译：可配置电压调节器
公开(公告)号：US07979224B2
公开(公告)日：2011-07-12
申请号：US12862815
申请日：2010-08-25
申请人： Sehat Sutardja
发明人： Sehat Sutardja
IPC分类号： G06F19/00
CPC分类号： H03H7/40 , G06F1/26 , H01L23/66 , H01L2223/5444 , H01L2924/0002 , H03F3/45475 , H03F2200/261 , H03F2203/45138 , H03H7/0153 , H03H11/1291 , H03H11/30 , H01L2924/00
摘要： A configurable semiconductor device includes at least one select pin configured to connect to one of a plurality of impedances. The impedances are external to the configurable semiconductor device and have impedance values within predetermined tolerances. A measurement circuit is connected to the at least one select pin. The measurement circuit is configured to measure electrical characteristics of the plurality of impedances, correlate the electrical characteristics to respective predetermined ranges of impedances, and generate digital output values corresponding to the correlation. A controller is configured to control a characteristic of the configurable semiconductor device based on the digital output values. Spacing between the respective predetermined ranges of impedances is based on the predetermined tolerances.
摘要翻译：可配置的半导体器件包括被配置为连接到多个阻抗中的一个阻抗的至少一个选择引脚。阻抗位于可配置的半导体器件的外部，并且具有在预定公差范围内的阻抗值。测量电路连接到至少一个选择引脚。测量电路被配置为测量多个阻抗的电特性，将电特性与相应的预定范围的阻抗相关联，并产生对应于相关性的数字输出值。控制器被配置为基于数字输出值来控制可配置半导体器件的特性。各个预定阻抗范围之间的间距是基于预定公差。

74. 发明授权

US07960958B2 Voltage regulator feedback protection method and apparatus 有权
标题翻译：稳压器反馈保护方法及装置
公开(公告)号：US07960958B2
公开(公告)日：2011-06-14
申请号：US12398265
申请日：2009-03-05
申请人： Sehat Sutardja
发明人： Sehat Sutardja
IPC分类号： G05F1/56
CPC分类号： H02M1/08 , G05F1/613
摘要： An integrated circuit includes an output terminal. A plurality of feedback terminals receives a feedback signal. A voltage regulator has a feedback input in communication with the plurality of feedback terminals to receive the feedback signal. The voltage regulator has a power output in communication with the output terminal. The voltage regulator is responsive to the feedback signal to generate the power output.
摘要翻译：集成电路包括输出端子。多个反馈终端接收反馈信号。电压调节器具有与多个反馈端子通信的反馈输入，以接收反馈信号。电压调节器具有与输出端子通信的功率输出。电压调节器响应于反馈信号以产生功率输出。

75. 发明授权

US07958292B2 Disk drive system on chip with integrated buffer memory and support for host memory access 有权
标题翻译：带有集成缓冲存储器的磁盘驱动器系统，支持主机内存访问
公开(公告)号：US07958292B2
公开(公告)日：2011-06-07
申请号：US10926486
申请日：2004-08-19
申请人： Sehat Sutardja
发明人： Sehat Sutardja
IPC分类号： G06F13/38
CPC分类号： G06F5/12 , G06F3/0613 , G06F3/0656 , G06F3/0676 , G11B20/10527 , G11B2020/10675
摘要： A circuit for a storage device that communicates with a host device comprises a first high speed interface. A storage controller communicates with the high speed interface. A buffer communicates with the storage controller. The storage device generates storage buffer data during operation. The storage controller is adapted to selectively store the storage buffer data in at least one of the buffer and/or in the host device via the high speed interface. A bridge chip for enterprise applications couples the circuit to an enterprise device.
摘要翻译：用于与主机设备通信的存储设备的电路包括第一高速接口。存储控制器与高速接口通信。缓冲区与存储控制器通信。存储设备在操作期间生成存储缓冲区数据。存储控制器适于经由高速接口选择性地将存储缓冲器数据存储在缓冲器和/或主机设备中的至少一个中。用于企业应用的桥芯片将电路耦合到企业设备。

76. 发明授权

US07885760B2 GPS-based traffic monitoring system 有权
标题翻译：基于GPS的交通监控系统
公开(公告)号：US07885760B2
公开(公告)日：2011-02-08
申请号：US11787296
申请日：2007-04-16
申请人： Sehat Sutardja
发明人： Sehat Sutardja
IPC分类号： G08G7/76
CPC分类号： G08G1/0104 , G01S19/14 , G08G1/01 , G08G1/096775 , G08G1/127 , H04W24/00 , H04W48/08 , H04W64/006 , H04W88/02
摘要： A traffic monitoring system comprises memory for storing map data, a traffic report generating module that receives vector and location data from at least one of cellular phones and vehicles and that generates and transmits traffic reports based on the vector and location data. A map monitoring module includes a path determining module that determines a travel path of the at least one of the cellular phones and the vehicles based on the vector and location data, a comparing module that compares the travel path to roads defined by the map data, and an identifying module that selectively identifies new roads based on the comparison.
摘要翻译：交通监控系统包括用于存储地图数据的存储器，从蜂窝电话和车辆中的至少一个接收向量和位置数据的业务报告生成模块，并且基于向量和位置数据生成和传输业务报告。地图监视模块包括路径确定模块，该路径确定模块基于向量和位置数据确定移动电话和车辆中的至少一个的行进路径;比较模块，其将行进路径与由地图数据定义的道路进行比较; 以及基于比较选择性地识别新道路的识别模块。

77. 发明授权

US07885758B2 GPS-based traffic monitoring system 有权
标题翻译：基于GPS的交通监控系统
公开(公告)号：US07885758B2
公开(公告)日：2011-02-08
申请号：US11637173
申请日：2006-12-11
申请人： Sehat Sutardja
发明人： Sehat Sutardja
IPC分类号： G08G1/00
CPC分类号： G08G1/0104 , G01S19/14 , G08G1/01 , G08G1/096775 , G08G1/127 , H04W24/00 , H04W48/08 , H04W64/006 , H04W88/02
摘要： A traffic monitoring system comprises a traffic estimating module that estimates an average traffic level on the road during prior ones of first periodic periods. A traffic monitoring module estimates a current traffic level on the road during a first portion of a current one of the first periodic periods based on vector and location information received from at least one of cellular phones and vehicles during the first portion. A traffic predicting module predicts traffic levels on the road during a remaining portion of the current one of the first periodic periods based on the average traffic level and the estimated current traffic level during the first portion.
摘要翻译：交通监控系统包括业务估计模块，其在先前的第一周期期间估计道路上的平均业务量。交通监控模块基于在第一部分期间从蜂窝电话和车辆中的至少一个接收的向量和位置信息来估计在第一周期期间的当前时间段的第一部分期间道路上的当前交通等级。交通预测模块基于在第一部分期间的平均业务量和估计的当前业务量来预测在当前第一周期周期的剩余部分期间道路上的业务量。

78. 发明授权

US07884677B2 Method and apparatus for reducing phase noise in an oscillator signal of a Colpitts oscillator 有权
标题翻译：用于降低Colpitts振荡器的振荡器信号中的相位噪声的方法和装置
公开(公告)号：US07884677B2
公开(公告)日：2011-02-08
申请号：US12104050
申请日：2008-04-16
申请人： Sehat Sutardja
发明人： Sehat Sutardja
IPC分类号： H03B5/12
CPC分类号： H03B5/1228 , H03B5/1218 , H03B5/1231 , H03B5/124
摘要： A Colpitts oscillator includes a tank circuit, a first transistor, and a first feedback circuit. The first transistor includes a first region, a second region, and a control region. The first region communicates with the tank circuit. The first feedback circuit communicates with the second region and the control region of the first transistor.
摘要翻译： Colpitts振荡器包括储能电路，第一晶体管和第一反馈电路。第一晶体管包括第一区域，第二区域和控制区域。第一区域与储罐回路连通。第一反馈电路与第一晶体管的第二区域和控制区域通信。

79. 发明申请

US20110018627A1 NESTED TRANSIMPENDANCE AMPLIFIER 有权
标题翻译：嵌入式转换放大器
公开(公告)号：US20110018627A1
公开(公告)日：2011-01-27
申请号：US12857949
申请日：2010-08-17
申请人： Sehat Sutardja
发明人： Sehat Sutardja
IPC分类号： H03F1/00
CPC分类号： H03F1/34 , H03F1/08 , H03F3/08 , H03F3/45179 , H03F3/45475 , H03F3/45928 , H03F2200/331 , H03F2200/36 , H03F2203/45528 , H03F2203/45531 , H03F2203/45652
摘要： A nested transimpedance amplifier circuit includes a first-order nested transimpedance amplifier having an input and an output. The first-order nested transimpedance amplifier is configured to be powered by a first voltage. A charge pump module is configured to receive the first voltage and a second voltage. The second voltage is different from the first voltage. The charge pump module generates a third voltage based on the first voltage and the second voltage. A first operational amplifier has an input and an output. The input of the first operational amplifier communicates with the output of the zero-order transimpedance amplifier, and the first operational amplifier is configured to be powered by the third voltage.
摘要翻译：嵌套跨阻抗放大器电路包括具有输入和输出的一阶嵌套跨阻抗放大器。一阶嵌套跨阻抗放大器被配置为由第一电压供电。电荷泵模块被配置为接收第一电压和第二电压。第二电压与第一电压不同。电荷泵模块基于第一电压和第二电压产生第三电压。第一运算放大器具有输入和输出。第一运算放大器的输入与零级跨阻抗放大器的输出通信，并且第一运算放大器被配置为由第三电压供电。

80. 发明授权

US07872542B2 Variable capacitance with delay lock loop 有权
标题翻译：具有延迟锁定环路的可变电容
公开(公告)号：US07872542B2
公开(公告)日：2011-01-18
申请号：US12180853
申请日：2008-07-28
申请人： Jody Greenberg , Sehat Sutardja
发明人： Jody Greenberg , Sehat Sutardja
IPC分类号： H03B1/00 , H03K7/08
CPC分类号： H03B5/02 , H03B5/04 , H03B5/1215 , H03B5/1228 , H03B5/1265 , H03B2200/005 , H03B2201/0266 , H03J2200/10 , H03K7/08 , H03L1/022 , H03L1/026 , H03L7/07 , H03L7/08 , H03L7/0812 , H03L7/099 , H03L7/22
摘要： An integrated circuit includes a delay lock loop (DLL) circuit that generates incremental delay line signals and a delay line output signal based on a received clock signal. A pulse-width modulation (PWM) control module generates a PWM control signal. A tunable circuit having variable capacitance is controlled based on the delay line output signal, the PWM control signal, and one of the incremental delay line signals.
摘要翻译：集成电路包括延迟锁定环（DLL）电路，其基于接收的时钟信号产生增量延迟线信号和延迟线输出信号。脉冲宽度调制（PWM）控制模块产生PWM控制信号。基于延迟线输出信号，PWM控制信号和增量延迟线信号之一来控制具有可变电容的可调谐电路。

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