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71. 发明授权

US07573249B2 Power array system and method 有权
标题翻译：功率阵列系统及方法
公开(公告)号：US07573249B2
公开(公告)日：2009-08-11
申请号：US11906084
申请日：2007-09-28
申请人： Sehat Sutardja , Runsheng He , Jiancheng Zhang
发明人： Sehat Sutardja , Runsheng He , Jiancheng Zhang
IPC分类号： G05F1/40
CPC分类号： H02M3/157 , H02M1/088 , H02M1/38 , H02M3/158 , H02M3/1588 , H02M2001/0009 , H02M2001/0012 , H02M2001/0025 , H02M2001/0048 , H03K5/1565 , H03K17/122 , H03K17/167 , H03K17/6871 , Y02B70/1466 , Y02B70/1491
摘要： A digital controller that controls an output regulator includes controller sub-blocks that perform sub-functions of the digital controller, wherein at least one of the controller sub-blocks includes at least one of a delay line and a first comparator. A controller monitors output power states of the output regulator and controls flow of power to the at least one of the controller sub-blocks of the digital controller to reduce power consumption of the digital controller during selected ones of the output power states of the output regulator.
摘要翻译：控制输出调节器的数字控制器包括执行数字控制器的子功能的控制器子块，其中控制器子块中的至少一个包括延迟线和第一比较器中的至少一个。控制器监视输出调节器的输出功率状态并且控制到数字控制器的至少一个控制器子块的功率流，以在输出调节器的输出功率状态的选定的一个期间降低数字控制器的功耗。

72. 发明授权

US07528444B2 Efficient transistor structure 有权
标题翻译：高效晶体管结构
公开(公告)号：US07528444B2
公开(公告)日：2009-05-05
申请号：US11586467
申请日：2006-10-25
申请人： Sehat Sutardja
发明人： Sehat Sutardja
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L29/0692 , H01L21/76816 , H01L21/76838 , H01L21/76895 , H01L21/823418 , H01L21/823437 , H01L27/0203 , H01L27/0207 , H01L27/088 , H01L27/105 , H01L29/0696 , H01L29/41758 , H01L29/4238 , H01L29/78 , H01L29/7816
摘要： An integrated circuit comprises a first drain region having a generally rectangular shape. First, second, third and fourth source regions have a generally rectangular shape and that are arranged adjacent to sides of the first drain region. A gate region is arranged between the first, second, third and fourth source regions and the first drain region. First, second, third and fourth substrate contact regions that are arranged adjacent to corners of the first drain region.
摘要翻译：集成电路包括具有大致矩形形状的第一漏区。第一，第二，第三和第四源极区域具有大致矩形形状并且被布置成与第一漏极区域的侧面相邻。栅极区域布置在第一，第二，第三和第四源极区域与第一漏极区域之间。第一，第二，第三和第四衬底接触区域，其布置成与第一漏极区域的角部相邻。

73. 发明申请

US20090051432A1 High-bandwidth high-gain amplifier 有权
标题翻译：高带宽高增益放大器
公开(公告)号：US20090051432A1
公开(公告)日：2009-02-26
申请号：US12217753
申请日：2008-07-08
申请人： Sehat Sutardja
发明人： Sehat Sutardja
IPC分类号： H03F3/68 , H03F3/45 , H03M1/12
CPC分类号： H03F3/45183 , H03F1/08 , H03F3/26 , H03F2200/36
摘要： A pipelined analog to digital converter includes a first stage that receives an input voltage, that generates a first sampled digital value and a first residue voltage, and that includes a first amplifier that amplifies the first residue voltage and generates a first amplified residue voltage. A second stage receives the first amplified residue voltage, generates a second sampled digital value and a second residue voltage, and includes a second amplifier that amplifies the second residue voltage. At least one of the first amplifier and the second amplifier comprises a first transistor having a control terminal, a first terminal, and a second terminal, a second transistor having a control terminal, a first terminal, and a second terminal that communicates with the second terminal of the first transistor, a differential transimpedance amplifier and a differential output amplifier.
摘要翻译：流水线模数转换器包括接收输入电压的第一级，其产生第一采样数字值和第一残余电压，并且包括放大第一残余电压并产生第一放大残余电压的第一放大器。第二级接收第一放大残余电压，产生第二采样数字值和第二残留电压，并且包括放大第二残余电压的第二放大器。第一放大器和第二放大器中的至少一个包括具有控制端子，第一端子和第二端子的第一晶体管，具有控制端子的第二晶体管，第一端子和与第二端子连通的第二端子第一晶体管的端子，差分跨阻放大器和差分输出放大器。

74. 发明授权

US07459381B2 Integrated circuits and interconnect structure for integrated circuits 有权
标题翻译：用于集成电路的集成电路和互连结构
公开(公告)号：US07459381B2
公开(公告)日：2008-12-02
申请号：US11386276
申请日：2006-03-22
申请人： Sehat Sutardja
发明人： Sehat Sutardja
IPC分类号： H01L21/44
CPC分类号： H01L23/4824 , H01L23/367 , H01L23/5286 , H01L23/5386 , H01L24/02 , H01L24/15 , H01L24/16 , H01L24/40 , H01L27/092 , H01L2224/0401 , H01L2224/16 , H01L2224/16245 , H01L2224/40225 , H01L2224/83801 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2224/37099
摘要： A method for reducing parasitic resistance in an integrated circuit, comprises connecting first and second terminals of a first transistor to second and first plane-like metal layers, respectively; connecting third and fourth terminals of a second transistor to said first and a third plane-like metal layer, respectively; and connecting first, second and third contact portions of a fourth plane-like metal layer to said second plane-like metal layer, said first plane-like metal layer and said third plane-like metal layer, respectively.
摘要翻译：一种用于降低集成电路中的寄生电阻的方法，包括将第一晶体管的第一和第二端子分别连接到第二和第一平面状金属层; 将第二晶体管的第三和第四端子分别连接到所述第一和第三平面状金属层; 并且将第四平面状金属层的第一，第二和第三接触部分分别连接到所述第二平面状金属层，所述第一平面状金属层和所述第三平面状金属层。

75. 发明申请

US20080288748A1 Dynamic core switching 审中-公开
标题翻译：动态核心切换
公开(公告)号：US20080288748A1
公开(公告)日：2008-11-20
申请号：US12215760
申请日：2008-06-30
申请人： Sehat Sutardja , Hong-Yi Chen , Premanand Sakarda , Mark N. Fullerton , Jay Heeb
发明人： Sehat Sutardja , Hong-Yi Chen , Premanand Sakarda , Mark N. Fullerton , Jay Heeb
IPC分类号： G06F15/80 , G06F9/00
CPC分类号： G06F1/3293 , G06F1/3203 , G06F1/3287 , G06F1/329 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/38 , G06F9/3885 , G06F9/461 , G06F9/4856 , G06F9/4893 , Y02D10/122 , Y02D10/171 , Y02D10/24 , Y02D10/32 , Y02D50/20
摘要： A core switching system includes a mode switching module that receives a switch signal to switch operation between a first mode and a second mode. During the first mode, instructions associated with applications are executed by a first asymmetric core, and a second asymmetric core is inactive. During the second mode, the instructions are executed by the second asymmetric core, and the first asymmetric core is inactive. A core activation module stops processing of the applications by the first asymmetric core after interrupts are disabled. A state transfer module transfers a state of the first asymmetric core to the second asymmetric core. The core activation module allows the second asymmetric core to resume execution of the instructions and the interrupts are enabled.
摘要翻译：核心交换系统包括模式切换模块，其接收切换信号以在第一模式和第二模式之间切换操作。在第一模式期间，与应用相关联的指令由第一不对称核执行，而第二非对称核是不活动的。在第二模式期间，指令由第二非对称核执行，第一非对称核是不活动的。核心激活模块在禁止中断之后停止第一个非对称核心处理应用程序。状态转移模块将第一不对称核的状态转移到第二不对称核。核心激活模块允许第二非对称核继续执行指令，中断被使能。

76. 发明申请

US20080263324A1 DYNAMIC CORE SWITCHING 审中-公开
标题翻译：动态芯切换
公开(公告)号：US20080263324A1
公开(公告)日：2008-10-23
申请号：US12145660
申请日：2008-06-25
申请人： Sehat Sutardja , Hong-Yi Chen , Premanand Sakarda , Mark N. Fullerton , Jay Heeb
发明人： Sehat Sutardja , Hong-Yi Chen , Premanand Sakarda , Mark N. Fullerton , Jay Heeb
IPC分类号： G06F9/00
CPC分类号： G06F1/3293 , G06F1/3203 , G06F1/3287 , G06F1/329 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/38 , G06F9/3885 , G06F9/461 , G06F9/4856 , G06F9/4893 , Y02D10/122 , Y02D10/171 , Y02D10/24 , Y02D10/32 , Y02D50/20
摘要： A system includes a first asymmetric core, a second asymmetric core, and a core switching module. The first asymmetric core executes an application when the system operates in a first mode and is inactive when the system operates in a second mode. The second asymmetric core executes the application when the system operates in the second mode. The core switching module switches operation of the system between the first mode and the second mode. The core switching module selectively stops processing of the application by the first asymmetric core after receiving a first control signal. The core switching module transfers a first state of the first asymmetric core to the second asymmetric core. The second asymmetric core resumes executing the application in the second mode.
摘要翻译：系统包括第一不对称核心，第二非对称核心和核心交换模块。当系统以第一模式操作时，第一非对称核执行应用，并且当系统以第二模式操作时，该状态不活动。当系统在第二模式下运行时，第二个非对称核执行应用程序。核心交换模块在第一模式和第二模式之间切换系统的操作。核心交换模块在接收到第一控制信号之后选择性地停止第一非对称核心处理应用程序。核心交换模块将第一不对称核心的第一状态传送到第二不对称核心。第二个非对称核心在第二个模式中恢复执行应用程序。

77. 发明授权

US07417575B2 High-bandwidth high-gain amplifier 有权
标题翻译：高带宽高增益放大器
公开(公告)号：US07417575B2
公开(公告)日：2008-08-26
申请号：US11528034
申请日：2006-09-27
申请人： Sehat Sutardja
发明人： Sehat Sutardja
IPC分类号： H03M1/38
CPC分类号： H03F3/45183 , H03F1/08 , H03F3/26 , H03F2200/36
摘要： A pipelined analog to digital converter comprises a first stage that receives an input voltage, that generates a first sampled digital value and a first residue voltage, and that includes a first amplifier that amplifies the first residue voltage and generates a first amplified residue voltage. A second stage receives the first amplified residue voltage, generates a second sampled digital value and a second residue voltage, and includes a second amplifier that amplifies the second residue voltage. At least one of the first amplifier and the second amplifier comprises a first transistor having a control terminal, a first terminal, and a second terminal, a transimpedance amplifier having an input that communicates with the first terminal of the first transistor, and an output, and an output amplifier having an input that communicates with the output of the transimpedance amplifier, and an output.
摘要翻译：流水线模数转换器包括接收输入电压的第一级，其产生第一采样数字值和第一残余电压，并且包括放大第一残余电压并产生第一放大残余电压的第一放大器。第二级接收第一放大残余电压，产生第二采样数字值和第二残留电压，并且包括放大第二残余电压的第二放大器。第一放大器和第二放大器中的至少一个包括具有控制端子，第一端子和第二端子的第一晶体管，具有与第一晶体管的第一端子连通的输入端的跨阻抗放大器，以及具有与跨阻放大器的输出通信的输入的输出放大器和输出。

78. 发明申请

US20080165794A1 DUAL PORTED NETWORK PHYSICAL LAYER 有权
标题翻译：双重网络物理层
公开(公告)号：US20080165794A1
公开(公告)日：2008-07-10
申请号：US11857238
申请日：2007-09-18
申请人： Sehat Sutardja , Pierte Roo
发明人： Sehat Sutardja , Pierte Roo
IPC分类号： H04L12/56
CPC分类号： H03K17/005 , H03K17/693
摘要： A switching physical layer (PHY) device comprises a first termination network, a switching transmitter, and a switching receiver. The first termination network communicates with a first network connector. The switching transmitter includes first and second outputs, which communicate with the first termination network and a second termination network, respectively. The switching transmitter selectively outputs a transmit signal to a selected one of the first and second termination networks based on a control signal. The switching receiver includes first and second inputs, which communicate with the first and second termination networks, respectively. The switching receiver receives a receive signal from the selected one of the first and second termination networks.
摘要翻译：交换物理层（PHY）设备包括第一终端网络，交换发射机和切换接收机。第一终端网络与第一网络连接器通信。切换发射机包括分别与第一终端网络和第二终端网络通信的第一和第二输出。开关发射器基于控制信号选择性地向第一和第二终端网络中的一个输出发射信号。切换接收机包括分别与第一和第二终端网络通信的第一和第二输入。切换接收器从所选择的第一和第二终端网络接收接收信号。

79. 发明申请

US20080165602A1 Processor Instruction Cache with Dual-Read Modes 有权
标题翻译：具有双读模式的处理器指令缓存
公开(公告)号：US20080165602A1
公开(公告)日：2008-07-10
申请号：US11870833
申请日：2007-10-11
申请人： Sehat Sutardja , Jason T. Su , Hong-Yi Chen , Jason Sheu , Jensen Tjeng
发明人： Sehat Sutardja , Jason T. Su , Hong-Yi Chen , Jason Sheu , Jensen Tjeng
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1045 , G06F12/0877 , G06F12/0882 , G06F12/0893 , G06F2212/1028 , G11C7/1027 , G11C7/12 , G11C11/418 , G11C2207/104 , G11C2207/2245 , Y02D10/13
摘要： A processor includes a cache memory. The cache memory includes an array of cells, word lines and bit lines. A control module enables a word line of the word lines to access a first cell in the enabled word line. The control module disables the word line and maintains the word line in a disabled state to access a second cell in the word line.
摘要翻译：处理器包括高速缓冲存储器。高速缓冲存储器包括单元阵列，字线和位线。控制模块使得字线的字线能够访问所启用的字线中的第一单元。控制模块禁用字线并将字线保持在禁用状态，以访问字线中的第二个单元格。

80. 发明授权

US07397310B2 High-bandwidth high-gain amplifier 有权
标题翻译：高带宽高增益放大器
公开(公告)号：US07397310B2
公开(公告)日：2008-07-08
申请号：US11528033
申请日：2006-09-27
申请人： Sehat Sutardja
发明人： Sehat Sutardja
IPC分类号： H03F3/68 , H03M1/12
CPC分类号： H03F3/45183 , H03F1/08 , H03F3/26 , H03F2200/36
摘要： A pipelined analog to digital converter includes a first stage that receives an input voltage, that generates a first sampled digital value and a first residue voltage, and that includes a first amplifier that amplifies the first residue voltage and generates a first amplified residue voltage. A second stage receives the first amplified residue voltage, generates a second sampled digital value and a second residue voltage, and includes a second amplifier that amplifies the second residue voltage. At least one of the first amplifier and the second amplifier comprises a first transistor having a control terminal, a first terminal, and a second terminal, a second transistor having a control terminal, a first terminal, and a second terminal that communicates with the second terminal of the first transistor, a differential transimpedance amplifier and a differential output amplifier.
摘要翻译：流水线模数转换器包括接收输入电压的第一级，其产生第一采样数字值和第一残余电压，并且包括放大第一残余电压并产生第一放大残余电压的第一放大器。第二级接收第一放大残余电压，产生第二采样数字值和第二残留电压，并且包括放大第二残余电压的第二放大器。第一放大器和第二放大器中的至少一个包括具有控制端子，第一端子和第二端子的第一晶体管，具有控制端子的第二晶体管，第一端子和与第二端子连通的第二端子第一晶体管的端子，差分跨阻放大器和差分输出放大器。

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