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71. 发明授权

US07535066B2 Gate structure and method 有权
标题翻译：门结构和方法
公开(公告)号：US07535066B2
公开(公告)日：2009-05-19
申请号：US10349686
申请日：2003-01-23
申请人： Antonio L. P. Rotondaro , Luigi Colombo , Mark R. Visokay , Rajesh Khamankar , Douglas E. Mercer
发明人： Antonio L. P. Rotondaro , Luigi Colombo , Mark R. Visokay , Rajesh Khamankar , Douglas E. Mercer
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/823857 , H01L21/823871 , H01L27/092 , H01L29/517 , H01L29/518
摘要： A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.
摘要翻译：一种MOSFET结构，包括在栅极材料沉积之前具有栅极电介质的氮化处理的硅酸盐栅极电介质。

72. 发明授权

US07528024B2 Dual work function metal gate integration in semiconductor devices 有权
标题翻译：双功能金属门集成在半导体器件中
公开(公告)号：US07528024B2
公开(公告)日：2009-05-05
申请号：US10890365
申请日：2004-07-13
申请人： Luigi Colombo , James J. Chambers , Mark R. Visokay
发明人： Luigi Colombo , James J. Chambers , Mark R. Visokay
IPC分类号： H01L21/28 , H01L21/338 , H01L21/44
CPC分类号： H01L21/823842 , H01L29/4958
摘要： The present invention provides, in one embodiment, a process for forming a dual work function metal gate semiconductor device (100). The process includes providing a semiconductor substrate (105) having a gate dielectric layer (110) thereon and a metal layer (205) on the gate dielectric layer. A work function of the metal layer is matched to a conduction band or a valence band of the semiconductor substrate. The process also includes forming a conductive barrier layer (210) on a portion (215) of the metal layer and a material layer (305) on the metal layer. The metal layer and the material layer are annealed to form a metal alloy layer (405) to thereby match a work function of the metal alloy layer to another of the conduction band or the valence band of the substrate. Other embodiments of the invention include a dual work function metal gate semiconductor device (900) and an integrated circuit (1000).
摘要翻译：本发明在一个实施例中提供了一种用于形成双功函数金属栅极半导体器件（100）的工艺。该方法包括提供其上具有栅极电介质层（110）的半导体衬底（105）和栅极电介质层上的金属层（205）。金属层的功函数与半导体衬底的导带或价带相匹配。该方法还包括在金属层的一部分（215）和金属层上的材料层（305）上形成导电阻挡层（210）。对金属层和材料层进行退火以形成金属合金层（405），从而将金属合金层的功函数与衬底的导带或价带中的另一个相匹配。本发明的其它实施例包括双功函数金属栅极半导体器件（900）和集成电路（1000）。

73. 发明授权

US07387956B2 Refractory metal-based electrodes for work function setting in semiconductor devices 有权
$Refractory metal-based electrodes for work function setting in semiconductor devices$
标题翻译：用于半导体器件功能设置的耐火金属基电极
公开(公告)号：US07387956B2
公开(公告)日：2008-06-17
申请号：US11462573
申请日：2006-08-04
申请人： Luigi Colombo , James J Chambers , Mark R Visokay
发明人： Luigi Colombo , James J Chambers , Mark R Visokay
IPC分类号： H01L21/3205
CPC分类号： H01L21/823842 , H01L29/4958
摘要： The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).
摘要翻译：本发明在一个实施例中提供一种栅极结构（100）。栅极结构包括栅极电介质（105）和栅极（110）。栅极电介质包括难熔金属并且位于半导体衬底（115）之上。半导体衬底具有导带和价带。栅极位于栅极电介质上方并且包括难熔金属。栅极具有与导带或价带对准的功函数。其他实施例包括替代栅极结构（200），形成用于半导体器件（301）的栅极结构（300）和双栅极集成电路（400）的方法。

74. 发明授权

US07338865B2 Method for manufacturing dual work function gate electrodes through local thickness-limited silicidation 有权
标题翻译：通过局部厚度限制硅化物制造双功能功能栅电极的方法
公开(公告)号：US07338865B2
公开(公告)日：2008-03-04
申请号：US10897846
申请日：2004-07-23
申请人： Robert W. Murto , Luigi Colombo , Mark R. Visokay
发明人： Robert W. Murto , Luigi Colombo , Mark R. Visokay
IPC分类号： H01L21/8234
CPC分类号： H01L21/823835 , H01L21/823842
摘要： The present invention provides a method of manufacturing a semiconductor device. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a gate electrode (135) that includes a metal silicide layer 135a over which is located a silicon gate layer (135b) together which have a work function associated therewith, and a second transistor (125) located over the semiconductor substrate (110) and proximate the first transistor (120), wherein the second transistor (125) also includes a gate electrode (160) that includes a metal silicide layer (160a) over which is located a silicon gate layer (160b) together which have a different work function from that of the first gate electrode (135) associated therewith.
摘要翻译：本发明提供一种制造半导体器件的方法。除了其它可能的元件之外，半导体器件（100）包括位于半导体衬底（110）上方的第一晶体管（120），其中第一晶体管（120）具有包括金属硅化物层135a的栅电极（135）位于硅栅极层（135b）上，其具有与其相关联的功函数;以及第二晶体管（125），位于半导体衬底（110）之上并且靠近第一晶体管（120），其中第二晶体管 125）还包括栅电极（160），其包括金属硅化物层（160a），栅极电极（160a）位于硅栅极层（160b）上，其具有与第一栅电极（135）的功函数不同的功函随之而来。

75. 发明授权

US07233035B2 Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound 有权
标题翻译：使用掺杂多晶硅和金属硅锗化合物的双功函数栅电极
公开(公告)号：US07233035B2
公开(公告)日：2007-06-19
申请号：US11463128
申请日：2006-08-08
申请人： Antonio L. P. Rotondaro , Mark R. Visokay , Luigi Colombo
发明人： Antonio L. P. Rotondaro , Mark R. Visokay , Luigi Colombo
IPC分类号： H01L29/80 , H01L21/336
CPC分类号： H01L21/28097 , H01L21/823842 , H01L29/4975
摘要： A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the dielectric layer (50) and over the first region (20) and the second region (30). The polysilicon layer can comprise 0 to 50 atomic percent of germanium. A metal layer is formed over the polysilicon layer and one of the regions and reacted with the underlying polysilicon layer to form a metal silicide or a metal germano silicide. The polysilicon and metal silicide or germano silicide regions are etched to form transistor gate regions (60) and (90) respectively. If desired a cladding layer (100) can be formed above the metal gate structures.
摘要翻译：在包含第一区域（20）和第二区域（30）的半导体（10）上形成介电层（50）。在电介质层（50）上并在第一区域（20）和第二区域（30）之上形成多晶硅层。多晶硅层可以包含0至50原子％的锗。在多晶硅层和其中一个区域上形成金属层，并与下面的多晶硅层反应形成金属硅化物或金属锗化硅。蚀刻多晶硅和金属硅化物或锗硅化物区域以分别形成晶体管栅极区域（60）和（90）。如果需要，可以在金属栅极结构上方形成包覆层（100）。

76. 发明授权

US07045456B2 MOS transistor gates with thin lower metal silicide and methods for making the same 有权
标题翻译：具有薄的下金属硅化物的MOS晶体管栅极及其制造方法
公开(公告)号：US07045456B2
公开(公告)日：2006-05-16
申请号：US10745454
申请日：2003-12-22
申请人： Robert William Murto , Luigi Colombo , Mark Robert Visokay
发明人： Robert William Murto , Luigi Colombo , Mark Robert Visokay
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L29/4975 , H01L21/28097 , H01L21/823835 , H01L29/665 , H01L29/6659
摘要： Methods are presented for fabricating transistor gate structures, wherein upper and lower metal suicides are formed above a gate dielectric. In one example, the lower silicide is formed by depositing a thin first silicon-containing material over the gate dielectric, which is implanted and then reacted with a first metal by annealing to form the lower silicide. A capping layer can be formed over the first metal prior to annealing, to prevent oxidation of the metal prior to silicidation, and a barrier layer can be formed over the lower silicide to prevent reaction with subsequently formed silicon material. In another example, the lower silicide is a multilayer silicide structure including a plurality of metal silicide sublayers.
摘要翻译：呈现用于制造晶体管栅极结构的方法，其中上和下金属硅化物形成在栅极电介质上方。在一个示例中，下硅化物通过在栅极电介质上沉积薄的第一含硅材料而形成，其被注入，然后通过退火与第一金属反应以形成下硅化物。在退火之前可以在第一金属上形成覆盖层，以防止在硅化物之前金属的氧化，并且可以在下硅化物上形成阻挡层以防止随后形成的硅材料的反应。在另一个实例中，下硅化物是包括多个金属硅化物层的多层硅化物结构。

77. 发明申请

US20060074014A1 Dalbavancin compositions for treatment of bacterial infections 审中-公开
标题翻译：达巴万星组合物治疗细菌感染
公开(公告)号：US20060074014A1
公开(公告)日：2006-04-06
申请号：US11116064
申请日：2005-04-26
申请人： Martin Stogniew , Luigi Colombo , Romeo Ciabatti
发明人： Martin Stogniew , Luigi Colombo , Romeo Ciabatti
IPC分类号： A61K38/16
CPC分类号： C07H7/033 , A61K31/704 , A61K38/00 , C07H13/06 , C07H15/203 , C07K9/008 , Y02A50/475 , Y02A50/478 , Y02A50/479 , Y02A50/481 , A61K2300/00
摘要： The invention provides methods and compositions for treatment of bacterial infections. The composition may be a combination of factors, which include A0, A1, B1, B2, C0, C1, isoB0, and MAG, in the presence of low level solvent. Methods of the invention include administration of dalbavancin formulations for treatment of a bacterial infection, in particular a Gram-positive bacterial infection of skin and soft tissue. Dosing regimens include multiple dose administration of dalbavancin, which often remains at therapeutic levels in the bloodstream for at least one week, providing prolonged therapeutic action against a bacterial infection. Dosing regimens for renal patients are also included.
摘要翻译：本发明提供了用于治疗细菌感染的方法和组合物。组合物可以是因素的组合，其包括A 1，A 1，B 1，B 2，在低级溶剂存在下，将C 1 O 3，C 1 H 2，异丁基低级烷基和杂芳基。本发明的方法包括施用达巴万星制剂用于治疗细菌感染，特别是皮肤和软组织的革兰氏阳性细菌感染。给药方案包括达巴万星的多剂量给药，其通常在血流中保持治疗水平至少一周，为细菌感染提供长时间的治疗作用。还包括肾脏患者的给药方案。

78. 发明授权

US07018902B2 Gate dielectric and method 有权
公开(公告)号：US07018902B2
公开(公告)日：2006-03-28
申请号：US10165888
申请日：2002-06-10
申请人： Mark R. Visokay , Antonio L. P. Rotondaro , Luigi Colombo
发明人： Mark R. Visokay , Antonio L. P. Rotondaro , Luigi Colombo
IPC分类号： H01L21/00
CPC分类号： H01L21/823857 , H01L21/823842
摘要： A MOSFET structure with high-k gate dielectric layer and silicon or metal gates, amorphizing treatment of the high-k gate dielectric layer as with a plasma or ion implantation.

79. 发明申请

US20050205948A1 Gate dielectric and method 有权
公开(公告)号：US20050205948A1
公开(公告)日：2005-09-22
申请号：US11118647
申请日：2005-04-28
申请人： Antonio Rotondaro , Luigi Colombo , Malcolm Bevan
发明人： Antonio Rotondaro , Luigi Colombo , Malcolm Bevan
IPC分类号： H01L27/092 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/78 , H01L29/76 , H01L31/062
CPC分类号： H01L21/823842 , H01L21/823857
摘要： CMOS gate dielectric made of high-k metal silicates by passivating a silicon surface with nitrogen compounds prior to high-k dielectric deposition. Optionally, a silicon dioxide monolayer may be preserved at the interface.

80. 发明申请

US20050130438A1 Method of fabricating a dielectric layer for a semiconductor structure 审中-公开
标题翻译：制造半导体结构的电介质层的方法
公开(公告)号：US20050130438A1
公开(公告)日：2005-06-16
申请号：US10736444
申请日：2003-12-15
申请人： Antonio Rotondaro , Luigi Colombo
发明人： Antonio Rotondaro , Luigi Colombo
IPC分类号： H01L21/3115 , H01L21/314 , H01L21/318 , H01L21/31 , H01L21/469
CPC分类号： H01L21/823864 , H01L21/3115 , H01L21/3141 , H01L21/3143 , H01L21/3185
摘要： Fabricating a semiconductor structure includes establishing a non-stoichiometry associated with a dielectric layer, where the degree of non-stoichiometry corresponds to a nitrogen profile of the dielectric layer. Deposition of the dielectric layer outwardly from a substrate is controlled to substantially yield the established non-stoichiometry of the dielectric layer. Nitrogen is incorporated into the dielectric layer to substantially yield the nitrogen profile without nitridation of the interface.
摘要翻译：制造半导体结构包括建立与电介质层相关的非化学计量，其中非化学计量的程度对应于电介质层的氮分布。电介质层从衬底向外沉积被控制以基本上产生介电层的已建立的非化学计量。将氮气结合到电介质层中以基本上产生氮分布，而不会使界面氮化。

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