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71. 发明申请

US20090089719A1 Structure for a Stacked Power Clamp Having a BigFET Gate Pull-Up Circuit 有权
标题翻译：具有BigFET栅极上拉电路的堆叠电源钳位的结构
公开(公告)号：US20090089719A1
公开(公告)日：2009-04-02
申请号：US12127245
申请日：2008-05-27
申请人： Robert J. Gauthier, JR. , Junjun Li
发明人： Robert J. Gauthier, JR. , Junjun Li
IPC分类号： H02H9/00 , G06F17/50
CPC分类号： G06F17/5045 , H01L27/0285 , H01L2924/0002 , H01L2924/00
摘要： Design structure for an electrostatic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event. The design structure for the ESD protection circuit includes a stack of BigFETs, a BigFET gate driver for driving the gates of the BigFETs, and a trigger for triggering the BigFET gate driver to drive the gates of the BigFETs in response to an ESD event. The BigFET gate driver includes gate pull-up circuitry for pulling up the gate of a lower one of the BigFETs. The gate pull-up circuitry is configured so as to obviate the need for a diffusion contact between the stacked BigFETs, resulting in a significant savings in terms of the chip area needed to implement the ESD protection circuit.
摘要翻译：用于保护集成电路芯片免受ESD事件的静电放电（ESD）保护电路的设计结构。 ESD保护电路的设计结构包括一堆BigFET，用于驱动BigFET栅极的BigFET栅极驱动器，以及用于触发BigFET栅极驱动器以响应于ESD事件来驱动BigFET栅极的触发器。 BigFET栅极驱动器包括用于拉低下一个BigFET的栅极的栅极上拉电路。栅极上拉电路被配置为消除对堆叠的BigFET之间的扩散接触的需要，导致实现ESD保护电路所需的芯片面积的显着节省。

72. 发明授权

US08692291B2 Passive devices for FinFET integrated circuit technologies 有权
标题翻译： FinFET集成电路技术的无源器件
公开(公告)号：US08692291B2
公开(公告)日：2014-04-08
申请号：US13431456
申请日：2012-03-27
申请人： William F. Clark, Jr. , Robert J. Gauthier, Jr. , Junjun Li
发明人： William F. Clark, Jr. , Robert J. Gauthier, Jr. , Junjun Li
IPC分类号： H01L29/66
CPC分类号： H01L21/845 , H01L27/0262 , H01L27/1211
摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device structure is formed that includes a well of a first conductivity type in a device region and a doped region of a second conductivity in the well. The device region is comprised of a portion of a device layer of a semiconductor-on-insulator substrate. The doped region and a first portion of the well define a junction. A second portion of the well is positioned between the doped region and an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.
摘要翻译：无源器件的器件结构，设计结构和制造方法可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。形成器件结构，其包括器件区域中的第一导电类型的阱和阱中的第二导电性的掺杂区域。器件区域由绝缘体上半导体衬底的器件层的一部分组成。掺杂区域和阱的第一部分限定了结。阱的第二部分位于器件区域的掺杂区域和外部侧壁之间。可以对器件层的另一部分进行构图以形成翅片型场效应晶体管的鳍片。

73. 发明申请

US20130285211A1 DEVICE STRUCTURES COMPATIBLE WITH FIN-TYPE FIELD-EFFECT TRANSISTOR TECHNOLOGIES 有权
标题翻译：与FIN型场效应晶体管技术兼容的器件结构
公开(公告)号：US20130285211A1
公开(公告)日：2013-10-31
申请号：US13455732
申请日：2012-04-25
申请人： Robert J. Gauthier, JR. , Jeffrey B. Johnson , Junjun Li
发明人： Robert J. Gauthier, JR. , Jeffrey B. Johnson , Junjun Li
IPC分类号： H01L29/00 , G06F17/50 , H01L21/20
CPC分类号： H01L27/1211 , G06F17/5068 , H01L21/3086 , H01L21/845
摘要： Device structures, design structures, and fabrication methods for fin-type field-effect transistor integrated circuit technologies. First and second fins, which constitute electrodes of the device structure, are each comprised of a first semiconductor material. The second fin is formed adjacent to the first fin to define a gap separating the first and second fins. Positioned in the gap is a layer comprised of a second semiconductor material.
摘要翻译：鳍式场效应晶体管集成电路技术的器件结构，设计结构和制造方法。构成器件结构的电极的第一和第二鳍片均由第一半导体材料构成。第二翅片邻近第一翅片形成以限定分隔第一和第二翅片的间隙。位于间隙中的是由第二半导体材料构成的层。

74. 发明申请

US20130020645A1 ESD FIELD-EFFECT TRANSISTOR AND INTEGRATED DIFFUSION RESISTOR 有权
标题翻译： ESD场效应晶体管和集成扩散电阻
公开(公告)号：US20130020645A1
公开(公告)日：2013-01-24
申请号：US13188094
申请日：2011-07-21
申请人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Rahul Mishra , Junjun Li , Mujahid Muhammad
发明人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Rahul Mishra , Junjun Li , Mujahid Muhammad
IPC分类号： H01L29/772 , G06F9/45 , H01L21/336
CPC分类号： H01L29/41775 , H01L27/0266 , H01L29/1087 , H01L29/66659 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection device, methods of fabricating an electrostatic discharge protection device, and design structures for an electrostatic discharge protection device. A drain of a first field-effect transistor and a diffusion resistor of higher electrical resistance may be formed as different portions of a doped region. The diffusion resistor, which is directly coupled with the drain of the first field-effect transistor, may be defined using an isolation region of dielectric material disposed in the doped region and selective silicide formation. The electrostatic discharge protection device may also include a second field-effect transistor having a drain as a portion the doped region that is directly coupled with the diffusion resistor and indirectly coupled by the diffusion resistor with the drain of the first field-effect transistor.
摘要翻译：静电放电保护装置，静电放电保护装置的制造方法以及静电放电保护装置的设计结构。第一场效应晶体管的漏极和较高电阻的扩散电阻可以形成为掺杂区域的不同部分。可以使用布置在掺杂区域中的介电材料的隔离区域和选择性硅化物形成来限定与第一场效应晶体管的漏极直接耦合的扩散电阻器。静电放电保护器件还可以包括第二场效应晶体管，其具有作为与扩散电阻器直接耦合并且由扩散电阻器与第一场效应晶体管的漏极间接耦合的掺杂区域的一部分的漏极。

75. 发明授权

US08354722B2 SCR/MOS clamp for ESD protection of integrated circuits 失效
标题翻译：用于集成电路ESD保护的SCR / MOS钳位
公开(公告)号：US08354722B2
公开(公告)日：2013-01-15
申请号：US13149174
申请日：2011-05-31
申请人： John B. Campi, Jr. , Shunhua Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： John B. Campi, Jr. , Shunhua Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H01L29/78 , H01L29/788 , H02H9/00
CPC分类号： H01L29/742 , H01L27/0262
摘要： An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad.
摘要翻译：静电放电（ESD）保护电路，制造ESD保护电路的方法，提供ESD保护的方法以及ESD保护电路的设计结构。可以在p阱中形成NFET，并且可以在n阱中形成PFET。在p阱和n阱之间形成的对接p-n结导致形成与NFET和PFET集成的SCR的NPNP结构。 NFET，PFET和SCR被配置为共同保护诸如电源板的焊盘免受ESD事件的影响。在正常工作期间，NFET，PFET和SCR被RC触发电路偏置，使得ESD保护电路处于高阻抗状态。在芯片无电源时的ESD事件期间，RC触发电路输出触发信号，使SCR，NFET和PFET进入导通状态，并协同地将ESD电流从受保护的焊盘分流。

76. 发明申请

US20120305984A1 SCR/MOS CLAMP FOR ESD PROTECTION OF INTEGRATED CIRCUITS 失效
标题翻译：用于ESD保护集成电路的SCR / MOS钳位
公开(公告)号：US20120305984A1
公开(公告)日：2012-12-06
申请号：US13149174
申请日：2011-05-31
申请人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
发明人： John B. Campi, JR. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, JR. , Junjun Li , Rahul Mishra , Mujahid Muhammad
IPC分类号： H01L29/747 , G06F17/50 , H01L21/332
CPC分类号： H01L29/742 , H01L27/0262
摘要： An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad.
摘要翻译：静电放电（ESD）保护电路，制造ESD保护电路的方法，提供ESD保护的方法以及ESD保护电路的设计结构。可以在p阱中形成NFET，并且可以在n阱中形成PFET。在p阱和n阱之间形成的对接p-n结导致形成与NFET和PFET集成的SCR的NPNP结构。 NFET，PFET和SCR被配置为共同保护诸如电源板的焊盘免受ESD事件的影响。在正常工作期间，NFET，PFET和SCR被RC触发电路偏置，使得ESD保护电路处于高阻抗状态。在芯片无电源时的ESD事件期间，RC触发电路输出触发信号，使SCR，NFET和PFET进入导通状态，并协同地将ESD电流从受保护的焊盘分流。

77. 发明授权

US08230382B2 Model based simulation of electronic discharge and optimization methodology for design checking 有权
标题翻译：基于模型的电子放电仿真和设计检查优化方法
公开(公告)号：US08230382B2
公开(公告)日：2012-07-24
申请号：US12695494
申请日：2010-01-28
申请人： Robert J. Gauthier, Jr. , Bradford L. Hunter , Amol A. Joshi , Junjun Li , Gregory Joseph Schroer
发明人： Robert J. Gauthier, Jr. , Bradford L. Hunter , Amol A. Joshi , Junjun Li , Gregory Joseph Schroer
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method, apparatus and program product are provided for simulating a circuit. A plurality of elements of the circuit is represented by device models including pass/fail criteria. A circuit simulation program is executed on a hardware implemented processor where the circuit simulation program is configured to obtain simulation results from the device models in response to applied parameters. The circuit simulation program identifies a failure of one or more of the plurality of elements of the circuit based on the pass/fail criteria of the device models. The circuit simulation program is further configured to output the failures during simulation of the one or more of the plurality of elements that are identified in response to the applied parameters.
摘要翻译：提供了一种用于模拟电路的方法，装置和程序产品。电路的多个元件由包括通过/不合格标准的器件模型表示。在硬件实现的处理器上执行电路仿真程序，其中电路仿真程序被配置为响应于所应用的参数从设备模型获得仿真结果。电路仿真程序基于设备模型的通过/不合格标准来识别电路的多个元件中的一个或多个元件的故障。电路仿真程序还被配置为在模拟响应于所应用的参数识别的多个元件中的一个或多个元件期间输出故障。

78. 发明授权

US07397641B2 Apparatus and method for improved triggering and oscillation suppression of ESD clamping devices 失效
标题翻译：用于改善ESD钳位装置的触发和振荡抑制的装置和方法
公开(公告)号：US07397641B2
公开(公告)日：2008-07-08
申请号：US11276411
申请日：2006-02-28
申请人： Albert M. Chu , Robert J. Gauthier, Jr. , Junjun Li , Thomas W. Wyckoff
发明人： Albert M. Chu , Robert J. Gauthier, Jr. , Junjun Li , Thomas W. Wyckoff
IPC分类号： H02H9/00 , H02H1/00
CPC分类号： H01L27/0266
摘要： An apparatus for protecting an integrated circuit from electrostatic discharge (ESD) includes an RC trigger device configured between a pair of power rails, a first control path coupled to the RC trigger device, and a second control path coupled to the RC trigger device. A power clamp is configured between the power rails for discharging current from an ESD event, the power clamp having an input coupled to outputs of the first and second control paths, the power clamp independently controllable by the first and second control paths. The first and second control paths are further configured to prevent the power clamp from reactivating following an initial deactivation of the power clamp.
摘要翻译：用于保护集成电路免受静电放电（ESD）的装置包括RC触发装置，其配置在耦合到RC触发装置的一对电源轨，第一控制路径和耦合到RC触发装置的第二控制路径之间。功率钳被配置在用于从ESD事件放电的电源轨之间，功率钳具有耦合到第一和第二控制路径的输出的输入，功率钳由第一和第二控制路径独立地控制。第一和第二控制路径还被配置为防止在电源钳的初始去激活之后电源钳位被重新激活。

79. 发明授权

US07085113B2 ESD protection power clamp for suppressing ESD events occurring on power supply terminals 失效
标题翻译： ESD保护电源钳位，用于抑制电源端子发生的ESD事件
公开(公告)号：US07085113B2
公开(公告)日：2006-08-01
申请号：US10711085
申请日：2004-08-20
申请人： Robert J. Gauthier, Jr. , Junjun Li
发明人： Robert J. Gauthier, Jr. , Junjun Li
IPC分类号： H02H9/00 , H02H3/22
CPC分类号： H01L27/0266
摘要： An ESD protection power clamp for suppressing ESD events. A clamping transistor having power source connections connected across the power supply terminals of an integrated circuit is connected to clamp the voltage during an ESD event. An RC timing circuit defines a time interval where ESD voltage for triggering the FET out of conduction. An inverter circuit connects the RC and timing circuit to the clamping FET. A dynamic feedback transistor is connected in series with one stage of the inverter and the power supply. During an ESD event, the feedback transistor delays the time for disabling the FET transistor, providing increased immunity against mistriggering of the clamping transistor, and forces the circuit to reset following the mistrigger event.
摘要翻译：用于抑制ESD事件的ESD保护电源钳。具有连接在集成电路的电源端子上的电源连接的钳位晶体管被连接以在ESD事件期间钳位电压。 RC定时电路定义用于触发FET导通的ESD电压的时间间隔。逆变器电路将RC和定时电路连接到钳位FET。动态反馈晶体管与逆变器和电源的一级串联连接。在ESD事件期间，反馈晶体管延迟了禁止FET晶体管的时间，提供了抵抗钳位晶体管失谐的增强的抗扰性，并迫使电路在雾触发器事件之后复位。

80. 发明授权

US08906751B2 Silicon controlled rectifiers (SCR), methods of manufacture and design structures 有权
标题翻译：硅控整流器（SCR），制造方法和设计结构
公开(公告)号：US08906751B2
公开(公告)日：2014-12-09
申请号：US12985840
申请日：2011-01-06
申请人： Michel J. Abou-Khalil , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li
发明人： Michel J. Abou-Khalil , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li
IPC分类号： H01L21/332 , H01L29/66 , H01L27/02 , H01L29/08 , H01L29/74
CPC分类号： H01L27/0262 , G06F17/5045 , H01L29/0649 , H01L29/0839 , H01L29/66393 , H01L29/7436
摘要： Silicon controlled rectifiers (SCR), methods of manufacture and design structures are disclosed herein. The method includes forming a common P-well on a buried insulator layer of a silicon on insulator (SOI) wafer. The method further includes forming a plurality of silicon controlled rectifiers (SCR) in the P-well such that N+ diffusion cathodes of each of the plurality of SCRs are coupled together by the common P-well.
摘要翻译：本文公开了可控硅整流器（SCR），制造方法和设计结构。该方法包括在绝缘体上硅（SOI）晶片的掩埋绝缘体层上形成公共P阱。该方法还包括在P阱中形成多个可控硅整流器（SCR），使得多个SCR中的每一个的N +扩散阴极通过公共P阱耦合在一起。

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