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71. 发明授权

US06320815B1 Memory system having flexible bus structure and method 有权
标题翻译：具有灵活总线结构和方法的存储系统
公开(公告)号：US06320815B1
公开(公告)日：2001-11-20
申请号：US09711623
申请日：2000-11-13
申请人： Robert D. Norman , Vinod C. Lakhani , Christophe J. Chevallier
发明人： Robert D. Norman , Vinod C. Lakhani , Christophe J. Chevallier
IPC分类号： G11C800
CPC分类号： G06F12/0661
摘要： A memory system having a memory controller connected to multiple memory devices by way of a system bus. The memory controller issues device select, memory program and memory read instructions for the memory devices over the system bus, with the device select instructions including a device select address and a device select command. The memory devices each include an array of memory cells and a memory operation manager which functions to carry out memory read and program operations on the array. The memory operation manager includes an address comparator which compares the device select address received on the system bus with a local address stored in the memory device and a command decoder which detects commands on the system bus, with the memory operation manager operating to switch the memory device from a device-disabled state to a device-enabled state when the memory device receive a select address which matches the local address together with one of the device select commands.
摘要翻译：一种具有通过系统总线连接到多个存储器件的存储器控制器的存储器系统。存储器控制器通过系统总线向存储器件发出器件选择，存储器程序和存储器读取指令，器件选择指令包括器件选择地址和器件选择命令。存储器件各自包括存储器单元阵列和用于对阵列执行存储器读取和编程操作的存储器操作管理器。存储器操作管理器包括地址比较器，其将系统总线上接收的设备选择地址与存储在存储设备中的本地地址进行比较，以及命令解码器，其用于检测系统总线上的命令，存储器操作管理器操作以切换存储器设备从设备禁用状态到启用设备的状态，当存储设备接收与本地地址匹配的选择地址以及设备选择命令之一时。

72. 发明授权

US06317812B1 Device and method for controlling solid-state memory system 失效
标题翻译：用于控制固态存储器系统的装置和方法
公开(公告)号：US06317812B1
公开(公告)日：2001-11-13
申请号：US09657369
申请日：2000-09-08
申请人： Karl M. J. Lofgren , Jeffrey Donald Stai , Anil Gupta , Robert D. Norman , Sanjay Mehrotra
发明人： Karl M. J. Lofgren , Jeffrey Donald Stai , Anil Gupta , Robert D. Norman , Sanjay Mehrotra
IPC分类号： G06F1200
CPC分类号： G11C5/04 , G06F3/0613 , G06F3/0659 , G06F3/0679 , G06F12/0676 , G06F13/1668 , G06F13/4243 , G11C5/00 , G11C5/066 , G11C8/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A memory system includes an array of solid-state memory devices are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is assigned an array address by an array mount. An memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array mount configuration is used to unconditionally select the device mounted. A reserved address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory subsystem to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.
摘要翻译：存储器系统包括固态存储器件阵列，其经由具有极少线路的器件总线与控制器模块通信并处于控制器模块的控制之下。这形成了集成电路大容量存储系统，其被设想来替代大容量存储系统，例如计算机系统中的磁盘驱动器存储器。命令，地址和数据信息被串行化为组件字符串，并在控制器模块和存储器件阵列之间传输之前被多路复用。序列化信息伴随着一个控制信号，以帮助整理复用的组件。阵列中的每个内存设备都由阵列装载分配一个阵列地址。通过在设备总线上广播的适当地址来选择存储设备，而不需要通常的专用选择信号。保留阵列安装配置用于无条件地选择安装的设备。通过设备总线广播的保留地址将取消所有先前选择的存储设备。通过读取流技术增强读取性能，其中当当前大量数据被序列化并从存储器子系统移出到控制器模块时，控制器模块还设置下一个数据块的地址以开始寻址内存系统。

73. 发明授权

US06148363A Device and method for controlling solid-state memory system 失效
公开(公告)号：US06148363A
公开(公告)日：2000-11-14
申请号：US64528
申请日：1998-04-21
申请人： Karl M. J. Lofgren , Jeffrey Donald Stai , Anil Gupta , Robert D. Norman , Sanjay Mehrotra
发明人： Karl M. J. Lofgren , Jeffrey Donald Stai , Anil Gupta , Robert D. Norman , Sanjay Mehrotra
IPC分类号： G06F3/06 , G06F12/06 , G06F13/16 , G06F13/42 , G11C5/00 , G11C5/06 , G11C8/12 , G06F12/00
CPC分类号： G11C5/04 , G06F12/0676 , G06F13/1668 , G06F13/4243 , G06F3/0613 , G06F3/0659 , G06F3/0679 , G11C5/00 , G11C5/066 , G11C8/12 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A memory system includes an array of solid-state memory devices are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is assigned an array address by an array mount. An memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array mount configuration is used to unconditionally select the device mounted. A reserved address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory subsystem to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.

74. 发明授权

US6107630A Array combining many photoconductive detectors in a compact package 失效
标题翻译：阵列将许多光电导检测器结合在一个紧凑的封装中
公开(公告)号：US6107630A
公开(公告)日：2000-08-22
申请号：US77781
申请日：1998-06-05
申请人： John S. Mazurowski , John S. Griffith , Robert D. Norman
发明人： John S. Mazurowski , John S. Griffith , Robert D. Norman
IPC分类号： G01J5/06 , G01J5/28 , H01L31/0203 , H01L31/024 , H04N5/225 , H04N5/33 , G01J5/14
CPC分类号： H04N5/2253 , G01J5/061 , G01J5/28 , H01L31/0203 , H01L31/024 , H01L2224/48091 , H04N5/33
摘要： A radiation detector includes a plurality of detector elements arranged on a detector substrate in an interdigitated linear array. A thermoelectric or other cooler is attached to the lower surface of the detector substrate. A pair of interconnect boards is positioned on opposite sides of the detector substrate. The detector elements, substrate, cooler and pair of boards are received in a sealed housing and a radiation transmitting window in the housing permits radiation to pass into the housing and strike the detector elements. A plurality of conductive pins extends through the housing and terminates at electrical traces on the interconnect boards. A thermistor or other temperature sensor is attached to the detector substrate and, through control of the thermoelectric cooler, maintains the detector substrate at a desired operating temperature.
摘要翻译： PCT No.PCT / US96 / 19799 Sec。 371日期：1998年1月27日 102（e）1998年1月27日PCT PCT 1996年12月6日PCT公布。出版物WO97 / 21080 日期：1997年6月12日辐射检测器包括以叉指线性阵列布置在检测器基底上的多个检测器元件。热电或其他冷却器连接到检测器基板的下表面。一对互连板位于检测器基板的相对侧上。检测器元件，基板，冷却器和一对板被容纳在密封的壳体中，壳体中的辐射透射窗口允许辐射进入壳体并撞击检测器元件。多个导电针延伸穿过壳体并终止在互连板上的电迹线上。热敏电阻或其他温度传感器连接到检测器基板，并且通过热电冷却器的控制将检测器基板保持在期望的工作温度。

75. 发明授权

US6073208A Apparatus and method for reducing programming cycles for multistate memory system 有权
标题翻译：用于减少多状态存储器系统的编程周期的装置和方法
公开(公告)号：US6073208A
公开(公告)日：2000-06-06
申请号：US190975
申请日：1998-11-12
申请人： Robert D. Norman
发明人： Robert D. Norman
IPC分类号： G11C11/56 , G06F12/00 , G06F13/00
CPC分类号： G11C11/5628 , G11C11/56 , G11C11/5621 , G11C2211/5647
摘要： An apparatus and method for reducing the number of programming states (threshold voltage levels) required to be traversed when programming a multistate memory cell with a given set of data. The invention first determines the average programming state (corresponding to an average threshold voltage level) for the set of data which is to be programmed into the memory cells. This is accomplished by counting the number of programming states which must be traversed in programming the cells with the data. If the majority of the data requires programming the memory cell(s) to the upper two programming states (in the case of a two bit per cell or four state system), then the data is inverted and stored in the memory in the inverted form. This reduces the amount of programming time, the number of programming states traversed, and the power consumed in programming the memory cell(s) with the data field. In the case of data which is encoded using a scheme other than a direct sequential ordering of the threshold voltage levels, the encoded data is converted into an alternate form prior to counting the states. A flag indicating the translation operation (inversion of states, reassignment of states to different levels, etc.) used to assign the existing threshold voltage levels to those that will be programmed into the memory cells is also stored. The flag can be used to indicate the transformation process needed to convert the stored data back to its original form.
摘要翻译：一种用于减少在用给定的一组数据编程多状态存储器单元时需要遍历的编程状态（阈值电压电平）的数量的装置和方法。本发明首先确定要编程到存储器单元中的数据组的平均编程状态（对应于平均阈值电压电平）。这是通过对使用数据编程单元格中必须遍历的编程状态数进行计数来实现的。如果大多数数据需要将存储器单元编程到上两个编程状态（在每个单元或四个状态系统为2位的情况下），则数据被反转并以倒置形式存储在存储器中。这减少了编程时间的数量，遍历的编程状态的数量以及使用数据字段编程存储单元的功耗。在使用除了阈值电压电平的直接顺序排列之外的方案编码的数据的情况下，在对状态进行计数之前将编码数据转换成替代形式。还存储用于将现有阈值电压电平分配给将被编程到存储器单元中的那些的转换操作（状态的反转，状态的重新分配到不同的电平等）的标志。该标志可用于指示将存储的数据转换回其原始形式所需的转换过程。

76. 发明授权

US6073204A Memory system having flexible architecture and method 失效
公开(公告)号：US6073204A
公开(公告)日：2000-06-06
申请号：US839034
申请日：1997-04-23
申请人： Vinod C. Lakhani , Robert D. Norman , Christophe J. Chevallier
发明人： Vinod C. Lakhani , Robert D. Norman , Christophe J. Chevallier
IPC分类号： A22C17/00 , G06F12/06 , G06F12/00
CPC分类号： G06F12/0676
摘要： A memory system having a single memory controller connected to several memory devices by way of a common bus, with the memory controller configured to issue memory program, memory read and memory erase instructions over the system bus to a selected one of the memory devices. Each memory device has an array of memory cells and several volatile control registers which contain control parameters provided by the memory controller. The control parameters operate to control one or more of the voltages applied to the array in memory read, program and erase operations, including the timing of the application of the voltages and the magnitude of the voltages so that the memory operations can be optimized by the memory controller.

77. 发明授权

US5907855A Apparatus and method for reducing programming cycles for multistate memory system 失效
公开(公告)号：US5907855A
公开(公告)日：1999-05-25
申请号：US730099
申请日：1996-10-15
申请人： Robert D. Norman
发明人： Robert D. Norman
IPC分类号： G11C11/56 , G11C11/34 , G06F12/00
CPC分类号： G11C11/5628 , G11C11/56 , G11C11/5621 , G11C2211/5647
摘要： An apparatus and method for reducing the number of programming states (threshold voltage levels) required to be traversed when programming a multistate memory cell with a given set of data. The invention first determines the average programming state (corresponding to an average threshold voltage level) for the set of data which is to be programmed into the memory cells. This is accomplished by counting the number of programming states which must be traversed in programming the cells with the data. If the majority of the data requires programming the memory cell(s) to the upper two programming states (in the case of a two bit per cell or four state system), then the data is inverted and stored in the memory in the inverted form. This reduces the amount of programming time, the number of programming states traversed, and the power consumed in programming the memory cell(s) with the data field. In the case of data which is encoded using a scheme other than a direct sequential ordering of the threshold voltage levels, the encoded data is converted into an alternate form prior to counting the states. A flag indicating the translation operation (inversion of states, reassignment of states to different levels, etc.) used to assign the existing threshold voltage levels to those that will be programmed into the memory cells is also stored. The flag can be used to indicate the transformation process needed to convert the stored data back to its original form.

78. 发明授权

US5657332A Soft errors handling in EEPROM devices 失效
标题翻译： EEPROM器件中的软错误处理
公开(公告)号：US5657332A
公开(公告)日：1997-08-12
申请号：US406677
申请日：1995-03-20
申请人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
发明人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
IPC分类号： G06F11/10 , G11C16/10 , G11C29/50 , G11C29/52 , G11C29/00 , G11C11/34
CPC分类号： G11C29/028 , G11C16/10 , G11C16/3431 , G11C29/50 , G11C29/50004 , G11C29/52 , G06F11/1068 , G06F11/1072 , G06F2201/81 , G11C16/04 , G11C2029/5004 , G11C2029/5006
摘要： Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.
摘要翻译：正常使用固态存储器（如EEPROM或闪存EEPROM）时会发生软错误。存储器单元的编程阈值电压从原来的预期电平漂移导致软错误。在正常读取期间，最初不容易检测到该误差，直到累积漂移变得如此严重以致其发展为硬错误。数据可能会丢失，如果这些硬错误足够的可以在存储器中发出可用的纠错码。一种存储器件及其技术能够在整个使用存储器件的过程中检测这些漂移并且将每个存储器单元的阈值电压基本上保持在其预期的水平，从而抵抗将软错误发展成硬错误。

79. 发明授权

US5562729A Heart valve 失效
标题翻译：心脏瓣膜
公开(公告)号：US5562729A
公开(公告)日：1996-10-08
申请号：US332720
申请日：1994-11-01
申请人： David L. Purdy , James R. Cupp , Frederick J. Shipko , Robert D. Norman
发明人： David L. Purdy , James R. Cupp , Frederick J. Shipko , Robert D. Norman
IPC分类号： A61F2/24
CPC分类号： A61F2/2412 , Y10S623/90
摘要： A multi-leaflet (usually trileaflet) heart valve composed of biocompatible polymer which, in all of its embodiments, simultaneously imitates the structure and dynamics of biological heart valves and avoids promotion of calcification. The valve includes a plurality of flexible leaflets dip cast on a mandrel, which leaflets are then bonded with a bonding agent to the interior surfaces of a plurality of struts on a metal-reinforced prosthetic stent. The leaflets open and close in response to the pumping action of the heart and, due to the design of the leaflets, fatigue resistance of the heart valve is high. The leaflets and the polymer components of the prosthetic stent are manufactured of biocompatible polymers exhibiting intrinsic calcification-resistant properties.
摘要翻译：一种由生物相容性聚合物组成的多叶（通常是三叶草）心脏瓣膜，其在其所有实施方案中同时模仿生物心脏瓣膜的结构和动力学并避免促进钙化。阀包括浸在心轴上的多个柔性传单，然后将这些小叶与粘合剂结合到金属增强的假体支架上的多个支柱的内表面上。响应于心脏的泵送动作，传单打开和关闭，并且由于小叶的设计，心脏瓣膜的抗疲劳性高。假体支架的传单和聚合物组分由表现出固有的抗钙化特性的生物相容性聚合物制成。

80. 发明授权

US5532962A Soft errors handling in EEPROM devices 失效
公开(公告)号：US5532962A
公开(公告)日：1996-07-02
申请号：US408109
申请日：1995-03-21
申请人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
发明人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
IPC分类号： G06F11/10 , G11C16/34 , G11C29/50 , G11C29/00
CPC分类号： G06F11/1008 , G11C16/3418 , G11C16/3431 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C29/028 , G11C29/50 , G11C29/50004 , G06F2201/81 , G11C16/04
摘要： Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

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