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71. 发明授权

US5843625A Method of reducing via and contact dimensions beyond photolithography equipment limits 失效
标题翻译：降低光刻设备限制以外的通孔和接触尺寸的方法
公开(公告)号：US5843625A
公开(公告)日：1998-12-01
申请号：US685144
申请日：1996-07-23
申请人： Fred N. Hause , Mark I. Gardner , Robert Dawson
发明人： Fred N. Hause , Mark I. Gardner , Robert Dawson
IPC分类号： H01L21/768 , G03F7/00
CPC分类号： H01L21/76816
摘要： A semiconductor process for forming an interlevel contact. A semiconductor wafer is provided with a semiconductor substrate, a first conductive layer formed on the substrate, and a dielectric layer formed on the conductive layer. A border layer, preferably comprising polysilicon or silicon nitride is formed on the dielectric layer. Portions of the border layer are then selectively removed to expose an upper surface of a spacer region of the dielectric layer, the selective removal of the border layer resulting in a border layer having an annular sidewall extending upward from the dielectric layer and encircling the spacer region. A spacer structure is then formed on the annular sidewall. Preferably, the spacer structure is formed by chemically vapor depositing a spacer material and anisotropically etching the spacer material to just clear in the planar regions with minimum overetch. The spacer structure thereby covers peripheral portions of the spacer region such that an upper surface of a contact region remains exposed. Portions of the dielectric layer within the contact region are then removed to form a via extending from an upper surface of the spacer structure to an upper surface of the first conductive layer. Preferably, the lateral dimension of the spacer region is approximately equal to the minimum feature size of a photolithography exposure apparatus in the lateral dimension of the via at substantially less than the minimum feature size of the photolithography exposure apparatus.
摘要翻译：一种用于形成层间接触的半导体工艺。半导体晶片设置有半导体衬底，形成在衬底上的第一导电层和形成在导电层上的电介质层。优选地包括多晶硅或氮化硅的边界层形成在电介质层上。然后选择性地去除边界层的部分以暴露电介质层的间隔区域的上表面，选择性地去除边界层，导致边界层具有从电介质层向上延伸并环绕间隔区域的环形侧壁。然后在环形侧壁上形成间隔结构。优选地，通过化学气相沉积间隔物材料并且各向异性地蚀刻间隔物材料来形成间隔结构，以便在具有最小过蚀刻的平面区域中刚好清除。间隔结构由此覆盖间隔区域的周边部分，使得接触区域的上表面保持暴露。然后去除接触区域内的电介质层的部分以形成从间隔物结构的上表面延伸到第一导电层的上表面的通孔。优选地，间隔区域的横向尺寸基本上等于光刻曝光装置在通孔的横向尺寸中的最小特征尺寸，其基本上小于光刻曝光装置的最小特征尺寸。

72. 发明授权

US06365943B1 High density integrated circuit 有权
公开(公告)号：US06365943B1
公开(公告)日：2002-04-02
申请号：US09157644
申请日：1998-09-21
申请人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
发明人： Mark I. Gardner , Daniel Kadosh , Fred N. Hause
IPC分类号： H01L2976
CPC分类号： H01L21/823437 , Y10S438/947
摘要： A semiconductor transistor which includes a silicon base layer, a gate dielectric formed on the silicon base layer, first and second silicon source/drain structures, first and second spacer structures, and a silicon gate structure is provided. A method for forming the semiconductor transistor may include a semiconductor process in which a dielectric layer is formed on an upper surface of a semiconductor substrate which includes a silicon base layer. Thereafter, an upper silicon layer is formed on an upper surface of the dielectric layer. The dielectric layer and the upper silicon layer are then patterned to form first and second silicon-dielectric stacks on the upper surface of the base silicon layer. The first and second silicon-dielectric stacks are laterally displaced on either side of a channel region of the silicon substrate and each include a proximal sidewall and a distal sidewall. The proximal sidewalls are approximately coincident with respective boundaries of the channel region. Thereafter, proximal and distal spacer structures are formed on the proximal and distal sidewalls respectively of the first and second silicon-dielectric stacks. A gate dielectric layer is then formed on exposed portions of the silicon base layer over a channel region of the base silicon layer. Portions of the first and second silicon-dielectric stacks located over respective source/drain regions of the base silicon layer are then selectively removed. Silicon is then deposited to fill first and second voids created by the selected removal of the stacks. The silicon deposition also fills a silicon gate region above the gate dielectric over the channel region. Thereafter, an impurity distribution is introduced into the deposited silicon. The deposited silicon is then planarized to physically isolate the silicon within the gate region from the silicon within the first and second voids resulting in the formation of a transistor including a silicon gate structure and first and second source/drain structures.

73. 发明授权

US06323561B1 Spacer formation for precise salicide formation 失效
标题翻译：间歇形成精确的自杀化合物形成
公开(公告)号：US06323561B1
公开(公告)日：2001-11-27
申请号：US08987455
申请日：1997-12-09
申请人： Mark I. Gardner , Fred N. Hause , Charles E. May
发明人： Mark I. Gardner , Fred N. Hause , Charles E. May
IPC分类号： H01L27088
CPC分类号： H01L29/66598 , H01L21/266 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： The formation of a spacer for precise salicide formation is disclosed. In one embodiment, a method includes four steps. In the first step, at least one first spacer is formed, where each spacer is adjacent to an edge of a gate on a substrate and has a triangular geometry. In the second step, an ion implantation is applied to form a graded lightly doped region within the substrate underneath each spacer, the region corresponding to the triangular geometry of the spacer. In the third step, at least one second spacer is formed, where each second spacer overlaps a corresponding first spacer. In the fourth step, a metal silicide within the substrate is formed immediately adjacent to each second spacer.
摘要翻译：公开了形成用于精确的自对准硅化物形成的间隔物。在一个实施例中，一种方法包括四个步骤。在第一步骤中，形成至少一个第一间隔物，其中每个间隔物邻近衬底上的栅极的边缘并且具有三角形几何形状。在第二步骤中，施加离子注入以在每个间隔物下面的衬底内形成渐变的轻掺杂区域，该区域对应于间隔物的三角形几何形状。在第三步骤中，形成至少一个第二间隔物，其中每个第二间隔物与相应的第一间隔物重叠。在第四步骤中，衬底内的金属硅化物紧邻每个第二间隔物形成。

74. 发明授权

US6117739A Semiconductor device with layered doped regions and methods of manufacture 有权
标题翻译：具有分层掺杂区域的半导体器件和制造方法
公开(公告)号：US6117739A
公开(公告)日：2000-09-12
申请号：US166000
申请日：1998-10-02
申请人： Mark I. Gardner , Fred N. Hause , Charles E. May
发明人： Mark I. Gardner , Fred N. Hause , Charles E. May
IPC分类号： H01L21/266 , H01L21/336 , H01L29/10 , H01L29/49
CPC分类号： H01L29/66583 , H01L21/266 , H01L29/1083 , H01L29/4966 , H01L29/66537
摘要： A semiconductor device can be formed with active regions disposed in a substrate adjacent to a gate electrode and a doped region, of the same conductivity type as the active regions, embedded beneath the channel region defined by the active regions. In one embodiment, a patterned masking layer having at least one opening is formed over the substrate. A dopant material is implanted into the substrate using the masking layer to form active regions adjacent to the opening and an embedded doped region that is between and spaced apart from the active regions and is deeper in the substrate then the active regions. In addition or alternatively, spacer structures can be formed on the gate electrode by forming a conformal dielectric layer along a bottom surface and at least one sidewall of the opening and forming a gate electrode in the opening over the dielectric layer. The masking layer is then removed to leave the dielectric layer between the gate electrode and the substrate and as spacer structures on the sidewalls of the gate electrode.
摘要翻译：可以形成半导体器件，该有源区域设置在与由栅极电极相邻的衬底中的有源区域和与有源区域相同的导电类型的掺杂区域，嵌入在由有源区域限定的沟道区域的下面。在一个实施例中，在衬底上形成具有至少一个开口的图案化掩模层。使用掩模层将掺杂剂材料注入到衬底中以形成与开口相邻的有源区和位于有源区之间并且与有源区间隔开的嵌入的掺杂区，并且在衬底中更深的是有源区。另外或替代地，可以通过沿着底表面和开口的至少一个侧壁形成保形电介质层并在电介质层上的开口中形成栅电极，在栅电极上形成间隔结构。然后去除掩模层以在栅电极和衬底之间留下介电层，并且作为栅电极的侧壁上的间隔结构。

75. 发明授权

US6087249A Transistor fabrication process employing a common chamber for gate oxide and gate conductor formation 有权
标题翻译：晶体管制造工艺采用公共室进行栅极氧化和栅极导体的形成
公开(公告)号：US6087249A
公开(公告)日：2000-07-11
申请号：US151075
申请日：1998-09-10
申请人： Mark I. Gardner , Fred N. Hause
发明人： Mark I. Gardner , Fred N. Hause
IPC分类号： C23C16/40 , C23C16/452 , H01L21/28 , H01L21/314 , H01L29/51 , H01L21/3205
CPC分类号： H01L21/28202 , C23C16/402 , C23C16/452 , H01L21/28017 , H01L21/28035 , H01L21/3145 , H01L29/513 , H01L29/518 , H01L21/28185 , Y10S438/907 , Y10S438/908
摘要： An integrated circuit transistor is provided having a gate oxide and a gate conductor arranged upon a semiconductor topography, the gate oxide and gate conductor are formed within a common chamber. The initial semiconductor topography includes a silicon substrate having isolation regions disposed within its upper surface. The semiconductor topography may include an defined region, or well, doped opposite the substrate. The semiconductor topography is first placed in the common chamber. A separate chamber is operably placed gaseous communication with the common chamber. A plasma is created within the separate chamber, causing nitrogen, silicon, and oxygen containing compounds therein to form ions, molecular fragments, and excited molecules which are transported to the common chamber. The ions, molecular fragments, and excited molecules react and bombard the surface of the semiconductor topography to form an oxide layer thereon. The oxide layer is incorporated with nitrogen atoms which act as barrier atoms. Polysilicon is then deposited upon the oxide layer by CVD within the common chamber. The semiconductor topography is never exposed to ambient conditions outside the common chamber during and between the plasma oxide formation and the polysilicon deposition steps. Preventing ingress of outside ambient helps minimize contamination from entering the oxide. During the polysilicon deposition, dopant atoms are forwarded and become entrained within the polysilicon. The barrier atoms within the deposited oxide helps minimize dopant atoms from passing through the oxide and entering the channel below the oxide.
摘要翻译：提供一种集成电路晶体管，其具有栅极氧化物和布置在半导体形貌上的栅极导体，栅极氧化物和栅极导体形成在公共室内。初始半导体形貌包括具有设置在其上表面内的隔离区的硅衬底。半导体形貌可以包括与衬底相对掺杂的限定区域或阱。首先将半导体形貌放置在公共室中。独立的腔室可操作地与公共腔室气体连通。在分离的室内产生等离子体，在其中产生氮，硅和含氧化合物，以形成被输送到公共室的离子，分子片段和被激发的分子。离子，分子片段和激发的分子反应并轰击半导体形貌的表面以在其上形成氧化物层。氧化物层与作为阻挡原子的氮原子结合。然后通过CVD在公共室内将多晶硅沉积在氧化物层上。在等离子体氧化物形成和多晶硅沉积步骤期间和之间，半导体形貌从未暴露于公共室外的环境条件。防止外界进入有助于最大限度地减少进入氧化物的污染。在多晶硅沉积期间，掺杂剂原子被转移并被夹带在多晶硅内。沉积的氧化物内的阻挡原子有助于最小化掺杂剂原子通过氧化物并进入氧化物下方的通道。

76. 发明授权

US6018179A Transistors having a scaled channel length and integrated spacers with enhanced silicidation properties 有权
标题翻译：具有缩放沟道长度的晶体管和具有增强的硅化特性的集成间隔物
公开(公告)号：US6018179A
公开(公告)日：2000-01-25
申请号：US187028
申请日：1998-11-05
申请人： Mark I. Gardner , Fred N. Hause , Derick J. Wristers
发明人： Mark I. Gardner , Fred N. Hause , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/311 , H01L21/321 , H01L21/336 , H01L29/423 , H01L29/51 , H01L27/088
CPC分类号： H01L21/28194 , H01L21/28114 , H01L21/28123 , H01L21/28202 , H01L21/31116 , H01L29/42376 , H01L29/513 , H01L29/518 , H01L29/66583 , H01L29/6659 , H01L21/3212 , Y10S257/90
摘要： A high speed MOS device has a scaled channel length and integrated spacers. The MOS device is formed on a substrate having active and isolation regions. In constructing the MOS device wells and Vt regions are formed as required. Then, a thin nitride layer is formed upon the substrate. Subsequently, an oxide layer is formed upon the nitride layer. Then, the oxide layer is pattern masked to expose gate regions. The gate regions are sloped etched to form slope etched voids. The slope etching may proceed to the nitride layer, through a portion of the nitride layer or fully through the nitride layer, depending upon the embodiment. In another embodiment, the nitride layer is not deposed and the oxide layer is either fully or partially slope etched to the silicon substrate. The patterned mask is then removed and remaining portions of the nitride layer may be converted to an oxynitride. Additionally, a gate oxide may be formed. The slope etched void is then filled with a gate conductor and the surface is planarized in a CMP process. The gate conductor then has a shape wherein its lower surface is smaller than its upper surface. Then, the substrate is isotropically etched to remove portions of the oxide layer and nitride layer unprotected by the gate conductor. The remaining structure includes integrally formed spacers. Active regions, LDD regions and punchthrough regions are then formed to complete formation of the transistor.
摘要翻译：高速MOS器件具有缩放的沟道长度和集成间隔物。 MOS器件形成在具有有源和隔离区域的衬底上。在构建MOS器件时，根据需要形成Vt区域。然后，在基板上形成薄的氮化物层。随后，在氮化物层上形成氧化物层。然后，将氧化层图案掩模以露出栅极区域。栅极区被倾斜蚀刻以形成斜坡蚀刻的空隙。根据实施例，倾斜蚀刻可以通过氮化物层的一部分或完全通过氮化物层而进行到氮化物层。在另一个实施例中，氮化物层不被沉积，并且氧化物层被完全或部分地倾斜蚀刻到硅衬底。然后去除图案化掩模，并且可以将氮化物层的剩余部分转化为氮氧化合物。另外，可以形成栅极氧化物。然后用栅极导体填充斜面蚀刻的空隙，并且在CMP工艺中平坦化表面。然后，栅极导体具有其下表面小于其上表面的形状。然后，各向同性蚀刻衬底，以除去未被栅极导体保护的氧化物层和氮化物层的部分。其余结构包括一体形成的间隔物。然后形成有源区，LDD区和穿透区，以完成晶体管的形成。

77. 发明授权

US5912493A Enhanced oxidation for spacer formation integrated with LDD implantation 失效
标题翻译：与LDD植入相结合的间隔物形成的增强氧化
公开(公告)号：US5912493A
公开(公告)日：1999-06-15
申请号：US970263
申请日：1997-11-14
申请人： Mark I. Gardner , Fred N. Hause , Charles E. May
发明人： Mark I. Gardner , Fred N. Hause , Charles E. May
IPC分类号： H01L21/336 , H01L29/08 , H01L29/10 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/66575 , H01L29/0847 , H01L29/107
摘要： A method for forming a semiconductor device to produce graded doping in the source region and the drain region includes the steps of forming a gate on the surface of the substrate separated from the substrate by a gate oxide, and applying a first ion implantation to implant lightly doped source and drain regions into the substrate, and implanting a material to a portion of the gate oxide over the source region and a portion of the gate oxide over the drain region to vary the rate of oxide formation. An oxide layer is then formed. The resulting oxide layer has at least two thicknesses. Another ion implantation is applied through the formed oxide layer. The ion implantation converts a portion of the lightly doped source region into a heavily doped source region, and converts a portion of the lightly doped drain region into a heavily doped drain region. The implanted ions travel a set distance through the oxide layer formed and into the substrate and more specifically into the source and drain regions formed in the substrate. Therefore, the geometry of the interface between the lightly doped region and the heavily doped region in the source region and the drain region depends on the geometry (thickness and pattern) of oxide layer formed. A set of spacers can also be added after lightly doping the substrate to form the Ldd source and Ldd drain. The geometry of the spacers will also then effect the geometry of the interface between the lightly doped and heavily doped regions within the source and the drain. Also disclosed is a device made by this process as well as an information handling system including such a device.
摘要翻译：一种形成半导体器件以在源极区域和漏极区域中产生渐变掺杂的方法包括以下步骤：通过栅极氧化物在衬底的表面上形成栅极，并施加第一离子注入以轻微地注入掺杂的源极和漏极区域进入衬底，并且将材料注入源极区域上的栅极氧化物的一部分和在漏极区域上的栅极氧化物的一部分以改变氧化物形成速率。然后形成氧化物层。所得到的氧化物层具有至少两个厚度。通过形成的氧化物层施加另一离子注入。离子注入将轻掺杂源区的一部分转换为重掺杂源区，并将轻掺杂漏区的一部分转换为重掺杂漏极区。注入的离子通过形成的氧化物层进入设置的距离，并进一步具体地进入形成在衬底中的源区和漏区。因此，源极区域和漏极区域中的轻掺杂区域和重掺杂区域之间的界面的几何形状取决于形成的氧化物层的几何形状（厚度和图案）。在轻掺杂衬底以形成Ldd源和Ldd漏极之后，也可以添加一组间隔物。间隔物的几何形状还将影响源极和漏极之间的轻掺杂区域和重掺杂区域之间的界面的几何形状。还公开了通过该方法制造的装置以及包括这种装置的信息处理系统。

78. 发明授权

US5885879A Thin polysilicon masking technique for improved lithography control 失效
标题翻译：薄多晶硅掩模技术，用于改进光刻控制
公开(公告)号：US5885879A
公开(公告)日：1999-03-23
申请号：US822941
申请日：1997-03-21
申请人： Mark I. Gardner , Fred N. Hause
发明人： Mark I. Gardner , Fred N. Hause
IPC分类号： H01L21/28 , H01L21/316 , H01L21/768 , H01L21/336
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/28123 , H01L21/31662 , H01L21/76895
摘要： A process for fabricating a semiconductor transistor in which a semiconductor substrate is provided and a gate dielectric layer formed on an upper surface of the semiconductor substrate. A base conductive layer is then deposited on an upper surface of the gate dielectric layer. The base conductive layer is patterned to form base sections of a first and a second gate structure. Source/drain impurity distributions are introduced into the semiconductor substrate using the base sections as a mask to form source/drain structures within the semiconductor substrate. An insulating support layer is then formed on a topography defined by the semiconductor substrate and the base section. The insulating support layer is planarized until an upper surface of the insulating support layer is substantially planar with upper surfaces of the base sections. A second conductive layer is then deposited. The second conductive layer includes gate portions and interconnect portions. The gate portions reside above the base sections of the first and second gate structures. The interconnect portions reside above the insulating support layer. The second conductive layer is then patterned by removing selected areas of the interconnect portions of the second conductive layer. This process completes the first and second gate structures wherein each of the gate structures includes the base section and the gate portion of the second conductive layer. In this manner, a completed thickness of the first and second gate structures is greater than a thickness of the gate structures prior to the introduction of the source/drain impurity distributions.
摘要翻译：一种半导体晶体管的制造方法，其中设置半导体衬底和形成在半导体衬底的上表面上的栅介质层。然后将基底导电层沉积在栅极介电层的上表面上。图案化基底导电层以形成第一和第二栅极结构的基极部分。源极/漏极杂质分布被引入半导体衬底中，使用基极部分作为掩模，以在半导体衬底内形成源极/漏极结构。然后在由半导体衬底和基底部分限定的形貌上形成绝缘支撑层。绝缘支撑层被平坦化，直到绝缘支撑层的上表面与基部的上表面基本平坦。然后沉积第二导电层。第二导电层包括栅极部分和互连部分。栅极部分位于第一和第二栅极结构的基极部分之上。互连部分位于绝缘支撑层之上。然后通过去除第二导电层的互连部分的选定区域来图案化第二导电层。该过程完成了第一和第二栅极结构，其中每个栅极结构包括基极部分和第二导电层的栅极部分。以这种方式，在引入源极/漏极杂质分布之前，第一和第二栅极结构的完成厚度大于栅极结构的厚度。

79. 发明授权

US06661061B1 Integrated circuit with differing gate oxide thickness 有权
标题翻译：具有不同栅极氧化物厚度的集成电路
公开(公告)号：US06661061B1
公开(公告)日：2003-12-09
申请号：US09207437
申请日：1998-12-08
申请人： Mark I. Gardner , Fred N. Hause
发明人： Mark I. Gardner , Fred N. Hause
IPC分类号： H01L2978
CPC分类号： H01L27/0922 , H01L21/823857 , Y10S438/981
摘要： A semiconductor process for producing two gate oxide thicknesses within an integrated circuit in which a semiconductor substrate having a first region and a second region is provided. The first region and the second region are laterally displaced with respect to one another. A nitrogen species impurity distribution is then introduced into the first region of the semiconductor substrate. Thereafter, a gate dielectric layer is grown on an upper surface of the semiconductor substrate. The gate dielectric has a first thickness over the first region of the semiconductor substrate and a second thickness over the second region of the semiconductor substrate. The first thickness is less than the second thickness. In a CMOS embodiment of the present invention, the first region of the semiconductor substrate comprises p-type silicon while the second substrate region comprises n-type silicon. Preferably, the step of introducing the nitrogen species impurity distribution into the semiconductor substrate is accomplished by thermally oxidizing the first substrate region in a nitrogen bearing ambient. In a presently preferred embodiment, the nitrogen bearing ambient includes N2O, NH3, O2 and HCl in an approximate ratio of 60:30:7:3. In alternative embodiments the nitrogen bearing ambient includes NO, O2 and HCl in an approximate ratio of 90:7:3 or N2O, O2 and HCl in an approximate ratio of 90:7:3. The introduction of the nitrogen species impurity into first substrate region 102 may alternatively be accomplished with rapid thermal anneal processing.
摘要翻译：一种用于在集成电路内产生两个栅极氧化物厚度的半导体工艺，其中提供具有第一区域和第二区域的半导体衬底。第一区域和第二区域相对于彼此横向移位。然后将氮物质杂质分布引入半导体衬底的第一区域。此后，在半导体衬底的上表面上生长栅极电介质层。栅极电介质在半导体衬底的第一区域上具有第一厚度，并且在半导体衬底的第二区域上具有第二厚度。第一厚度小于第二厚度。在本发明的CMOS实施例中，半导体衬底的第一区域包括p型硅，而第二衬底区域包括n型硅。优选地，将氮物质杂质分布引入半导体衬底的步骤是通过在含氮环境中热氧化第一衬底区域来实现的。在目前优选的实施方案中，含氮环境包括大约比例为60:30:7:3的N2O，NH3，O2和HCl。在替代实施方案中，含氮环境包括大约比例为90:7:3的N，O 2和HCl，N 2 O，O 2和HCl的比例大约为90:7:3。可以通过快速热退火处理来实现将氮物质杂质引入到第一衬底区域102中。

80. 发明授权

US6165858A Enhanced silicidation formation for high speed MOS device by junction grading with dual implant dopant species 有权
标题翻译：通过具有双注入掺杂物种的连接分级来增强用于高速MOS器件的硅化物形成
公开(公告)号：US6165858A
公开(公告)日：2000-12-26
申请号：US200143
申请日：1998-11-25
申请人： Mark I. Gardner , Fred N. Hause , Jon C. Cheek
发明人： Mark I. Gardner , Fred N. Hause , Jon C. Cheek
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238
CPC分类号： H01L29/665 , H01L21/26513 , H01L21/823814 , H01L21/823835
摘要： A method of making a MOS transistors in an integrated circuit includes forming a plurality of doped source and drain regions adjacent respective gate structures that include gate dielectrics, gate conductors and spacers. The plurality of doped source and drain regions are formed at different depths, at different doses and with differing dopants. In one embodiment, first doped source and drain regions are formed at a first depth, at a first dose using a first dopant while second doped source and drain regions are formed at a second depth, at a second dose using a second dopant. The first depth is shallower than the second depth so that the first doped source and drain regions serve as sacrificial doped regions that are consumed in a silicidation process when they are converted into a silicide by being combined with a silicidation metal. However, the second doped source and drain regions maintain their doping profiles and dopant levels. The implant energy of the dopants depends upon their molecular weight and desired doping depths. The dose of such doping depends upon desired drive current and other characteristics of the transistors.
摘要翻译：在集成电路中制造MOS晶体管的方法包括在包括栅极电介质，栅极导体和间隔物的各个栅极结构附近形成多个掺杂源极和漏极区域。多个掺杂源极和漏极区域以不同的深度，不同的剂量和不同的掺杂剂形成。在一个实施例中，使用第一掺杂剂以第一剂量在第一深度处形成第一掺杂源极和漏极区，而使用第二掺杂剂以第二剂量在第二深度形成第二掺杂源极和漏极区。第一深度比第二深度浅，使得第一掺杂源极和漏极区域用作牺牲掺杂区域，当硅化物通过与硅化物金属组合而转化为硅化物时，其在硅化工艺中被消耗。然而，第二掺杂源极和漏极区域保持其掺杂分布和掺杂剂水平。掺杂剂的注入能量取决于它们的分子量和所需的掺杂深度。这种掺杂的剂量取决于期望的驱动电流和晶体管的其它特性。

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