专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US5981363A Method and apparatus for high performance transistor devices 失效
标题翻译：高性能晶体管器件的方法和装置
公开(公告)号：US5981363A
公开(公告)日：1999-11-09
申请号：US193447
申请日：1998-11-17
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L29/51 , H01L29/78 , H01L21/3205
CPC分类号： H01L29/66659 , H01L21/2815 , H01L21/823425 , H01L21/823468 , H01L29/6656 , H01L29/7835 , H01L21/28194 , H01L21/28202 , H01L29/51 , H01L29/517 , H01L29/518 , Y10S438/947
摘要： The present invention is directed to a method for forming a semiconductor device having a reduced channel length. The method comprises forming a layer of a dielectric material above a surface of a semiconducting substrate, and forming a layer of polysilicon above the layer of dielectric material. The method further comprises forming a layer of silicon nitride or silicon oxynitride above the layer of polysilicon, and patterning said layer of polysilicon and layer of silicon nitride or silicon oxynitride to define an opening and expose a sidewall surface of the polysilicon layer. The method continues with the growth of a lateral extension of the polysilicon layer and the oxidation of the extension. The method concludes with the patterning of the polysilicon layer to define a gate conductor, and the formation of source and drain regions in the substrate.
摘要翻译：本发明涉及一种形成具有减小的通道长度的半导体器件的方法。该方法包括在半导体衬底的表面上方形成电介质材料层，以及在介电材料层之上形成多晶硅层。该方法还包括在多晶硅层之上形成氮化硅或氮氧化硅层，以及图案化所述多晶硅层和氮化硅层或氮氧化硅层以限定开口并暴露多晶硅层的侧壁表面。该方法继续扩展多晶硅层的横向延伸和延伸的氧化。该方法结束于多晶硅层的图案化以限定栅极导体，以及在衬底中形成源极和漏极区域。

72. 发明授权

US3939048A Process for making anhydrous metal halides 失效
标题翻译：制备无水金属卤化物的方法
公开(公告)号：US3939048A
公开(公告)日：1976-02-17
申请号：US527728
申请日：1974-11-27
申请人： Warren H. Philipp , Stanley J. Marsik , Charles E. May
发明人： Warren H. Philipp , Stanley J. Marsik , Charles E. May
IPC分类号： B01J19/08 , C01G1/06 , B01J1/10
CPC分类号： B01J19/081 , C01G1/06
摘要： A process for the preparation and isolation of high purity anhydrous lower valence state metal halides comprising dissolving the corresponding higher valence state metal halide of the desired lower valence state metal halide in an organic liquid, which is selected such that the higher valence state metal halide is soluble therein and the lower valence state metal halide is insoluble therein, and subjecting the solution to high energy radiation which reduces the higher valence state metal halide to its corresponding lower valence state metal halide, at a temperature in the range of from about 0.degree.C. to about room temperature.
摘要翻译：一种制备和分离高纯度无水低价态金属卤化物的方法，包括将所需低价态金属卤化物的相应较高价态的金属卤化物溶解在有机液体中，该有机液体被选择为使得较高价态的金属卤化物为可溶于其中，低价态的金属卤化物不溶于其中，并且将溶液进行高能辐射，其将较高价态金属卤化物还原成其相应的低价态金属卤化物，温度范围为约0℃ 至约室温。

73. 发明授权

US07601643B1 Arrangement and method for fabricating a semiconductor wafer 失效
标题翻译：用于制造半导体晶片的布置和方法
公开(公告)号：US07601643B1
公开(公告)日：2009-10-13
申请号：US09943196
申请日：2001-08-30
申请人： Charles E. May
发明人： Charles E. May
IPC分类号： H01L21/302
CPC分类号： H01L21/02074 , B24B37/042 , B24B57/02 , H01L21/3212
摘要： An arrangement and method for fabricating a semiconductor wafer which utilizes a nonaqueous solvent rinse is disclosed.
摘要翻译：公开了一种使用非水溶剂漂洗的半导体晶片的制造方法和方法。

74. 发明授权

US06875693B1 Via and metal line interface capable of reducing the incidence of electro-migration induced voids 有权
标题翻译：通孔和金属线接口能够减少电迁移引起的空隙的发生
公开(公告)号：US06875693B1
公开(公告)日：2005-04-05
申请号：US10400297
申请日：2003-03-26
申请人： Charles E. May , Wilbur G. Catabay
发明人： Charles E. May , Wilbur G. Catabay
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76844
摘要： Embodiments of the invention include a method for forming copper interconnect structure. The method involves providing a substrate having a copper conductive layer formed thereon. An insulating layer having openings is formed on the conductive layer so that the openings expose portions of the underlying conductive layer at the bottom of the openings. A barrier layer is formed on the surface of the substrate. A portion of the barrier layer is removed at the bottom of the opening to expose the underlying conductive layer. A copper plug is formed in the opening such that the bottom of the plug is in contact with the exposed conductive layer. The substrate can be subjected to further processing if desired. The invention also includes a copper interconnect structure having increased resistance to electromigration.
摘要翻译：本发明的实施例包括一种形成铜互连结构的方法。该方法包括提供其上形成有铜导电层的基板。具有开口的绝缘层形成在导电层上，使得开口暴露在开口底部的下面的导电层的部分。在衬底的表面上形成阻挡层。阻挡层的一部分在开口的底部被去除以暴露下面的导电层。在开口中形成铜塞，使得插头的底部与暴露的导电层接触。如果需要，可以对衬底进行进一步处理。本发明还包括具有增加的电迁移阻力的铜互连结构。

75. 发明授权

US06620729B1 Ion beam dual damascene process 失效
标题翻译：离子束双镶嵌工艺
公开(公告)号：US06620729B1
公开(公告)日：2003-09-16
申请号：US09952343
申请日：2001-09-14
申请人： Charles E. May
发明人： Charles E. May
IPC分类号： H01L214763
CPC分类号： H01L21/76807 , H01L21/31111 , H01L21/31144
摘要： A dual-damascene process for forming an integrated circuit structure is described. The process includes forming a trench in a dielectric substrate, and forming a via mask layer over the dielectric substrate and the trench. An aperture is formed in the via mask layer overlying the trench, thereby exposing a portion of the underlying dielectric substrate. The exposed portion of the dielectric substrate is subjected to an ion beam to damage the exposed dielectric material. The damaged portion of the dielectric substrate is then removed, such as by etching, thereby forming a via cavity below the trench in the dielectric substrate. Generally, the damaged portion of the dielectric substrate etches at a faster rate than do adjacent non-damaged regions. With a faster etch, there is practically no outward spreading of the via cavity as the etch proceeds downward through the dielectric substrate, thereby forming a via cavity wall that is very nearly vertical. More precise control of via cavity geometry provides for more precise alignment of the via cavity with underlying conductors in the integrated circuit structure.
摘要翻译：描述了一种用于形成集成电路结构的双镶嵌工艺。该工艺包括在电介质衬底中形成沟槽，并在电介质衬底和沟槽上形成通孔掩模层。在覆盖沟槽的通孔掩模层中形成一个孔，从而暴露出一部分下面的电介质基片。电介质基板的暴露部分经受离子束以损坏暴露的电介质材料。然后例如通过蚀刻去除电介质基板的损坏部分，从而在电介质基板中的沟槽下方形成通孔。通常，电介质基片的损坏部分以比相邻的未损坏区域更快的速度蚀刻。通过更快的蚀刻，当蚀刻通过电介质衬底向下延伸时，通孔腔几乎没有向外扩散，从而形成非常接近垂直的通孔腔壁。通孔的几何形状的更精确的控制提供了通孔腔与集成电路结构中底层导体的更精确对准。

76. 发明授权

US06544829B1 Polysilicon gate salicidation 有权
标题翻译：多晶硅栅盐化
公开(公告)号：US06544829B1
公开(公告)日：2003-04-08
申请号：US10251016
申请日：2002-09-20
申请人： Venkatesh Gopinath , Mohammad Mirabedini , Charles E. May , Arvind Kamath
发明人： Venkatesh Gopinath , Mohammad Mirabedini , Charles E. May , Arvind Kamath
IPC分类号： H01L218238
CPC分类号： H01L21/823835 , H01L21/823814 , H01L21/823878
摘要： A method of fabricating a substantially completely silicided polysilicon gate electrode in a CMOS process flow. A hard mask material is formed on an integrated circuit substrate, where the integrated circuit substrate includes an unpatterned polysilicon layer that overlies a gate oxide layer, and a well region disposed between isolation structures. Portions of the hard mask material are removed to define gate electrode masks that overlie first portions of the unpatterned polysilicon layer and the gate oxide layer, leaving exposed second portions of the unpatterned polysilicon layer and the gate oxide layer. The integrated circuit substrate is exposed to a dopant that passes through the second portions of the gate oxide layer but does not penetrate the first portions of the gate oxide layer that underlie the gate electrode masks, which defines source drain regions in the well region. The exposed second portions of the unpatterned polysilicon layer are removed to define polysilicon gate electrode precursors under the gate electrode masks. The gate electrode masks are removed from the polysilicon gate electrode precursors, and a metal layer is deposited over the polysilicon gate electrode precursors and the source drain regions. The integrated circuit substrate is annealed to substantially completely consume the polysilicon gate electrode precursors and form silicide gate electrodes from the polysilicon gate electrode precursors and the overlying metal layer, by which silicide contacts in the source drain regions are also formed.
摘要翻译：一种在CMOS工艺流程中制造基本上完全硅化的多晶硅栅电极的方法。在集成电路基板上形成硬掩模材料，其中集成电路基板包括覆盖在栅极氧化物层上的未图案化的多晶硅层和设置在隔离结构之间的阱区域。去除硬掩模材料的部分以限定覆盖未图案化多晶硅层和栅极氧化物层的第一部分的栅电极掩模，留下未图案化的多晶硅层和栅极氧化物层的暴露的第二部分。集成电路基板暴露于穿过栅极氧化物层的第二部分但不穿过限定阱区中的源极漏极区域的栅极电极掩模之下的栅极氧化物层的第一部分的掺杂剂。去除未图案化的多晶硅层的暴露的第二部分以在栅极电极掩模下限定多晶硅栅电极前体。栅极电极掩模从多晶硅栅电极前驱体去除，并且金属层沉积在多晶硅栅极电极前体和源极漏极区上。将集成电路基板退火以基本上完全消耗多晶硅栅极电极前体，并从多晶硅栅极电极前体和上覆金属层形成硅化物栅极电极，由此源极漏极区域中的硅化物接触也形成。

77. 发明授权

US06531364B1 Advanced fabrication technique to form ultra thin gate dielectric using a sacrificial polysilicon seed layer 有权
标题翻译：使用牺牲多晶硅种子层形成超薄栅极电介质的先进制造技术
公开(公告)号：US06531364B1
公开(公告)日：2003-03-11
申请号：US09129703
申请日：1998-08-05
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21336
CPC分类号： H01L21/28202 , H01L21/28211 , H01L29/513 , H01L29/518
摘要： A method is presented for forming a transistor wherein polysilicon is preferably deposited upon a dielectric-covered substrate to form a sacrificial polysilicon layer. The sacrificial polysilicon layer may then be reduced to a desired thickness. Thickness reduction of the sacrificial polysilicon layer is preferably undertaken by oxidizing a portion of the sacrificial polysilicon layer and then etching the oxidized portion. As an option, the sacrificial polysilicon layer may be heated such that it is recrystallized. The sacrificial polysilicon layer is preferably annealed in a nitrogen-bearing ambient such that it is converted to a gate dielectric layer that includes nitride. Polysilicon may be deposited upon the gate dielectric layer, and select portions of the polysilicon may be removed to form a gate conductor. LDD and source/drain areas may be formed adjacent to the gate conductor.
摘要翻译：提出了一种用于形成晶体管的方法，其中多晶硅优选沉积在介电覆盖的衬底上以形成牺牲多晶硅层。然后可以将牺牲多晶硅层还原成所需的厚度。牺牲多晶硅层的厚度减少优选通过氧化牺牲多晶硅层的一部分然后蚀刻氧化部分进行。作为选择，可以加热牺牲多晶硅层使其重结晶。牺牲多晶硅层优选在含氮环境中退火，使得其被转换成包括氮化物的栅极电介质层。多晶硅可以沉积在栅极介电层上，并且可以去除多晶硅的部分以形成栅极导体。 LDD和源极/漏极区域可以形成在栅极导体附近。

78. 发明授权

US06323519B1 Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabrication process 有权
标题翻译：使用低温半导体制造工艺的超薄，含氮MOSFET侧壁间隔物
公开(公告)号：US06323519B1
公开(公告)日：2001-11-27
申请号：US09177871
申请日：1998-10-23
申请人： Mark I. Gardner , Derick J. Wristers , Charles E. May
发明人： Mark I. Gardner , Derick J. Wristers , Charles E. May
IPC分类号： H01L2976
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/3144 , H01L29/4983 , H01L29/665 , H01L29/6656
摘要： A transistor and a method for making a transistor are described. A gate conductor is patterned over a gate dielectric upon a semiconductor substrate. Dopant impurity distributions self-aligned to the gate conductor may be introduced. A conformal oxide having thickness between about 100 angstroms and 500 angstroms is deposited over the gate conductor and substrate. The oxide is exposed to a nitrogen-bearing plasma for conversion to nitrided oxide. Anisotropic etching may then be used to form ultrathin, nitrided oxide spacers. Introduction of a second dopant impurity distribution may be performed to create source-drain regions having narrow LDD regions, and resulting decreased series resistance and increased saturated drain current. Thicker spacers or spacers combining oxide and nitrided oxide portions may firther be formed by repeated deposition of thin conformal oxides. The presence of nitrogen in nitrided oxide portions of the spacers is believed to help prevent dopant outdiffusion from adjacent silicon, prevent silicide bridging across spacers, and increase resistance of the spacers to oxide etchants.
摘要翻译：描述晶体管和制造晶体管的方法。在半导体衬底上的栅极电介质上形成栅极导体。可以引入与栅极导体自对准的掺杂杂质分布。在栅极导体和衬底上沉积厚度在约100埃和500埃之间的共形氧化物。将氧化物暴露于含氮等离子体以转化为氮化氧化物。然后可以使用各向异性蚀刻来形成超薄，氮化的氧化物间隔物。可以引入第二掺杂剂杂质分布以产生具有窄LDD区域的源极 - 漏极区域，并且导致降低的串联电阻和增加的饱和漏极电流。结合氧化物和氮化氧化物部分的较厚的间隔物或间隔物可以通过重复沉积薄的共形氧化物而形成。认为间隔物的氮化氧化物部分中存在氮气有助于防止掺杂剂从相邻硅中扩散，从而防止跨越间隔物的硅化物桥接，并增加间隔物对氧化物蚀刻剂的电阻。

79. 发明授权

US06303962B1 Dielectrically-isolated transistor with low-resistance metal source and drain formed using sacrificial source and drain structures 有权
标题翻译：具有低电阻金属源和漏极的绝缘隔离晶体管，使用牺牲源极和漏极结构形成
公开(公告)号：US06303962B1
公开(公告)日：2001-10-16
申请号：US09227512
申请日：1999-01-06
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： A01L2701
CPC分类号： H01L29/66757 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/41733 , H01L29/78675
摘要： A transistor is provided and formed using self-aligned low-resistance source and drain regions within a metal-oxide semiconductor (MOS) process. The gate of the transistor may also be formed from a low-resistance material such as a metal. The transistor channel is located in a polysilicon layer arranged over a dielectric layer on a semiconductor substrate. To fabricate the transistor, an isolating dielectric, polysilicon layer, and protective dielectric layer are deposited over a semiconductor substrate. Source/drain trenches are formed in the protective dielectric and polysilicon layers and subsequently filled with sacrificial dielectrics. The protective dielectric lying between these sacrificial dielectrics is removed, and replaced with sidewall spacers, a gate dielectric, and a gate conductor which may be formed from a low-resistance metal. The sacrificial dielectrics are subsequently removed and replaced with source/drain regions which may be formed from a low-resistance metal. The resulting transistor may exhibit low contact and series resistances, and increased operation speed.
摘要翻译：在金属氧化物半导体（MOS）工艺中，使用自对准的低电阻源极和漏极区域提供并形成晶体管。晶体管的栅极也可以由诸如金属的低电阻材料形成。晶体管沟道位于布置在半导体衬底上的电介质层上的多晶硅层中。为了制造晶体管，在半导体衬底上沉积隔离电介质，多晶硅层和保护电介质层。源极/漏极沟槽形成在保护电介质层和多晶硅层中，随后填充有牺牲电介质。位于这些牺牲电介质之间的保护电介质被去除，并被替代为可由低电阻金属形成的侧壁间隔物，栅极电介质和栅极导体。随后去除牺牲电介质并用可由低电阻金属形成的源极/漏极区域代替。所得到的晶体管可以表现出低接触和串联电阻，并且增加了操作速度。

80. 发明授权

US06255215B1 Semiconductor device having silicide layers formed using a collimated metal layer 有权
标题翻译：具有使用准直金属层形成的硅化物层的半导体器件
公开(公告)号：US06255215B1
公开(公告)日：2001-07-03
申请号：US09175652
申请日：1998-10-20
申请人： Fred Hause , Charles E. May , William S. Brennan
发明人： Fred Hause , Charles E. May , William S. Brennan
IPC分类号： H01L2144
CPC分类号： H01L21/28518
摘要： A process for forming a silicide layer using a metal layer formed by collimated deposition is provided. The collimated metal layer may, for example, be formed by sputtering metal particles and filtering the metal particles prior to forming the metal layer. By depositing metal in this manner, the resistance of the resultant metal silicide layer can be reduced as compared to metal silicide layers formed using conventional techniques. Lower silicidation reaction temperatures may also be employed.
摘要翻译：提供了使用通过准直沉积形成的金属层形成硅化物层的工艺。准直金属层可以例如通过溅射金属颗粒并在形成金属层之前过滤金属颗粒来形成。通过以这种方式沉积金属，与使用常规技术形成的金属硅化物层相比，所得金属硅化物层的电阻可以降低。也可以采用较低的硅化反应温度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式