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71. 发明授权

US07209998B2 Scalable bus structure 有权
标题翻译：可扩展总线结构
公开(公告)号：US07209998B2
公开(公告)日：2007-04-24
申请号：US10921053
申请日：2004-08-17
申请人： Richard Gerard Hofmann , Mark Michael Schaffer
发明人： Richard Gerard Hofmann , Mark Michael Schaffer
IPC分类号： G06F13/14 , G06F13/00 , G06F13/28
CPC分类号： G06F13/4265
摘要： A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with first and second channels. The sending component may be configured to broadcast on the first channel read and write address information, read and write control signals, and write data. The sending component may also be configured to signal the receiving component such that the receiving component can distinguish between the read and write address information, the read and write control signals, and the write data broadcast on the first channel. The receiving component may be configured to store the write data broadcast on the first channel based on the write address information and the write control signals, retrieve read data based on the read address information and the read control signals, and broadcast the retrieved read data on the second channel.
摘要翻译：公开了一种具有通过总线连接的发送部件和接收部件的处理系统。总线可以配置有第一和第二通道。发送组件可以被配置为在第一通道上广播读取和写入地址信息，读取和写入控制信号以及写入数据。发送组件还可以被配置为向接收组件发信号，使得接收组件可以区分读取和写入地址信息，读取和写入控制信号以及在第一通道上广播的写入数据。接收部件可以被配置为基于写入地址信息和写入控制信号在第一信道上存储写入数据，基于读取的地址信息和读取的控制信号来检索读取的数据，并将检索到的读取数据广播到第二个渠道。

72. 发明授权

US07167971B2 System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture 失效
标题翻译：用于可重构指令集协处理器架构的自适应运行时重新配置的系统和方法
公开(公告)号：US07167971B2
公开(公告)日：2007-01-23
申请号：US10881146
申请日：2004-06-30
申请人： Sameh W. Asaad , Richard Gerard Hofmann
发明人： Sameh W. Asaad , Richard Gerard Hofmann
IPC分类号： G06F9/30 , G06F9/00
CPC分类号： G06F9/3885 , G06F8/443 , G06F9/30181 , G06F9/3897
摘要： A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed.
摘要翻译：一种在具有通信地连接到至少一个可重配置协处理器的至少一个主处理器的计算机系统中的协处理器指令集的自适应运行时重新配置的方法包括以下步骤：配置协处理器以实现包括一个或多个协处理器指令，向协处理器发出协处理器指令，以及确定在协处理器中是否实现指令。对于未在协处理器指令集中实现的指令，提高失速信号以延迟主处理器，确定协处理器中对于未实现指令是否有足够的空间，以及如果存在足够的空间用于所述指令通过将未实现的指令添加到协处理器指令集来重新配置协处理器的指令集。停止信号被清除，指令被执行。

73. 发明授权

US06973520B2 System and method for providing improved bus utilization via target directed completion 失效
标题翻译：通过目标定向完成提供改进的总线利用率的系统和方法
公开(公告)号：US06973520B2
公开(公告)日：2005-12-06
申请号：US10195172
申请日：2002-07-11
申请人： Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Richard Nicholas Iachetta, Jr. , Barry Joe Wolford
发明人： Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Richard Nicholas Iachetta, Jr. , Barry Joe Wolford
IPC分类号： G06F13/00 , G06F13/14 , G06F13/364
CPC分类号： G06F13/364
摘要： An electronic system is disclosed, including multiple initiators and one or more targets coupled to a bus, and a request mask control unit (RMCU). The initiators are configured to initiate requests (e.g., read requests and write requests) via the bus, and the targets are configured to receive requests from the initiators via the bus. The targets are also configured to produce multiple MaskEnable signals, wherein each of the MaskEnable signals is generated following an initial request received via the bus, and dependent on a corresponding “masking situation” within the target. The RMCU receives the MaskEnable signals and produces multiple RequestMask signals dependent upon the MaskEnable signals. One or more of the initiators are permitted to repeat requests via the bus dependent upon one or more of the RequestMask signals. This mechanism provides additional bus bandwidth for carrying out successful data transfers.
摘要翻译：公开了一种电子系统，包括多个启动器和耦合到总线的一个或多个目标，以及请求掩码控制单元（RMCU）。启动器被配置为经由总线发起请求（例如，读请求和写请求），并且目标被配置为经由总线接收来自发起者的请求。目标还被配置为产生多个MaskEnable信号，其中每个MaskEnable信号是在经由总线接收到的初始请求之后生成的，并且取决于目标内相应的“屏蔽情况”。 RMCU接收MaskEnable信号，并根据MaskEnable信号产生多个RequestMask信号。一个或多个启动器被允许经由总线重复请求，取决于一个或多个请求掩码信号。该机制为进行成功的数据传输提供了额外的总线带宽。

74. 发明授权

US06834378B2 System on a chip bus with automatic pipeline stage insertion for timing closure 有权
标题翻译：系统具有自动流水线插入的片上总线，用于定时关闭
公开(公告)号：US06834378B2
公开(公告)日：2004-12-21
申请号：US10264162
申请日：2002-10-03
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
IPC分类号： G06F945
CPC分类号： G06F17/5045
摘要： A method of designing a system on a chip (SoC) to operate with varying latencies and frequencies. A layout of the chip is designed with specific placement of devices, including a bus controller, initiator, and target devices. The time for a signal to propagate from a source device to a destination device is determined relative to a default propagation time. A pipeline stage is then inserted into a bus path between said source device and destination device for each additional time the signal takes to propagate. Each device (i.e., initiators, targets, and bus controller) is designed with logic to control a protocol that functions with a variety of response latencies. With the additional logic, the devices do not need to be changed when pipeline stages are inserted in the various paths. Registers are utilized as the pipeline stages that are inserted within the paths.
摘要翻译：一种设计芯片上的系统（SoC）以在不同的延迟和频率下工作的方法。芯片的布局设计具有特定的器件布局，包括总线控制器，启动器和目标器件。相对于默认传播时间确定信号从源设备传播到目的地设备的时间。然后，在信号需要传播的每个附加时间，将流水线级插入到所述源设备和目的设备之间的总线路径中。每个设备（即，启动器，目标和总线控制器）被设计为具有控制以各种响应延迟起作用的协议的逻辑。使用附加逻辑，当管道级插入各种路径时，不需要更改设备。寄存器被用作插入到路径内的流水线级。

75. 发明授权

US06826656B2 Reducing power in a snooping cache based multiprocessor environment 失效
标题翻译：在基于多播处理器环境的基于高速缓存的基础上降低功耗
公开(公告)号：US06826656B2
公开(公告)日：2004-11-30
申请号：US10059537
申请日：2002-01-28
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
IPC分类号： G06F1208
CPC分类号： G06F1/3203 , G06F1/3275 , G06F12/0831 , Y02D10/14
摘要： A method and system for reducing power in a snooping cache based environment. A memory may be coupled to a plurality of processing units via a bus. Each processing unit may comprise a cache controller coupled to a cache associated with the processing unit. The cache controller may comprise a segment register comprising N bits where each bit in the segment register may be associated with a segment of memory divided into N segments. The cache controller may be configured to snoop a requested address on the bus. Upon determining which bit in the segment register is associated with the snooped requested address, the segment register may determine if the bit associated with the snooped requested address is set. If the bit is not set, then a cache search may not be performed thereby mitigating the power consumption associated with a snooped request cache search.
摘要翻译：一种用于在基于窥探缓存的环境中降低功耗的方法和系统。存储器可以经由总线耦合到多个处理单元。每个处理单元可以包括耦合到与处理单元相关联的高速缓存器的高速缓存控制器。高速缓存控制器可以包括包括N个比特的分段寄存器，其中分段寄存器中的每个比特可以与划分成N个分段的一段存储器相关联。高速缓存控制器可以被配置为窥探总线上的所请求的地址。一旦确定段寄存器中的哪个位与被窥探的请求地址相关联，则段寄存器可以确定是否设置与被窥探的请求地址相关联的位。如果该位未设置，则可能不执行高速缓存搜索，从而减轻与窥探请求高速缓存搜索相关联的功耗。

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