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71. 发明申请

US20080002851A1 Data hiding with wavelet transform histogram shifting 有权
标题翻译：数据隐藏与小波变换直方图转换
公开(公告)号：US20080002851A1
公开(公告)日：2008-01-03
申请号：US11418821
申请日：2006-05-08
申请人： Yun Shi , Guorong Xuan
发明人： Yun Shi , Guorong Xuan
IPC分类号： G06T1/00 , G06K9/00
CPC分类号： G06T1/0028 , G06T2201/0052 , G06T2201/0083 , G06T2201/0203
摘要： Embodiments related to data hiding using wavelet transforms and histogram shifting are disclosed.
摘要翻译：公开了与使用小波变换和直方图转换的数据隐藏有关的实施例。

72. 发明授权

US08890246B2 Shielding for high-voltage semiconductor-on-insulator devices 有权
标题翻译：高压绝缘体上半导体器件屏蔽
公开(公告)号：US08890246B2
公开(公告)日：2014-11-18
申请号：US13596410
申请日：2012-08-28
申请人： Alan B. Botula , Beth Ann Rainey , Yun Shi
发明人： Alan B. Botula , Beth Ann Rainey , Yun Shi
IPC分类号： H01L27/12 , H01L21/74 , H01L29/20
CPC分类号： H01L27/1203 , H01L21/743 , H01L29/2003
摘要： Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band.
摘要翻译：提供了在衬底中和在绝缘体上绝缘体（SOI）器件上的高压绝缘体（SOI）器件下面具有掺杂带的集成电路。在一个实施例中，本发明提供一种集成电路，包括：绝缘体上半导体（SOI）晶片，其包括：基板; 衬底上的掩埋氧化物（BOX）层; 以及位于BOX层顶部的半导体层; 在半导体层内串联连接的多个高压（HV）器件; 在所述衬底内并在所述多个HV器件中的第一个之下的掺杂带; 以及从半导体层和BOX层延伸到掺杂带的接触。

73. 发明授权

US08866226B2 SOI radio frequency switch with enhanced electrical isolation 有权
标题翻译： SOI射频开关具有增强的电气隔离
公开(公告)号：US08866226B2
公开(公告)日：2014-10-21
申请号：US13345871
申请日：2012-01-09
申请人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
IPC分类号： H01L27/12 , H01L21/84 , H01L21/762
CPC分类号： H01L21/84 , H01L21/76264 , H01L27/1203
摘要： At least one conductive via structure is formed from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to a bottom semiconductor layer. The shallow trench isolation structure laterally abuts at least two field effect transistors that function as a radio frequency (RF) switch. The at least one conductive via structure and the at interconnect-level metal line may provide a low resistance electrical path from the induced charge layer in a bottom semiconductor layer to electrical ground, discharging the electrical charge in the induced charge layer. The discharge of the charge in the induced charge layer thus reduces capacitive coupling between the semiconductor devices and the bottom semiconductor layer, and thus secondary coupling between components electrically disconnected by the RF switch is reduced.
摘要翻译：至少一个导电通孔结构由通过中间线（MOL）电介质层的互连级金属线，顶部半导体层中的浅沟槽隔离结构和到半导体层的掩埋绝缘体层形成。浅沟槽隔离结构横向邻接用作射频（RF）开关的至少两个场效应晶体管。所述至少一个导电通孔结构和所述互连级金属线可以提供从底部半导体层中的感应电荷层到电接地的低电阻电路径，从而对感应电荷层中的电荷进行放电。感应电荷层中的电荷的放电因此减小了半导体器件与底部半导体层之间的电容耦合，因此降低了由RF开关电断开的部件之间的二次耦合。

74. 发明授权

US08492843B2 Lateral hyperabrupt junction varactor diode in an SOI substrate 有权
标题翻译： SOI衬底中的横向超破坏结变容二极管
公开(公告)号：US08492843B2
公开(公告)日：2013-07-23
申请号：US13449419
申请日：2012-04-18
申请人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
发明人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
IPC分类号： H01L29/786
CPC分类号： H01L29/93 , H01L29/7391
摘要： A varactor diode includes a portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate and a gate electrode located thereupon. A first electrode having a doping of a first conductivity type laterally abuts a doped semiconductor region having the first conductivity type, which laterally abuts a second electrode having a doping of a second conductivity type, which is the opposite of the first conductivity type. A hyperabrupt junction is formed between the second doped semiconductor region and the second electrode. The gate electrode controls the depletion of the first and second doped semiconductor regions, thereby varying the capacitance of the varactor diode. A design structure for the varactor diode is also provided.
摘要翻译：变容二极管包括绝缘体上半导体（SOI）衬底的顶部半导体层的一部分和位于其上的栅电极。具有第一导电类型的掺杂的第一电极横向邻接具有第一导电类型的掺杂半导体区域，其横向邻接具有与第一导电类型相反的第二导电类型的掺杂的第二电极。在第二掺杂半导体区域和第二电极之间形成超破坏结。栅电极控制第一和第二掺杂半导体区的耗尽，从而改变变容二极管的电容。还提供了变容二极管的设计结构。

75. 发明授权

US08350338B2 Semiconductor device including high field regions and related method 有权
标题翻译：半导体器件包括高场区域及相关方法
公开(公告)号：US08350338B2
公开(公告)日：2013-01-08
申请号：US13023042
申请日：2011-02-08
申请人： William F. Clark, Jr. , Yun Shi
发明人： William F. Clark, Jr. , Yun Shi
IPC分类号： H01L23/013
CPC分类号： H01L29/78654 , H01L29/42384 , H01L29/78618 , H01L29/78696
摘要： A semiconductor device is disclosed. In an embodiment, a semiconductor device includes a N-well within a P-well in a silicon layer, the silicon layer positioned atop a buried oxide layer of a silicon-on-insulator (SOI) substrate; a first source region and a second source region within a portion of the P-well; a first drain region and a second drain region within a portion of the P-well and within a portion of the N-well; and a gate positioned atop the N-well, wherein a lateral high field region is generated between the N-well and the P-well and a vertical high field region is generated between the gate and the N-well. A related method is disclosed.
摘要翻译：公开了一种半导体器件。在一个实施例中，半导体器件包括在硅层中的P阱内的N阱，所述硅层位于绝缘体上硅（SOI）衬底的掩埋氧化物层的顶部; 在P阱的一部分内的第一源极区域和第二源极区域; 在P阱的一部分内并在N阱的一部分内的第一漏极区域和第二漏极区域; 以及位于N阱顶部的栅极，其中在N阱和P阱之间产生横向高场区域，并且在栅极和N阱之间产生垂直高场区域。公开了相关方法。

76. 发明申请

US20120168878A1 FIELD EFFECT TRANSISTOR HAVING OHMIC BODY CONTACT(S), AN INTEGRATED CIRCUIT STRUCTURE INCORPORATING STACKED FIELD EFFECT TRANSISTORS WITH SUCH OHMIC BODY CONTACTS AND ASSOCIATED METHODS 有权
标题翻译：具有OHMIC身体接触的场效应晶体管，集成电路结构与这样的OHMIC体接触和相关方法并入堆叠场效应晶体管
公开(公告)号：US20120168878A1
公开(公告)日：2012-07-05
申请号：US12983925
申请日：2011-01-04
申请人： Michel J. Abou-Khalil , William F. Clark, JR. , Yun Shi
发明人： Michel J. Abou-Khalil , William F. Clark, JR. , Yun Shi
IPC分类号： H01L27/088 , H01L21/336 , H01L21/8234 , H01L29/78
CPC分类号： H01L21/823481 , H01L21/743 , H01L21/823475 , H01L29/7833
摘要： Disclosed is a field effect transistor (FET), in which ohmic body contact(s) are placed relatively close to the active region. The FET includes a semiconductor layer, where the active region and body contact region(s) are defined by a trench isolation structure and where a body region is below and abuts the active region, the trench isolation structure and the body contact region(s). A gate traverses the active region. Dummy gate(s) are on the body contact region(s). A contact extends through each dummy gate to the body contact region below. Dielectric material isolates the contact(s) from the dummy gate(s). During processing, the dummy gate(s) act as blocks to ensure that the body contact regions are not implanted with source/drain dopants or source/drain extension dopants and, thereby to ensure that the body contacts, as formed, are ohmic. Also disclosed are an integrated circuit structure with stacked FETs, having such ohmic body contacts, and associated methods.
摘要翻译：公开了一种场效应晶体管（FET），其中欧姆体接触被放置得相对靠近有源区。 FET包括半导体层，其中有源区和体接触区由沟槽隔离结构限定，并且其中体区在下方并与活性区相邻，沟槽隔离结构和身体接触区。门穿过活动区域。虚拟门位于身体接触区域上。触点延伸穿过每个虚拟门到下面的身体接触区域。电介质材料将接触与虚拟栅极隔离开。在处理期间，伪栅极用作块，以确保体接触区域不被源/漏掺杂剂或源极/漏极延伸掺杂剂注入，从而确保所形成的本体接触是欧姆的。还公开了具有堆叠FET的集成电路结构，具有这种欧姆体接触以及相关联的方法。

77. 发明申请

US20110260281A1 SHIELDING FOR HIGH-VOLTAGE SEMICONDUCTOR-ON-INSULATOR DEVICES 有权
标题翻译：用于高压半导体绝缘体器件的屏蔽
公开(公告)号：US20110260281A1
公开(公告)日：2011-10-27
申请号：US12764244
申请日：2010-04-21
申请人： Alan B. Botula , Beth Ann Rainey , Yun Shi
发明人： Alan B. Botula , Beth Ann Rainey , Yun Shi
IPC分类号： H01L27/12 , H01L23/52
CPC分类号： H01L27/1203 , H01L21/743 , H01L29/2003
摘要： Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band.
摘要翻译：提供了在衬底中和在绝缘体上绝缘体（SOI）器件上的高压绝缘体（SOI）器件下面具有掺杂带的集成电路。在一个实施例中，本发明提供一种集成电路，包括：绝缘体上半导体（SOI）晶片，其包括：基板; 衬底上的掩埋氧化物（BOX）层; 以及位于BOX层顶部的半导体层; 在半导体层内串联连接的多个高压（HV）器件; 在所述衬底内并在所述多个HV器件中的第一个之下的掺杂带; 以及从半导体层和BOX层延伸到掺杂带的接触。

78. 发明申请

US20110221510A1 SOI RADIO FREQUENCY SWITCH WITH ENHANCED SIGNAL FIDELITY AND ELECTRICAL ISOLATION 有权
标题翻译：具有增强信号强度和电隔离的SOI无线电频率开关
公开(公告)号：US20110221510A1
公开(公告)日：2011-09-15
申请号：US13116396
申请日：2011-05-26
申请人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
IPC分类号： H03K3/01 , H01L21/336 , G06F17/50
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/76224 , H01L21/76251 , H01L21/84
摘要： A doped contact region having an opposite conductivity type as a bottom semiconductor layer is provided underneath a buried insulator layer in a bottom semiconductor layer. At least one conductive via structure extends from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer and to the doped contact region. The doped contact region is biased at a voltage that is at or close to a peak voltage in the RF switch that removes minority charge carriers within the induced charge layer. The minority charge carriers are drained through the doped contact region and the at least one conductive via structure. Rapid discharge of mobile electrical charges in the induce charge layer reduces harmonic generation and signal distortion in the RF switch. A design structure for the semiconductor structure is also provided.
摘要翻译：具有与底部半导体层相反的导电类型的掺杂接触区域设置在底部半导体层中的掩埋绝缘体层的下方。至少一个导电通孔结构从互连级金属线延伸穿过中间线（MOL）电介质层，顶部半导体层中的浅沟槽隔离结构，以及掩埋绝缘体层和掺杂接触区域。掺杂接触区域被偏置在处于或接近RF开关中的峰值电压的电压，该电压去除感应电荷层内的少数电荷载流子。少数电荷载体通过掺杂接触区域和至少一个导电通孔结构排出。诱导电荷层中的移动电荷的快速放电减少了RF开关中的谐波产生和信号失真。还提供了用于半导体结构的设计结构。

79. 发明授权

US07989302B2 Methods of forming a hyper-abrupt P-N junction and design structures for an integrated circuit 有权
标题翻译：形成超突变P-N结的方法和集成电路的设计结构
公开(公告)号：US07989302B2
公开(公告)日：2011-08-02
申请号：US12795108
申请日：2010-06-07
申请人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
发明人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
IPC分类号： H01L21/20
CPC分类号： H01L29/93
摘要： Methods of forming hyper-abrupt p-n junctions and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt p-n junction.
摘要翻译：形成超突变p-n结的方法和包含具有超突变p-n结的器件结构的集成电路的设计结构。通过将器件层的一部分注入具有一种导电类型，然后将该掺杂区域的一部分注入具有相反的导电型，在SOI衬底中限定超突变p-n结。反渗透定义了超突变p-n结。在离子注入期间，在器件层的顶表面上承载的栅结构作为硬掩模进行操作，以有助于限定超突变p-n结的横向边界。

80. 发明申请

US20100156526A1 SOI RADIO FREQUENCY SWITCH WITH ENHANCED SIGNAL FIDELITY AND ELECTRICAL ISOLATION 有权
标题翻译：具有增强信号强度和电隔离的SOI无线电频率开关
公开(公告)号：US20100156526A1
公开(公告)日：2010-06-24
申请号：US12342527
申请日：2008-12-23
申请人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
IPC分类号： H03H11/00 , H01L21/761 , H01L21/762 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/76224 , H01L21/76251 , H01L21/84
摘要： A doped contact region having an opposite conductivity type as a bottom semiconductor layer is provided underneath a buried insulator layer in a bottom semiconductor layer. At least one conductive via structure extends from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer and to the doped contact region. The doped contact region is biased at a voltage that is at or close to a peak voltage in the RF switch that removes minority charge carriers within the induced charge layer. The minority charge carriers are drained through the doped contact region and the at least one conductive via structure. Rapid discharge of mobile electrical charges in the induce charge layer reduces harmonic generation and signal distortion in the RF switch. A design structure for the semiconductor structure is also provided.
摘要翻译：具有与底部半导体层相反的导电类型的掺杂接触区域设置在底部半导体层中的掩埋绝缘体层的下方。至少一个导电通孔结构从互连级金属线延伸穿过中间线（MOL）电介质层，顶部半导体层中的浅沟槽隔离结构，以及掩埋绝缘体层和掺杂接触区域。掺杂接触区域被偏置在处于或接近RF开关中的峰值电压处的电压，其移除感应电荷层内的少数电荷载流子。少数电荷载体通过掺杂接触区域和至少一个导电通孔结构排出。诱导电荷层中的移动电荷的快速放电减少了RF开关中的谐波产生和信号失真。还提供了用于半导体结构的设计结构。

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