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71. 发明授权

US07964489B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07964489B2
公开(公告)日：2011-06-21
申请号：US12491984
申请日：2009-06-25
申请人： Masato Koyama , Yoshinori Tsuchiya , Yuuichi Kamimuta , Reika Ichihara , Katsuyuki Sekine
发明人： Masato Koyama , Yoshinori Tsuchiya , Yuuichi Kamimuta , Reika Ichihara , Katsuyuki Sekine
IPC分类号： H01L21/3205
CPC分类号： H01L27/092 , H01L21/28097 , H01L21/823842 , H01L21/823857 , H01L29/4975 , H01L29/513 , H01L29/517 , H01L29/7833
摘要： A semiconductor device includes: a p-channel MIS transistor including: a first insulating layer formed on a semiconductor region between a source region and a drain region, and containing at least silicon and oxygen; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, and a first gate electrode formed on the second insulating layer. The first and second insulating layers have a first and second region respectively. The first and second regions are in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer. Each of the first and second regions include aluminum atoms with a concentration of 1×1020 cm−3 or more to 1×1022 cm−3 or less.
摘要翻译：半导体器件包括：p沟道MIS晶体管，包括：第一绝缘层，形成在源极区域和漏极区域之间的半导体区域上，并且至少包含硅和氧; 形成在所述第一绝缘层上并且包含铪，硅，氧和氮的第二绝缘层，以及形成在所述第二绝缘层上的第一栅电极。第一和第二绝缘层分别具有第一和第二区域。第一和第二区域在从第一绝缘层和第二绝缘层之间的界面的膜厚度方向上为0.3nm的范围内。第一和第二区域中的每一个包括浓度为1×1020cm-3或更高至1×1022cm-3或更低的铝原子。

72. 发明授权

US07948790B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07948790B2
公开(公告)日：2011-05-24
申请号：US12558058
申请日：2009-09-11
申请人： Takayuki Tsukamoto , Reika Ichihara
发明人： Takayuki Tsukamoto , Reika Ichihara
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C13/0064 , G11C13/0069 , G11C16/3413 , G11C16/3463 , G11C2013/009 , G11C2211/5642 , G11C2213/31 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A memory cell arranged between first and second wirings includes a variable-resistor element. A controller controls a voltage applied between the first and second wirings. The controller performs a first operation that applies a first voltage between the first and second wirings to switch the variable-resistor element from a first state with a resistance value not less than a first resistance value, to a second state with a resistance value not more than a second resistance value smaller than the first resistance value. The second operation applies a second voltage smaller than the first voltage between the first and second wirings to switch the variable-resistor element from the second state to the first state. In the first operation, a verify voltage is applied between the first and second wirings. Based on the obtained signal, a third voltage smaller than the first voltage is applied between the first and second wirings.
摘要翻译：布置在第一和第二布线之间的存储单元包括可变电阻器元件。控制器控制施加在第一和第二布线之间的电压。控制器执行第一操作，其在第一和第二布线之间施加第一电压，以将具有不小于第一电阻值的电阻值的第一状态的可变电阻元件切换到具有不大于电阻值的第二状态比第一电阻值小的第二电阻值。第二操作施加小于第一和第二布线之间的第一电压的第二电压，以将可变电阻元件从第二状态切换到第一状态。在第一操作中，在第一和第二布线之间施加验证电压。基于获得的信号，在第一和第二布线之间施加小于第一电压的第三电压。

73. 发明授权

US07807990B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07807990B2
公开(公告)日：2010-10-05
申请号：US11753186
申请日：2007-05-24
申请人： Masato Koyama , Yoshinori Tsuchiya , Yuuichi Kamimuta , Reika Ichihara , Katsuyuki Sekine
发明人： Masato Koyama , Yoshinori Tsuchiya , Yuuichi Kamimuta , Reika Ichihara , Katsuyuki Sekine
IPC分类号： H01L31/00
CPC分类号： H01L27/092 , H01L21/28097 , H01L21/823842 , H01L21/823857 , H01L29/4975 , H01L29/513 , H01L29/517 , H01L29/7833
摘要： A semiconductor device includes: a p-channel MIS transistor including: a first insulating layer formed on a semiconductor region between a source region and a drain region, and containing at least silicon and oxygen; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, and a first gate electrode formed on the second insulating layer. The first and second insulating layers have a first and second region respectively. The first and second regions are in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer. Each of the first and second regions include aluminum atoms with a concentration of 1×1020 cm−3 or more to 1×1022 cm−3 or less.
摘要翻译：半导体器件包括：p沟道MIS晶体管，包括：第一绝缘层，形成在源极区域和漏极区域之间的半导体区域上，并且至少包含硅和氧; 形成在所述第一绝缘层上并且包含铪，硅，氧和氮的第二绝缘层，以及形成在所述第二绝缘层上的第一栅电极。第一和第二绝缘层分别具有第一和第二区域。第一和第二区域在从第一绝缘层和第二绝缘层之间的界面的膜厚度方向上为0.3nm的范围内。第一和第二区域中的每一个包括浓度为1×1020cm-3或更高至1×1022cm-3或更低的铝原子。

74. 发明授权

US07485936B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07485936B2
公开(公告)日：2009-02-03
申请号：US11355132
申请日：2006-02-16
申请人： Masato Koyama , Yoshinori Tsuchiya , Reika Ichihara
发明人： Masato Koyama , Yoshinori Tsuchiya , Reika Ichihara
IPC分类号： H01L29/76
CPC分类号： H01L21/823835 , H01L21/823842
摘要： It is possible to provide a semiconductor device including a CMOS device having a gate electrode, in which the variation in threshold voltage is little. There are a p-channel MIS transistor and a n-channel MIS transistor which are provided in a semiconductor substrate, and in a region of a gate electrode of the p-channel MIS transistor at least 1 nm or less apart from the interface with a gate insulating film, the oxygen concentration is 1020 cm−3 or more and 1022 cm−3 or less.
摘要翻译：可以提供一种包括具有门电极的CMOS器件的半导体器件，其中阈值电压的变化很小。存在设置在半导体衬底中的p沟道MIS晶体管和n沟道MIS晶体管，并且在p沟道MIS晶体管的栅电极的区域中，除了与栅极绝缘膜，氧浓度为1020cm -3以上且1022cm -3以下。

75. 发明申请

US20080258230A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
公开(公告)号：US20080258230A1
公开(公告)日：2008-10-23
申请号：US12133583
申请日：2008-06-05
申请人： Masato KOYAMA , Akira Nishiyama , Yoshinori Tsuchiya , Reika Ichihara
发明人： Masato KOYAMA , Akira Nishiyama , Yoshinori Tsuchiya , Reika Ichihara
IPC分类号： H01L27/092
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/28088 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate insulating layer formed on the P-type semiconductor layer, and a second gate electrode formed on the second gate insulating layer.

76. 发明申请

US20080254581A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080254581A1
公开(公告)日：2008-10-16
申请号：US12133605
申请日：2008-06-05
申请人： Masato KOYAMA , Akira Nishiyama , Yoshinori Tsuchiya , Reika Ichihara
发明人： Masato KOYAMA , Akira Nishiyama , Yoshinori Tsuchiya , Reika Ichihara
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/28088 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate insulating layer formed on the P-type semiconductor layer, and a second gate electrode formed on the second gate insulating layer.
摘要翻译：公开了一种包括P沟道MIS晶体管的半导体器件，其包括N型半导体层，形成在N型半导体层上并含有金属的碳化合物的第一栅极绝缘层和N沟道MIS 晶体管，其包括P型半导体层，形成在P型半导体层上的第二栅极绝缘层和形成在第二栅极绝缘层上的第二栅电极。

77. 发明授权

US07410855B2 Semiconductor device 有权
公开(公告)号：US07410855B2
公开(公告)日：2008-08-12
申请号：US11841841
申请日：2007-08-20
申请人： Reika Ichihara , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
发明人： Reika Ichihara , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823462
摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.

78. 发明授权

US07391085B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07391085B2
公开(公告)日：2008-06-24
申请号：US11299773
申请日：2005-12-13
申请人： Reika Ichihara , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
发明人： Reika Ichihara , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
IPC分类号： H01L27/092
CPC分类号： H01L21/823857 , H01L21/823462
摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
摘要翻译：半导体器件包括半导体衬底，形成在衬底上的nMISFET，nMISFET包括形成在衬底上的第一电介质和形成在第一电介质上的第一金属栅极，并由选自Ti，Zr，Hf， Ta，Sc，Y，镧系元素和锕系和选自所述一种金属元素的硼化物，硅化物和锗化合物的一种，以及形成在所述衬底上的pMISFET，所述pMISFET包括形成在所述衬底上的第二电介质和第二金属栅电极形成在第二电介质上并由与第一金属栅电极相同的材料制成，第二电介质面向第二金属栅电极的至少一部分由绝缘材料制成，绝缘材料与至少一部分的第一电介质面向第一金属栅电极。

79. 发明申请

US20080128822A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080128822A1
公开(公告)日：2008-06-05
申请号：US11753186
申请日：2007-05-24
申请人： Masato Koyama , Yoshinori Tsuchiya , Yuuichi Kamimuta , Reika Ichihara , Katsuyuki Sekine
发明人： Masato Koyama , Yoshinori Tsuchiya , Yuuichi Kamimuta , Reika Ichihara , Katsuyuki Sekine
IPC分类号： H01L27/092
CPC分类号： H01L27/092 , H01L21/28097 , H01L21/823842 , H01L21/823857 , H01L29/4975 , H01L29/513 , H01L29/517 , H01L29/7833
摘要： A semiconductor device includes: a p-channel MIS transistor including: a first insulating layer formed on a semiconductor region between a source region and a drain region, and containing at least silicon and oxygen; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, and a first gate electrode formed on the second insulating layer. The first and second insulating layers have a first and second region respectively. The first and second regions are in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer. Each of the first and second regions include aluminum atoms with a concentration of 1×1020 cm−3 or more to 1×1022 cm−3 or less.
摘要翻译：半导体器件包括：p沟道MIS晶体管，包括：第一绝缘层，形成在源极区域和漏极区域之间的半导体区域上，并且至少包含硅和氧; 形成在所述第一绝缘层上并且包含铪，硅，氧和氮的第二绝缘层，以及形成在所述第二绝缘层上的第一栅电极。第一和第二绝缘层分别具有第一和第二区域。第一和第二区域在从第一绝缘层和第二绝缘层之间的界面的膜厚度方向上为0.3nm的范围内。第一和第二区域中的每一个包括浓度为1×10 20 cm -3或更多至1×10 22 cm -3的铝原子， 3 以下。

80. 发明申请

US20070145493A1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070145493A1
公开(公告)日：2007-06-28
申请号：US11635040
申请日：2006-12-07
申请人： Masato Koyama , Reika Ichihara , Yoshinori Tsuchiya , Yuuichi Kamimuta , Akira Nishiyama
发明人： Masato Koyama , Reika Ichihara , Yoshinori Tsuchiya , Yuuichi Kamimuta , Akira Nishiyama
IPC分类号： H01L29/76
CPC分类号： H01L21/823842
摘要： A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.
摘要翻译：半导体器件包括衬底，形成在衬底上的n型阱上的p沟道MIS晶体管，具有形成在其上并由Ta-C合金形成的第一栅极电介质和第一栅电极，其中晶体取向比例膜厚方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]的TaC（111）面为80％以上，n型沟道MIS晶体管形成在p- 在基板上良好地形成具有形成在其上的第二栅极电介质和第二栅电极，并且由TaC（111）在膜厚度方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]为60％以下。

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