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71. 发明专利

HK1035080A1 AMPLIFIER WITH ADJUSTABLE BIAS CURRENT 未知
公开(公告)号：HK1035080A1
公开(公告)日：2001-11-09
申请号：HK01105741
申请日：2001-08-15
申请人： QUALCOMM INC
发明人： CICCARELLI STEVEN C , KAUFMAN RALPH E , PETERZELL PAUL E
IPC分类号： H03F1/02 , H03F1/26 , H03F1/34 , H03F1/32 , H03G1/00 , H03G3/18 , H03G3/20 , H04B1/10 , H04B1/16 , H03F , H03G
摘要： An amplifier having an adjustable current source which can be controlled to provide the requisite level of performance at reduced current consumption. The amplifier is first designed using one of many designs available and known in the art. A current source is then designed to provide adjustable bias current for the amplifier. The current source can be designed with MOSFETs which require no additional bias current and can accept a standard digital control signal. The current source can also be designed with active devices which are selected based on the logic of the control signals for ease of interface. The bias current determines the linearity and noise performance of the amplifier. The bias current is adjusted to provide the requisite level of performance while reducing power consumption. The current source can be designed to operate in discrete steps or to have substantially continuous current steps.

72. 发明专利

BR9813481A 未知
公开(公告)号：BR9813481A
公开(公告)日：2001-10-23
申请号：BR9813481
申请日：1998-12-08
申请人： QUALCOMM INC
发明人： CICCARELLI STEVEN C , YOUNIS SAED G , KAUFMAN RALPH E
IPC分类号： H03F1/02 , H03F1/34 , H03G1/00 , H03G3/18 , H03G3/20 , H04B1/10 , H04B1/16
摘要： A programmable linear receiver which provides the requisite level of system performance at reduced power consumption. The receiver minimizes power consumption based on measurement of the non-linearity in the output signal from the receiver. The amount of non-linearity can be measured by the RSSI slope or energy-per-chip-to-noise-ratio (Ec/Io) measurement. The RSSI slope is the ratio of the change in the output signal plus intermodulation to the change in the input signal. The input signal level is periodically increased by a predetermined level and the output signal from the receiver is measured. The output signal comprises the desired signal and intermodulation products from non-linearity within the receiver. When the receiver is operating linearly, the output signal level increases dB per dB with the input signal level. However, as the receiver transitions into non-linear region, intermodulation products due to non-linearity increase faster than the desired signal. By detecting the RSSI slope, the amount of degradation due to non-linearity can be determined. This information is then used to adjust the IIP3 operating point of the amplifiers and mixer to provide the requisite level of performance while minimizing power consumption.

73. 发明专利

HK1033718A1 Method and apparatus for downconverting signals transmitted using a plurality of modulation formats to a common intermediate frequency range 未知
公开(公告)号：HK1033718A1
公开(公告)日：2001-09-14
申请号：HK01103050
申请日：2001-04-27
申请人： QUALCOMM INC
发明人： CICCARELLI STEVEN C , YOUNIS SAED G
IPC分类号： G01S19/07 , G01S19/11 , G01S19/12 , G01S19/31 , H04B1/26 , H04B1/38 , H04B1/40 , H04B1/62 , H04L27/22 , H04B
摘要： A receiver that downconverts input signals modulated using first, second, third and fourth modulation formats to a common intermediate frequency range. The first and second modulation formats are transmitted to the receiver in a first frequency range, the third modulation format is transmitted to the receiver in a second frequency range, and the fourth modulation format is transmitted to the receiver in a third frequency range. The input signals are provided to first, second and third band selection filters that respectively select first, second and third frequency ranges. A first downconverter is coupled to an output of the first band selection filter, and downconverts signals from the first frequency range to the common intermediate frequency range. A second downconverter is selectively coupled by a switch to either an output of the second band selection filter or an output of the third band selection filter, and downconverts signals from either the second frequency range or the third frequency range to the common intermediate frequency range. The second downconverter has an input coupled to a frequency doubling circuit. Switching circuitry selectively couples one of either a first oscillating signal from a voltage controlled oscillator (VCO) having a VCO frequency range or a second oscillating signal at a second frequency that is outside the VCO frequency range to an input of the first downconverter and an input of the frequency doubling circuit.

74. 发明专利

NO20002931D0 未知
公开(公告)号：NO20002931D0
公开(公告)日：2000-06-08
申请号：NO20002931
申请日：2000-06-08
申请人： QUALCOMM INC
发明人： CICCARELLI STEVEN C , YOUNIS SAED G , KAUFMAN RALPH E
IPC分类号： H03F1/02 , H03F1/34 , H03G1/00 , H03G3/18 , H03G3/20 , H04B1/10 , H04B1/16 , H04B
摘要： A programmable linear receiver which provides the requisite level of system performance at reduced power consumption. The receiver minimizes power consumption based on measurement of the non-linearity in the output signal from the receiver. The amount of non-linearity can be measured by the RSSI slope or energy-per-chip-to-noise-ratio (Ec/Io) measurement. The RSSI slope is the ratio of the change in the output signal plus intermodulation to the change in the input signal. The input signal level is periodically increased by a predetermined level and the output signal from the receiver is measured. The output signal comprises the desired signal and intermodulation products from non-linearity within the receiver. When the receiver is operating linearly, the output signal level increases dB per dB with the input signal level. However, as the receiver transitions into non-linear region, intermodulation products due to non-linearity increase faster than the desired signal. By detecting the RSSI slope, the amount of degradation due to non-linearity can be determined. This information is then used to adjust the IIP3 operating point of the amplifiers and mixer to provide the requisite level of performance while minimizing power consumption.

75. 发明专利

AU1717899A Receiver with sigma-delta analog-to-digital converter 未知
公开(公告)号：AU1717899A
公开(公告)日：1999-06-28
申请号：AU1717899
申请日：1998-12-08
申请人： QUALCOMM INC
发明人： BAZARJANI SEYFOLLAH S , CICCARELLI STEVEN C , YOUNIS SAED G , BUTTERFIELD DANIEL K
IPC分类号： H03M1/66 , H03D3/00 , H03D7/16 , H03M3/02 , H04B1/26 , H04B1/16
摘要： A receiver comprising a sigma-delta analog-to-digital converter ( SIGMA DELTA ADC) can be utilized in one of four configurations, as a subsampling bandpass receiver, a subsampling baseband receiver, a Nyquist sampling bandpass receiver, or a Nyquist sampling baseband receiver. For subsampling SIGMA DELTA receivers, the sampling frequency is less than twice the center frequency of the input signal into the SIGMA DELTA ADC. For Nyquist sampling SIGMA DELTA receivers, the sampling frequency is at least twice the highest frequency of the input signal into the SIGMA DELTA ADC. For baseband SIGMA DELTA receivers, the center frequency of the output signal from the SIGMA DELTA ADC is approximately zero or DC. For bandpass SIGMA DELTA receivers, the center frequency of the output signal from the SIGMA DELTA ADC is greater than zero. The sampling frequency can be selected based on the bandwidth of the input signal to simplify the design of the digital circuits used to process the output samples from the SIGMA DELTA ADC. Furthermore, the center frequency of the input signal can be selected based on the sampling frequency and the bandwidth of the input signal. The SIGMA DELTA ADC within the receiver provides many benefits.

76. 发明专利

AU1632999A Programmable linear receiver 未知
公开(公告)号：AU1632999A
公开(公告)日：1999-06-28
申请号：AU1632999
申请日：1998-12-08
申请人： QUALCOMM INC
发明人： CICCARELLI STEVEN C , YOUNIS SAED G , KAUFMAN RALPH E
IPC分类号： H03F1/02 , H03F1/34 , H03G1/00 , H03G3/18 , H03G3/20 , H04B1/10 , H04B1/16
摘要： A programmable linear receiver which provides the requisite level of system performance at reduced power consumption. The receiver minimizes power consumption based on measurement of the non-linearity in the output signal from the receiver. The amount of non-linearity can be measured by the RSSI slope or energy-per-chip-to-noise-ratio (Ec/Io) measurement. The RSSI slope is the ratio of the change in the output signal plus intermodulation to the change in the input signal. The input signal level is periodically increased by a predetermined level and the output signal from the receiver is measured. The output signal comprises the desired signal and intermodulation products from non-linearity within the receiver. When the receiver is operating linearly, the output signal level increases dB per dB with the input signal level. However, as the receiver transitions into non-linear region, intermodulation products due to non-linearity increase faster than the desired signal. By detecting the RSSI slope, the amount of degradation due to non-linearity can be determined. This information is then used to adjust the IIP3 operating point of the amplifiers and mixer to provide the requisite level of performance while minimizing power consumption.

77. 发明申请

WO2004042937A3 DYNAMICALLY PROGRAMMABLE RECEIVER 审中-公开
标题翻译：动态可编程接收器
公开(公告)号：WO2004042937A3
公开(公告)日：2004-07-29
申请号：PCT/US0334749
申请日：2003-10-30
申请人： QUALCOMM INC
发明人： CICCARELLI STEVEN C
IPC分类号： H04B1/10 , H03G3/20 , H04B1/707
CPC分类号： H04K3/228 , H04B1/109 , H04B1/71 , H04K3/224
摘要： Disclosed is a novel and improved dynamically programmable linear receiver which provides the required level of system performance with reduced power consumption. In one embodiment, disclosed is a programmable receiver coupled to a jammer detector for detecting the presence of jamming in an RF signal, the jammer detector coupled to a state machine, and the state machine having means for controlling the receiver based on the results of the jammer detector detecting the presence of jamming in the RF signal. The disclosed receiver is capable of detecting the presence of jammers, with a means to adjust the bias current downward if no jammers are present, which improves the receiver's standby time and prolongs battery life.
摘要翻译：公开了一种新型和改进的动态可编程线性接收机，其提供所需级别的系统性能并降低功耗。在一个实施例中，公开了一种耦合到干扰检测器的可编程接收机，用于检测RF信号中干扰的存在，干扰检测器耦合到状态机，并且状态机具有用于基于干扰检测器检测RF信号中是否存在干扰。所公开的接收机能够检测到干扰的存在，并且具有如果不存在干扰信号来向下调整偏置电流的装置，这改进了接收机的待机时间并延长了电池寿命。

78. 发明申请

WO0243255A3 QUADRATURE GENERATOR WITH IMAGE REJECT MIXER 审中-公开
标题翻译：具有图像抑制混合器的平方发生器
公开(公告)号：WO0243255A3
公开(公告)日：2004-02-12
申请号：PCT/US0146189
申请日：2001-10-31
申请人： QUALCOMM INC
发明人： PERSICO CHARLES J , JAFFEE JAMES , CICCARELLI STEVEN C
IPC分类号： H04B1/26 , H03D7/16 , H03C3/40
CPC分类号： H03D7/166 , H03D7/165
摘要： In an exemplary application, an apparatus according to a disclosed embodiment receives a radio frequency signal and outputs an intermediate frequency signal. Rejection of image components in the intermediate frequency signal is obtained without the need to preprocess the radio frequency signal with an image reject filter. Such an apparatus may also exhibit an image rejection performance that is robust to frequency deviation of a local oscillator.
摘要翻译：在示例性应用中，根据所公开的实施例的装置接收射频信号并输出中频信号。获得中频信号中的图像分量的抑制，而不需要使用图像抑制滤波器对射频信号进行预处理。这种装置还可以呈现对本地振荡器的频率偏差鲁棒的图像抑制性能。

79. 发明申请

WO2004049580A2 AN AMPS RECEIVER SYSTEM USING A ZERO-IF ARCHITECTURE 审中-公开
标题翻译：使用零中立架构的AMPS接收机系统
公开(公告)号：WO2004049580A2
公开(公告)日：2004-06-10
申请号：PCT/US0302221
申请日：2003-01-24
申请人： QUALCOMM INC
发明人： CICCARELLI STEVEN C , RAGHUPATHY ARUN
IPC分类号： H03G3/30 , H04B1/30 , H04B
CPC分类号： H04B1/406 , H03G3/3068 , H04B1/0003 , H04B1/30
摘要： An AMPS receiver system utilizing a ZIF architecture and processing received forward link signals in the digital domain. The AMPS receiver system includes an antenna (105), a direct converter (110), high dynamic A/D converters (120, 130), low pass filters (140, 150), a phase shifter (160), a digital FM demodulator (180), an accumulator (185) and a controller (190). The direct converter (110) further includes a low noise amplifier (112), a splitter (113), mixers (114, 116) and low pass filters (118, 119). The controller (190) adjusts the gains of the low noise amplifier (112) and the digital VGA (170) based on the average power of the signal outputted by the digital VGA (170).
摘要翻译：采用ZIF架构并在数字领域处理接收到的前向链路信号的AMPS接收机系统。 AMPS接收机系统包括天线（105），直接转换器（110），高动态A / D转换器（120,130），低通滤波器（140,150），移相器（160），数字FM解调器（180），蓄能器（185）和控制器（190）。直接转换器（110）还包括低噪声放大器（112），分离器（113），混频器（114,116）和低通滤波器（118,119）。控制器（190）基于由数字VGA（170）输出的信号的平均功率来调节低噪声放大器（112）和数字VGA（170）的增益。

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