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71. 发明申请

US20130295767A1 INCREASED TRANSISTOR PERFORMANCE BY IMPLEMENTING AN ADDITIONAL CLEANING PROCESS IN A STRESS LINER APPROACH 审中-公开
标题翻译：通过在应力衬里方法中实施附加清洁过程来提高晶体管性能
公开(公告)号：US20130295767A1
公开(公告)日：2013-11-07
申请号：US13462246
申请日：2012-05-02
申请人： Thilo Scheiper , Peter Baars
发明人： Thilo Scheiper , Peter Baars
IPC分类号： H01L21/28 , H01L21/3065
CPC分类号： H01L21/823807 , H01L21/0206 , H01L21/823864 , H01L29/665 , H01L29/7833 , H01L29/7843
摘要： When forming sophisticated transistors on the basis of a highly stressed dielectric material formed above a transistor, the stress transfer efficiency may be increased by reducing the size of the spacer structure of the gate electrode structure prior to depositing the highly stressed material. Prior to the deposition of the highly stressed material, an additional cleaning process may be implemented in order to reduce the presence of any metal contaminants, in particular in the vicinity of the gate electrode structure, which would otherwise result in an increased fringing capacitance.
摘要翻译：当基于形成在晶体管上方的高应力电介质材料形成复杂的晶体管时，通过在沉积高应力材料之前减小栅电极结构的间隔结构的尺寸，可以增加应力传递效率。在沉积高应力材料之前，可以实施额外的清洁工艺，以减少任何金属污染物的存在，特别是在栅电极结构附近，否则会导致增加的边缘电容。

72. 发明申请

US20130193516A1 SRAM INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION 审中-公开
标题翻译： SRAM集成电路及其制造方法
公开(公告)号：US20130193516A1
公开(公告)日：2013-08-01
申请号：US13359242
申请日：2012-01-26
申请人： Matthias Goldbach , Peter Baars
发明人： Matthias Goldbach , Peter Baars
IPC分类号： H01L27/11 , H01L21/762 , H01L21/336
CPC分类号： H01L21/76224 , H01L21/76895 , H01L21/76897 , H01L27/0207 , H01L27/1104
摘要： SRAM ICs and methods for their fabrication are provided. One method includes forming dummy gate electrodes overlying a semiconductor substrate and defining locations of gate electrodes for two cross coupled inverters and two pass gate transistors. A first insulating layer is deposited overlying the dummy gate electrodes and gaps between the dummy gate electrodes are filled with a second insulating layer. The second insulating layer is etched to form inter-gate openings exposing portions of the substrate. The first insulating layer is etched to reduce the thickness of selected locations thereof, and the dummy gate electrodes are removed. A gate electrode metal is deposited and planarized to form gate electrodes and local interconnections coupling the gate electrodes of one inverter to a node between the pull up and pull down transistors of the other inverter and to a source/drain of one of the pass gate transistors.
摘要翻译：提供SRAM IC及其制造方法。一种方法包括形成覆盖在半导体衬底上的虚拟栅电极并且限定用于两个交叉耦合的反相器和两个通过栅极晶体管的栅电极的位置。第一绝缘层沉积在虚拟栅电极的上方，并且虚设栅电极之间的间隙填充有第二绝缘层。蚀刻第二绝缘层以形成露出衬底的部分的栅极间开口。蚀刻第一绝缘层以减小其选定位置的厚度，并且去除伪栅极电极。栅极电极金属被沉积并平坦化以形成将一个反相器的栅电极耦合到另一个反相器的上拉和下拉晶体管之间的节点的栅电极和局部互连，以及一个通栅晶体管之一的源极/漏极。

73. 发明申请

US20130189833A1 Method of Forming Self-Aligned Contacts for a Semiconductor Device 有权
标题翻译：形成半导体器件的自对准触点的方法
公开(公告)号：US20130189833A1
公开(公告)日：2013-07-25
申请号：US13354739
申请日：2012-01-20
申请人： Peter Baars , Andy Wei , Erik Geiss , Martin Mazur
发明人： Peter Baars , Andy Wei , Erik Geiss , Martin Mazur
IPC分类号： H01L21/28
CPC分类号： H01L21/76897 , H01L29/66545
摘要： Disclosed herein is a method of forming self-aligned contacts for a semiconductor device. In one example, the method includes forming a plurality of spaced-apart sacrificial gate electrodes above a semiconducting substrate, wherein each of the gate electrodes has a gate cap layer positioned on the gate electrode, and performing at least one etching process to define a self-aligned contact opening between the plurality of spaced-apart sacrificial gate electrodes. The method further includes removing the gate cap layers to thereby expose an upper surface of each of the sacrificial gate electrodes, depositing at least one layer of conductive material in said self-aligned contact opening and removing portions of the at least one layer of conductive material that are positioned outside of the self-aligned contact opening to thereby define at least a portion of a self-aligned contact positioned in the self-aligned contact opening.
摘要翻译：本文公开了一种形成用于半导体器件的自对准接触件的方法。在一个示例中，该方法包括在半导体衬底之上形成多个间隔开的牺牲栅电极，其中每个栅电极具有位于栅电极上的栅极帽层，并执行至少一个蚀刻工艺以限定自身在多个间隔开的牺牲栅电极之间的对准接触开口。该方法还包括去除栅极盖层，从而暴露每个牺牲栅电极的上表面，在所述自对准接触开口中沉积至少一层导电材料，并去除至少一层导电材料的部分其定位在自对准接触开口的外侧，从而限定位于自对准接触开口中的自对准接触件的至少一部分。

74. 发明授权

US08455960B2 High performance HKMG stack for gate first integration 有权
标题翻译：高性能HKMG堆栈，用于门控第一次集成
公开(公告)号：US08455960B2
公开(公告)日：2013-06-04
申请号：US13185112
申请日：2011-07-18
申请人： Frank Jakubowski , Peter Baars , Till Schloesser
发明人： Frank Jakubowski , Peter Baars , Till Schloesser
IPC分类号： H01L29/00
CPC分类号： H01L29/517 , H01L21/28088 , H01L29/4966 , H01L29/7833
摘要： Semiconductor devices are formed with a silicide interface between the work function layer and polycrystalline silicon. Embodiments include forming a high-k/metal gate stack by: forming a high-k dielectric layer on a substrate, forming a work function metal layer on the high-k dielectric layer, forming a silicide on the work function metal layer, and forming a poly Si layer on the silicide. Embodiments include forming the silicide by: forming a reactive metal layer in situ on the work function layer, forming an a-Si layer in situ on the entire upper surface of the reactive metal layer, and annealing concurrently with forming the poly Si Layer.
摘要翻译：半导体器件在功函数层与多晶硅之间形成硅化物界面。实施例包括通过以下方式形成高k /金属栅极堆叠：在衬底上形成高k电介质层，在高k电介质层上形成功函数金属层，在功函数金属层上形成硅化物，以及形成硅化物上的多晶硅层。实施例包括：通过在功函数层上原位形成反应性金属层，在反应性金属层的整个上表面上原位形成a-Si层，并与形成多晶硅层同时进行退火来形成硅化物。

75. 发明申请

US20130099295A1 REPLACEMENT GATE FABRICATION METHODS 有权
标题翻译：更换浇口制造方法
公开(公告)号：US20130099295A1
公开(公告)日：2013-04-25
申请号：US13281236
申请日：2011-10-25
申请人： Peter Baars , Matthias Goldbach
发明人： Peter Baars , Matthias Goldbach
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L27/0886 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： Semiconductor devices and related fabrication methods are provided. An exemplary fabrication method involves forming a pair of gate structures having a dielectric region disposed between a first gate structure of the pair and a second gate structure of the pair, and forming a voided region in the dielectric region between the first gate structure and the second gate structure. The first and second gate structures each include a first gate electrode material, wherein the method continues by removing the first gate electrode material to provide second and third voided regions corresponding to the gate structures and forming a second gate electrode material in the first voided region, the second voided region, and the third voided region.
摘要翻译：提供了半导体器件和相关的制造方法。示例性的制造方法包括形成一对栅极结构，其具有布置在该对的第一栅极结构和该对的第二栅极结构之间的介质区域，并且在第一栅极结构和第二栅极结构之间的介电区域中形成空隙区域门结构。第一和第二栅极结构各自包括第一栅极电极材料，其中该方法通过去除第一栅电极材料继续，以提供对应于栅极结构的第二和第三空隙区域，并在第一空隙区域中形成第二栅电极材料，第二空隙区域和第三空隙区域。

76. 发明授权

US08357978B1 Methods of forming semiconductor devices with replacement gate structures 有权
标题翻译：用替换栅极结构形成半导体器件的方法
公开(公告)号：US08357978B1
公开(公告)日：2013-01-22
申请号：US13230360
申请日：2011-09-12
申请人： Peter Baars , Andy Wei , Richard Carter
发明人： Peter Baars , Andy Wei , Richard Carter
IPC分类号： H01L21/70 , H01L29/76 , H01L21/8238 , H01L21/8234 , H01L21/336
CPC分类号： H01L27/088 , H01L21/76897 , H01L21/823828 , H01L21/823871 , H01L23/485 , H01L29/4966 , H01L29/66545 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Disclosed herein are various methods of forming replacement gate structures on semiconductor devices and devices incorporating such gate structures. In one example, the device includes a plurality of gate structures and at least one sidewall spacer positioned proximate each of the gate structures, a metal silicide region in a source/drain region formed in a substrate, wherein the metal silicide region extend laterally so as to contact the sidewall spacer positioned proximate each of the gate structures and a conductive contact positioned between the gate structures that conductively contacts the metal silicide region, wherein the conductive contact has a bottom portion that is wider than an upper portion of the conductive contact.
摘要翻译：这里公开了在半导体器件上形成替代栅极结构和结合这种栅极结构的器件的各种方法。在一个示例中，该器件包括多个栅极结构和位于每个栅极结构附近的至少一个侧壁间隔物，在基底中形成的源极/漏极区中的金属硅化物区域，其中金属硅化物区域横向延伸以便接触定位在每个栅极结构附近的侧壁隔离物和位于导电接触金属硅化物区域的栅极结构之间的导电接触，其中导电接触件具有比导电接触件的上部更宽的底部部分。

77. 发明申请

US20120292671A1 Method of Forming Spacers That Provide Enhanced Protection for Gate Electrode Structures 有权
标题翻译：形成对栅极电极结构提供增强保护的间隔物的方法
公开(公告)号：US20120292671A1
公开(公告)日：2012-11-22
申请号：US13108363
申请日：2011-05-16
申请人： Peter Baars , Sven Beyer , Jan Hoentschel , Thilo Scheiper
发明人： Peter Baars , Sven Beyer , Jan Hoentschel , Thilo Scheiper
IPC分类号： H01L21/3213 , H01L29/78
CPC分类号： H01L29/66772 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/78618 , H01L29/78687
摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming a gate electrode structure above a semiconducting substrate and forming a plurality of spacers proximate the gate electrode structures, wherein the plurality of spacers comprises a first silicon nitride spacer positioned adjacent a sidewall of the gate electrode structure, a generally L-shaped silicon nitride spacer positioned adjacent the first silicon nitride spacer, and a silicon dioxide spacer positioned adjacent the generally L-shaped silicon nitride spacer.
摘要翻译：本文公开了形成半导体器件的方法。在一个示例中，该方法包括在半导体衬底之上形成栅电极结构并在栅电极结构附近形成多个间隔区，其中多个间隔物包括邻近栅电极结构的侧壁定位的第一氮化硅间隔区，位于第一氮化硅间隔物附近的通常为L形的氮化硅间隔物，和位于大致L形的氮化硅间隔物附近的二氧化硅隔离物。

78. 发明申请

US20120282712A1 DOPANT MARKER FOR PRECISE RECESS CONTROL 审中-公开
标题翻译：用于精密控制的烙印标记
公开(公告)号：US20120282712A1
公开(公告)日：2012-11-08
申请号：US13471756
申请日：2012-05-15
申请人： Dmytro Chumakov , Peter Baars
发明人： Dmytro Chumakov , Peter Baars
IPC分类号： H01L21/66 , H01L21/306
CPC分类号： H01L21/31116 , H01L21/31053 , H01L22/12 , H01L22/26
摘要： Recess markers are implanted in a material during deposition and used during etching of the material for in-situ removal rate and removal homogeneity-over-radius definitions. An embodiment includes depositing a material on a substrate, implanting two dopants at two predetermined times, respectively, during deposition of the material, etching the material, detecting depths of the two dopants during etching, calculating the removal rate of the material in situ from the depths of the two dopants, and determining from the removal rate an etching stop position. Embodiments further include laterally implanting two dopants in a material at a predetermined depth during deposition, etching the material, detecting the positions and intensities of the two dopants during etching, and calculating lateral homogeneity of the material in situ from intensities of the dopants. Embodiments further include in situ corrective action for the removal process based on the determined removal rate and lateral homogeneity.
摘要翻译：凹陷标记物在沉积期间植入材料中并且在蚀刻材料期间用于原位去除速率和去除均匀度超半径定义。一个实施方案包括在衬底上沉积材料，在沉积材料期间分别在两个预定时间内注入两种掺杂剂，蚀刻材料，在蚀刻期间检测两种掺杂剂的深度，从原位离开材料的去除速率两个掺杂剂的深度，并根据去除率确定蚀刻停止位置。实施例还包括在沉积期间在预定深度的材料中横向注入两种掺杂剂，蚀刻材料，检测蚀刻期间两种掺杂剂的位置和强度，以及根据掺杂剂的强度计算材料的侧向均匀性。实施例还包括基于确定的去除速率和横向均匀性的去除过程的原位校正作用。

79. 发明授权

US08222103B1 Semiconductor device with embedded low-K metallization 有权
标题翻译：具有嵌入式低K金属化的半导体器件
公开(公告)号：US08222103B1
公开(公告)日：2012-07-17
申请号：US13027739
申请日：2011-02-15
申请人： Peter Baars , Till Schloesser
发明人： Peter Baars , Till Schloesser
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L27/10852 , H01L23/5223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L27/10817 , H01L28/92 , H01L2924/0002 , H01L2924/00
摘要： Generally, the subject matter disclosed herein relates to a semiconductor device with embedded low-k metallization. A method is disclosed that includes forming a plurality of copper metallization layers that are coupled to a plurality of logic devices in a logic area of a semiconductor device and, after forming the plurality of copper metallization layers, forming a plurality of capacitors in a memory array of the semiconductor device. The capacitors are formed using a non-low-k dielectric material (k value greater than 3), while the copper metallization layers are formed in layers of low-k dielectric material (k value less than 3). A semiconductor device is also disclosed which includes a plurality of logic devices, a memory array comprising a plurality of capacitors, a conductive contact plate coupled to the plurality of capacitors, and a plurality of copper metallization layers coupled to the logic devices, wherein the plurality of copper metallization layers are positioned at a level that is below a level of a bottom surface of the contact plate. A material other than a low-k dielectric material is positioned between the plurality of capacitors in the memory array.
摘要翻译：通常，这里公开的主题涉及具有嵌入式低k金属化的半导体器件。公开了一种方法，其包括形成耦合到半导体器件的逻辑区域中的多个逻辑器件的多个铜金属化层，并且在形成多个铜金属化层之后，在存储器阵列中形成多个电容器的半导体器件。使用非低k电介质材料（k值大于3）形成电容器，而铜金属化层以低k电介质材料（k值小于3）形成。还公开了一种半导体器件，其包括多个逻辑器件，包括多个电容器的存储器阵列，耦合到多个电容器的导电接触板以及耦合到逻辑器件的多个铜金属化层，其中多个的铜金属化层被定位在低于接触板的底表面的水平的水平。除了低k电介质材料之外的材料位于存储器阵列中的多个电容器之间。

80. 发明申请

US20100090263A1 MEMORY DEVICES INCLUDING SEMICONDUCTOR PILLARS 审中-公开
标题翻译：包括半导体支柱的存储器件
公开(公告)号：US20100090263A1
公开(公告)日：2010-04-15
申请号：US12249225
申请日：2008-10-10
申请人： Gerhard Kunkel , Peter Baars
发明人： Gerhard Kunkel , Peter Baars
IPC分类号： H01L27/105 , H01L21/8239
CPC分类号： H01L29/66666 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L29/7827
摘要： One embodiment relates to an integrated circuit that includes a memory array of pillars arranged in rows and columns. The pillars are separated from one another by row trenches and column trenches. The column trenches include a pair of parallel column trenches. A first trench of the pair includes two parallel bit lines coupled to pillars adjacent to the first trench. A second trench of the pair is free of bit lines. Other methods, devices, and systems are also disclosed.
摘要翻译：一个实施例涉及一种集成电路，其包括以行和列排列的柱的存储器阵列。柱子通过行沟槽和柱沟槽彼此分开。列沟槽包括一对平行的柱沟槽。该对的第一沟槽包括耦合到邻近第一沟槽的柱的两个平行位线。该对的第二个沟槽没有位线。还公开了其它方法，装置和系统。

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