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71. 发明授权

US08341501B2 Adaptive endurance coding of non-volatile memories 有权
标题翻译：非易失性存储器的适应性耐力编码
公开(公告)号：US08341501B2
公开(公告)日：2012-12-25
申请号：US12433669
申请日：2009-04-30
申请人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano
发明人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F12/0246 , G06F11/1012 , G06F2212/1036 , G06F2212/401 , G06F2212/403 , G06F2212/7207 , G11C16/349
摘要： Adaptive endurance coding including a method for storing data that includes receiving write data and a write address. A compression algorithm is applied to the write data to generate compressed data. An endurance code is applied to the compressed data to generate a codeword. The endurance code is selected and applied in response to the amount of space saved by applying the compression to the write data. The codeword is written to the write address.
摘要翻译：自适应耐力编码包括用于存储包括接收写入数据和写入地址的数据的方法。将压缩算法应用于写入数据以生成压缩数据。将耐力码应用于压缩数据以产生码字。响应于通过将压缩应用于写数据而节省的空间量来选择和应用耐久代码。代码字被写入写入地址。

72. 发明授权

US08331168B2 Increased capacity heterogeneous storage elements 有权
标题翻译：增加容量的异构存储元件
公开(公告)号：US08331168B2
公开(公告)日：2012-12-11
申请号：US12433157
申请日：2009-04-30
申请人： Ibrahim M. Elfadel , Michele Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Ibrahim M. Elfadel , Michele Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G11C7/00
CPC分类号： G11C29/08 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2211/5641
摘要： Providing increased capacity in heterogeneous storage elements including a method for storing data including a write process writing to a memory and a read process reading from the memory. Physical characteristics of memory cells in the memory support different sets of data levels. The write process takes into account the different sets of data levels when writing to the memory. The read process first obtains data in the memory and subsequently determines how to interpret the data.
摘要翻译：提供异构存储元件的增加的容量，包括用于存储数据的方法，包括对存储器的写入过程写入和从存储器读取读取过程。存储器单元的物理特性在存储器中支持不同的数据级别。写入过程在写入存储器时考虑到不同的数据级别集。读取过程首先获得存储器中的数据，然后确定如何解释数据。

73. 发明申请

US20120311262A1 MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE 审中-公开
标题翻译：用于改善记忆性能的存储单元预置
公开(公告)号：US20120311262A1
公开(公告)日：2012-12-06
申请号：US13151043
申请日：2011-06-01
申请人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
发明人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/00 , G06F12/08 , G06F12/0802 , G06F12/0891
摘要： Memory cell presetting for improved performance including a system that includes a memory, a cache, and a memory controller. The memory includes memory lines made up of memory cells. The cache includes cache lines that correspond to a subset of the memory lines. The memory controller is in communication with the memory and the cache. The memory controller is configured to perform a method that includes scheduling a request to set memory cells of a memory line to a common specified state in response to a cache line attaining a dirty state.
摘要翻译：用于改进性能的存储单元预置，包括包括存储器，高速缓存和存储器控制器的系统。存储器包括由存储单元组成的存储器线。缓存包括对应于存储器线的子集的高速缓存行。存储器控制器与存储器和缓存器通信。存储器控制器被配置为执行一种方法，该方法包括根据达到肮脏状态的高速缓存线来调度将存储器线的存储单元设置为公共指定状态的请求。

74. 发明授权

US08185899B2 Prediction based priority scheduling 有权
标题翻译：基于预测的优先级调度
公开(公告)号：US08185899B2
公开(公告)日：2012-05-22
申请号：US11683147
申请日：2007-03-07
申请人： David M. Daly , Peter A. Franaszek , Luis A. Lastras-Montano
发明人： David M. Daly , Peter A. Franaszek , Luis A. Lastras-Montano
IPC分类号： G06F9/46
CPC分类号： G06F9/4881
摘要： Systems and methods are provided that schedule task requests within a computing system based upon the history of task requests. The history of task requests can be represented by a historical log that monitors the receipt of high priority task request submissions over time. This historical log in combination with other user defined scheduling rules is used to schedule the task requests. Task requests in the computer system are maintained in a list that can be divided into a hierarchy of queues differentiated by the level of priority associated with the task requests contained within that queue. The user-defined scheduling rules give scheduling priority to the higher priority task requests, and the historical log is used to predict subsequent submissions of high priority task requests so that lower priority task requests that would interfere with the higher priority task requests will be delayed or will not be scheduled for processing.
摘要翻译：提供了系统和方法，其基于任务请求的历史在计算系统内调度任务请求。任务请求的历史可以由历史日志表示，该日志监视随时间的收到高优先级任务请求提交。该历史日志与其他用户定义的调度规则相结合用于调度任务请求。计算机系统中的任务请求被维护在列表中，该列表可以被划分成由包含在该队列内的任务请求所关联的优先级所区分的队列层次。用户定义的调度规则给予较高优先级任务请求的调度优先级，并且使用历史日志来预测高优先级任务请求的后续提交，使得将干扰较高优先级任务请求的较低优先级任务请求将被延迟或不会安排进行处理。

75. 发明授权

US08176234B2 Multi-write coding of non-volatile memories 有权
标题翻译：非易失性存储器的多写编码
公开(公告)号：US08176234B2
公开(公告)日：2012-05-08
申请号：US12631470
申请日：2009-12-04
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/401 , G11C11/5621 , G11C16/3418 , G11C16/349
摘要： Multi-write coding of non-volatile memories including a method that receives write data, and a write address of a memory page. The memory page is in either an erased state or a previously written state. If the memory page is in the erased state: selecting a first codeword from a code such that the first codeword encodes the write data and is consistent with a target set of distributions of electrical charge levels in the memory page; and writing the first codeword to the memory page. If the memory page is in the previously written state: selecting a coset from a linear code such that the coset encodes the write data and includes one or more words that are consistent with previously written content of the memory page; selecting a subsequent codeword from the one or more words in the coset; and writing the subsequent codeword to the memory page.
摘要翻译：包括接收写入数据的方法的非易失性存储器的多写入编码以及存储器页面的写入地址。存储器页面处于擦除状态或先前写入的状态。如果存储器页面处于擦除状态：从代码中选择第一码字，使得第一码字对写入数据进行编码，并与存储器页面中的电荷电平分布的目标集合一致; 以及将所述第一码字写入所述存储器页。如果存储器页面处于先前写入的状态：从线性代码选择陪集，使得陪集对编写数据进行编码并且包括与存储器页面的先前写入的内容一致的一个或多个单词; 从陪集中的一个或多个单词中选择随后的码字; 以及将所述后续码字写入所述存储器页面。

76. 发明授权

US08107276B2 Resistive memory devices having a not-and (NAND) structure 有权
标题翻译：具有非 - 和（NAND）结构的电阻式存储器件
公开(公告)号：US08107276B2
公开(公告)日：2012-01-31
申请号：US12631310
申请日：2009-12-04
申请人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
发明人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C15/046 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C16/0483 , G11C2013/0088 , G11C2013/0092 , G11C2213/75
摘要： Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element. The memory element access device is connected in parallel to the resistive memory element.
摘要翻译：具有包括电阻存储单元的非 - 和（NAND）结构的电阻存储器。电阻性存储单元包括用于存储电阻值的电阻性存储器元件和用于控制对电阻式存储器元件的访问的存储元件访问器件。存储元件存取装置与电阻式存储元件并联连接。

77. 发明申请

US20110320921A1 FAILING BUS LANE DETECTION USING SYNDROME ANALYSIS 有权
标题翻译：使用综合分析故障总线检测
公开(公告)号：US20110320921A1
公开(公告)日：2011-12-29
申请号：US12822498
申请日：2010-06-24
申请人： Kevin C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Lisa C. Gower
发明人： Kevin C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Lisa C. Gower
IPC分类号： G06F11/07
CPC分类号： G06F11/10 , H03M13/09 , H04L1/0061 , H04L1/24 , H04L2001/0094
摘要： Failing bus lane detection using syndrome analysis, including a method for receiving a plurality of syndromes of an error detection code, the error detection code associated with a plurality of frames that have been transmitted on a bus that includes a plurality of lanes and is protected by the error detection code. The method includes performing for each of the lanes in each of the syndromes: decoding the syndrome under an assumption that the lane is a failing lane, the decoding outputting a decode result; determining if the decode result is a valid decode; and voting for the lane in response to determining that the decode result is a valid decode. A failing lane is then identified in response to the voting, with the failing lane being characterized by having more votes than at least one other lane on the bus.
摘要翻译：包括用于接收错误检测码的多个综合征的方法，所述错误检测码与已经在包括多个车道的总线上发送并被由多个车道保护的多个帧相关联的错误检测码错误检测码。该方法包括对每个综合征中的每个通道执行：在所述通道是故障通道的假设下解码所述综合征，所述解码输出解码结果; 确定解码结果是否是有效的解码; 并且响应于确定解码结果是有效解码而对该通道进行投票。然后，响应于投票，确定失败的车道，失败的车道的特征在于比公车上的至少另一个车道具有更多的票数。

78. 发明授权

US08041989B2 System and method for providing a high fault tolerant memory system 有权
标题翻译：提供高容错存储系统的系统和方法
公开(公告)号：US08041989B2
公开(公告)日：2011-10-18
申请号：US11769936
申请日：2007-06-28
申请人： Luis A. Lastras-Montano , James A. O'Connor , Luiz C. Alves , William J. Clarke , Timothy J. Dell , Thomas J. Dewkett , Kevin C. Gower
发明人： Luis A. Lastras-Montano , James A. O'Connor , Luiz C. Alves , William J. Clarke , Timothy J. Dell , Thomas J. Dewkett , Kevin C. Gower
IPC分类号： G06F11/00
CPC分类号： G06F11/1044 , G11C5/04 , G11C29/4401 , G11C29/81 , G11C2029/0409 , G11C2029/0411
摘要： A system and method for providing a high fault tolerant memory system. The system includes a memory system having a memory controller, a plurality of memory modules and a mechanism. The plurality of memory modules are in communication with the memory controller and with a plurality of memory devices. The plurality of memory devices include at least one spare memory device for providing memory device sparing capability. The mechanism is for detecting that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the possible memory device failure.
摘要翻译：一种用于提供高容错存储器系统的系统和方法。该系统包括具有存储器控制器，多个存储器模块和机构的存储器系统。多个存储器模块与存储器控制器和多个存储器件通信。多个存储器件包括用于提供存储器件备用能力的至少一个备用存储器件。该机制用于检测存储器模块中的一个已经失败，可能与另一个存储器模块上的存储器件故障重合。该机制允许存储器系统在存在存储器模块故障和可能的存储器件故障的情况下继续运行不受损害。

79. 发明申请

US20110246703A1 CONSTRAINED CODING TO REDUCE FLOATING GATE COUPLING IN NON-VOLATILE MEMORIES 失效
标题翻译：约束编码以减少非易失性存储器中的浮动栅极耦合
公开(公告)号：US20110246703A1
公开(公告)日：2011-10-06
申请号：US12751197
申请日：2010-03-31
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C16/0483 , G06F12/0246 , G06F2212/7202 , G11C7/1006 , G11C16/10
摘要： Constrained coding to reduce floating gate coupling in non-volatile memories including a method for storing data. The method includes receiving write data to be written to a flash memory device, selecting a codeword in response to the write data, and writing the codeword to the flash memory device. The codeword is selected to reduce floating gate coupling in the flash memory device by preventing specified symbol patterns from occurring in the codeword.
摘要翻译：约束编码以减少非易失性存储器中的浮动栅极耦合，包括用于存储数据的方法。该方法包括接收要写入闪速存储器件的写入数据，响应写入数据选择一个代码字，以及将该代码字写入闪存器件。选择码字以通过防止在码字中发生指定的符号模式来减少闪存器件中的浮动栅极耦合。

80. 发明申请

US20110026318A1 ITERATIVE WRITE PAUSING TECHNIQUES TO IMPROVE READ LATENCY OF MEMORY SYSTEMS 有权
标题翻译：迭代写暂停技术来改善读取存储器系统的延迟
公开(公告)号：US20110026318A1
公开(公告)日：2011-02-03
申请号：US12533548
申请日：2009-07-31
申请人： Michele M. Franceschini , Luis A. Lastras-Montano , Moinuddin K. Qureshi , Vijayalakshmi Srinivasan
发明人： Michele M. Franceschini , Luis A. Lastras-Montano , Moinuddin K. Qureshi , Vijayalakshmi Srinivasan
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G06F13/1642 , G06F13/161
摘要： Iterative write pausing techniques to improve read latency of memory systems including memory systems with phase change memory (PCM) devices. A PCM device includes a plurality of memory locations and a mechanism for executing an iterative write to one or more of the memory locations in response to receiving a write command that includes data to be written. The executing includes initiating the iterative write, updating a state of the iterative write, pausing the iterative write including saving the state in response to receiving a pause command, and resuming the iterative write in response to receiving a resume command. The resuming is responsive to the saved state and to the data to be written.
摘要翻译：迭代写暂停技术，以提高内存系统（包括具有相变存储器（PCM）设备的存储器系统）的读取延迟。 PCM设备包括多个存储器位置和用于响应于接收到包括要写入的数据的写入命令而执行对一个或多个存储器位置的迭代写入的机制。执行包括启动迭代写入，更新迭代写入的状态，暂停迭代写入，包括响应于接收到暂停命令而保存状态，以及响应于接收到恢复命令恢复迭代写入。恢复响应于保存的状态和要写入的数据。

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