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71. 发明授权

US07417303B2 System and method for ESD protection 有权
标题翻译： ESD保护的系统和方法
公开(公告)号：US07417303B2
公开(公告)日：2008-08-26
申请号：US11521361
申请日：2006-09-15
申请人： Agnes N. Woo , Kenneth R. Kindsfater , Fang Lu
发明人： Agnes N. Woo , Kenneth R. Kindsfater , Fang Lu
IPC分类号： H01L29/72
CPC分类号： H01L23/50 , H01F17/0006 , H01F17/0013 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L23/60 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B5/364 , H03D7/161 , H03D7/18 , H03G1/0029 , H03H11/1291 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/23 , H04B1/28 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.
摘要翻译：描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。接收机前端提供可编程衰减和可编程增益低噪声放大器。频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。过滤器调谐和电感Q补偿温度在芯片上执行。滤波器采用多轨螺旋电感。使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。结合滤波，频率规划提供了额外的镜像抑制。片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。差分晶体振荡器有利地用作频率参考。差分信号传输有利地用于整个接收机。 ESD保护由保护信号完整性的焊盘环和ESD钳位结构提供。还提供每个引脚上的分流器，以放电ESD积聚。分流器利用栅极升压结构来提供足够的小信号RF性能和最小的寄生负载。

72. 发明申请

US20080115072A1 METHOD AND APPARATUS FOR VISUALLY ASSISTING LANGUAGE INPUT MODE INDENTIFICATION 审中-公开
标题翻译：用于视觉辅助语言输入模式识别的方法和装置
公开(公告)号：US20080115072A1
公开(公告)日：2008-05-15
申请号：US11558121
申请日：2006-11-09
申请人： Fang Lu
发明人： Fang Lu
IPC分类号： G06F3/048
CPC分类号： G06F3/04817 , G06F3/04812
摘要： A method and apparatus for visually assisting language input mode identification is provided. The method includes selecting a plurality of language modes and a plurality of language icons. The method associates each of the plurality of language modes with one of the plurality of language icons and selects at least one application border and associates each of the plurality of language modes with one of application borders. An embodiment is directed towards a computer program for executing a language identification mode of an application. The program includes selecting at least one language mode selecting at least one language icon to form a plurality of language mode/language icon pairs. The program includes associating each of the language mode/language icon pairs with at least one keyboard key and selecting one of the pluralities of language mode/language icon pairs with an associated keyboard key.
摘要翻译：提供了一种视觉辅助语言输入模式识别的方法和装置。该方法包括选择多种语言模式和多种语言图标。该方法将多个语言模式中的每一个与多个语言图标中的一个相关联，并且选择至少一个应用边界，并将多个语言模式中的每一个与应用边界之一相关联。一个实施例涉及用于执行应用程序的语言识别模式的计算机程序。该程序包括选择至少一种语言模式来选择至少一种语言图标以形成多种语言模式/语言图标对。该程序包括将每个语言模式/语言图标对与至少一个键盘键相关联，并且使用相关的键盘键选择多个语言模式/语言图标对中的一个。

73. 发明申请

US20080036037A1 System and method for ESD protection 有权
标题翻译： ESD保护的系统和方法
公开(公告)号：US20080036037A1
公开(公告)日：2008-02-14
申请号：US11878750
申请日：2007-07-26
申请人： Agnes Woo , Kenneth Kindsfater , Fang Lu
发明人： Agnes Woo , Kenneth Kindsfater , Fang Lu
IPC分类号： H01L29/00
CPC分类号： H01L23/50 , H01F17/0006 , H01F17/0013 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L23/60 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B5/364 , H03D7/161 , H03D7/18 , H03G1/0029 , H03H11/1291 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/23 , H04B1/28 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.
摘要翻译：描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。接收机前端提供可编程衰减和可编程增益低噪声放大器。频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。过滤器调谐和电感Q补偿温度在芯片上执行。滤波器采用多轨螺旋电感。使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。结合滤波，频率规划提供了额外的镜像抑制。片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。差分晶体振荡器有利地用作频率参考。差分信号传输有利地用于整个接收机。 ESD保护由保护信号完整性的焊盘环和ESD钳位结构提供。还提供每个引脚上的分流器，以放电ESD积聚。分流器利用栅极升压结构来提供足够的小信号RF性能和最小的寄生负载。

74. 发明授权

US07203227B1 All digital reference frequency locking 有权
标题翻译：全数字参考频率锁定
公开(公告)号：US07203227B1
公开(公告)日：2007-04-10
申请号：US10294048
申请日：2002-11-14
申请人： Bruce J. Currivan , Ravi Bhaskaran , Thomas J. Kolze , Kevin Lee Miller , Jeffrey S. Putnam , Fang Lu , Tak K. Lee , Thuji S. Lin , Loke Kun Tan , Gopal Triplicane Venkatesan , Hsin-An Liu , Jonathan S. Min , James P. Cavallo
发明人： Bruce J. Currivan , Ravi Bhaskaran , Thomas J. Kolze , Kevin Lee Miller , Jeffrey S. Putnam , Fang Lu , Tak K. Lee , Thuji S. Lin , Loke Kun Tan , Gopal Triplicane Venkatesan , Hsin-An Liu , Jonathan S. Min , James P. Cavallo
IPC分类号： H04B1/38
CPC分类号： H04L12/2801
摘要： All digital reference frequency locking. An all digital approach is provided for operation within one or more CMs within a cable modem communication system to lock the upstream of the one or more CMs to the downstream symbol clock provided from a CMTS. The locking of the CM's upstream may be performed using one of at least three different functions: (1) Locking the upstream symbol clock phase to the downstream symbol clock phase, (2) Locking the downstream symbol clock phase to the headend reference clock phase (typically 10.24 MHz or integer multiple thereof), and (3) Locking the upstream carrier frequency to the downstream symbol clock frequency. The all-digital techniques for supporting all digital reference frequency locking functionality provide high performance to support S-CDMA and other synchronous modulation techniques.
摘要翻译：全数字参考频率锁定。提供全数字方法以在电缆调制解调器通信系统内的一个或多个CM内操作，以将一个或多个CM的上游锁定到从CMTS提供的下游符号时钟。 CM的上游的锁定可以使用至少三种不同的功能中的一种执行：（1）将上游符号时钟相位锁定到下游符号时钟相位，（2）将下游符号时钟相位锁定到前端参考时钟相位通常为10.24MHz或其整数倍），以及（3）将上游载波频率锁定到下游符号时钟频率。用于支持所有数字参考频率锁定功能的全数字技术提供了高性能以支持S-CDMA和其他同步调制技术。

75. 发明申请

US20060274778A1 System and method for detecting collisions in a shared communications medium 有权
公开(公告)号：US20060274778A1
公开(公告)日：2006-12-07
申请号：US11489525
申请日：2006-07-20
申请人： Bruce Currivan , Jonathan Min , Fang Lu
发明人： Bruce Currivan , Jonathan Min , Fang Lu
IPC分类号： H04L12/413
CPC分类号： H04L12/44 , H04L12/2801
摘要： A system for detecting collisions in a shared communications medium, such as a TDMA medium, includes a receive path adapted to generate a first intermediate signal, a second intermediate signal, and a data symbol sequence from an input signal. A preamble detection module generates a correlation metric from the first intermediate signal. A power measurement module generates a power indication signal from the second intermediate signal. A noise measurement module generates a noise indication signal from the second intermediate signal and the data symbol sequence. A processing module is adapted to characterize the input signal as a collision for certain values of correlation metric, power indication signal, and noise indication signal.

76. 发明授权

US07120123B1 Pre-equalization technique for upstream communication between cable modem and headend 有权
标题翻译：电缆调制解调器和前端之间的上行通信的预均衡技术
公开(公告)号：US07120123B1
公开(公告)日：2006-10-10
申请号：US09710238
申请日：2000-11-09
申请人： Thomas J. Quigley , Jonathan S. Min , Lisa V. Denney , Henry Samueli , Sean F. Nazareth , Feng Chen , Fang Lu , Christopher R. Jones
发明人： Thomas J. Quigley , Jonathan S. Min , Lisa V. Denney , Henry Samueli , Sean F. Nazareth , Feng Chen , Fang Lu , Christopher R. Jones
IPC分类号： H04J1/16
CPC分类号： H04J3/0682 , H04B1/1036 , H04J3/0655 , H04L1/0003 , H04L1/0009 , H04L1/0061 , H04L1/203 , H04L12/2801 , H04L25/03343 , H04L2025/03808
摘要： A number of features for enhancing the performance of a cable transmission system in which data is transmitted between a cable modem termination system at a headend and a plurality of cable modems located different distances from the headend. The power transmission level, slot timing, and equalization of the cable modems are set by a ranging process. Data is transmitted by the modems in fragmented form. Various measures are taken to make transmission from the cable modems robust. The upstream data transmission is controlled to permit multiple access from the cable modems.
摘要翻译：用于增强电缆传输系统的性能的许多特征，其中数据在前端的电缆调制解调器终端系统与位于与头端不同距离的多个电缆调制解调器之间传输。电缆调制解调器的功率传输电平，时隙定时和均衡由测距过程设置。调制解调器以分段形式传输数据。采取各种措施使电缆调制解调器的传输稳健。控制上游数据传输以允许来自电缆调制解调器的多次访问。

77. 发明授权

US07115952B2 System and method for ESD protection 有权
公开(公告)号：US07115952B2
公开(公告)日：2006-10-03
申请号：US11171325
申请日：2005-07-01
申请人： Agnes N. Woo , Kenneth R. Kindsfater , Fang Lu
发明人： Agnes N. Woo , Kenneth R. Kindsfater , Fang Lu
IPC分类号： H01L29/72
CPC分类号： H01L23/50 , H01F17/0006 , H01F17/0013 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L23/60 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B5/364 , H03D7/161 , H03D7/18 , H03G1/0029 , H03H11/1291 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/23 , H04B1/28 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.

78. 发明授权

US07103065B1 Data packet fragmentation in a cable modem system 有权
标题翻译：电缆调制解调器系统中的数据包碎片
公开(公告)号：US07103065B1
公开(公告)日：2006-09-05
申请号：US09714713
申请日：2000-11-16
申请人： Thomas J. Quigley , Jonathan S. Min , Lisa V. Denney , Henry Samueli , Sean F. Nazareth , Feng Chen , Fang Lu , Christopher R. Jones
发明人： Thomas J. Quigley , Jonathan S. Min , Lisa V. Denney , Henry Samueli , Sean F. Nazareth , Feng Chen , Fang Lu , Christopher R. Jones
IPC分类号： H04J3/16 , H04J3/24
CPC分类号： H04L41/142 , H04B1/1027 , H04B1/1036 , H04J3/0655 , H04J3/0682 , H04L1/0003 , H04L1/0009 , H04L1/0045 , H04L1/0061 , H04L1/203 , H04L5/003 , H04L5/1446 , H04L12/2801 , H04L25/03019 , H04L25/03057 , H04L25/03343 , H04L27/0014 , H04L27/2601 , H04L27/34 , H04L2025/03808 , H04W72/085 , Y02D50/10
摘要： A number of features for enhancing the performance of a cable transmission system in which data is transmitted between a cable modem termination system at a headend and a plurality of cable modems located different distances from the headend. The power transmission level, slot timing, and equalization of the cable modems are set by a ranging process. Data is transmitted by the modems in fragmented form. Various measures are taken to make transmission from the cable modems robust. The upstream data transmission is controlled to permit multiple access from the cable modems.
摘要翻译：用于增强电缆传输系统的性能的许多特征，其中数据在前端的电缆调制解调器终端系统与位于与头端不同距离的多个电缆调制解调器之间传输。电缆调制解调器的功率传输电平，时隙定时和均衡由测距过程设置。调制解调器以分段形式传输数据。采取各种措施使电缆调制解调器的传输稳健。控制上游数据传输以允许来自电缆调制解调器的多次访问。

79. 发明申请

US20050236673A1 System and method for ESD protection 有权
标题翻译： ESD保护的系统和方法
公开(公告)号：US20050236673A1
公开(公告)日：2005-10-27
申请号：US11171325
申请日：2005-07-01
申请人： Agnes Woo , Kenneth Kindsfater , Fang Lu
发明人： Agnes Woo , Kenneth Kindsfater , Fang Lu
IPC分类号： H01F17/00 , H01L23/50 , H01L23/522 , H01L23/60 , H01L23/62 , H01L27/02 , H01L27/08 , H03B5/12 , H03B5/36 , H03D7/16 , H03D7/18 , H03G1/00 , H03H11/12 , H03J1/00 , H03J3/04 , H03J3/08 , H03J3/18 , H03L7/10 , H03L7/23 , H04B1/28
CPC分类号： H01L23/50 , H01F17/0006 , H01F17/0013 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L23/60 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B5/364 , H03D7/161 , H03D7/18 , H03G1/0029 , H03H11/1291 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/23 , H04B1/28 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.
摘要翻译：描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。接收机前端提供可编程衰减和可编程增益低噪声放大器。频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。过滤器调谐和电感Q补偿温度在芯片上执行。滤波器采用多轨螺旋电感。使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。结合滤波，频率规划提供了额外的镜像抑制。片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。差分晶体振荡器有利地用作频率参考。差分信号传输有利地用于整个接收机。 ESD保护由保护信号完整性的焊盘环和ESD钳位结构提供。还提供每个引脚上的分流器，以放电ESD积聚。分流器利用栅极升压结构来提供足够的小信号RF性能和最小的寄生负载。

80. 发明授权

US06445039B1 System and method for ESD Protection 有权
标题翻译： ESD保护的系统和方法
公开(公告)号：US06445039B1
公开(公告)日：2002-09-03
申请号：US09483551
申请日：2000-01-14
申请人： Agnes N. Woo , Kenneth R. Kindsfater , Fang Lu
发明人： Agnes N. Woo , Kenneth R. Kindsfater , Fang Lu
IPC分类号： H01L2972
CPC分类号： H01L23/50 , H01F17/0006 , H01F17/0013 , H01F2017/0053 , H01F2021/125 , H01L23/5227 , H01L23/60 , H01L27/0248 , H01L27/0251 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B5/364 , H03D7/161 , H03D7/18 , H03G1/0029 , H03H11/1291 , H03J1/0075 , H03J3/04 , H03J3/08 , H03J3/185 , H03J2200/10 , H03L7/10 , H03L7/23 , H04B1/28 , H01L2924/00
摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.
摘要翻译：描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。接收机前端提供可编程衰减和可编程增益低噪声放大器。频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。过滤器调谐和电感Q补偿温度在芯片上执行。滤波器采用多轨螺旋电感。使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。结合滤波，频率规划提供了额外的镜像抑制。片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。差分晶体振荡器有利地用作频率参考。差分信号传输有利地用于整个接收机。 ESD保护由保护信号完整性的焊盘环和ESD钳位结构提供。还提供每个引脚上的分流器，以放电ESD积聚。分流器利用栅极升压结构来提供足够的小信号RF性能和最小的寄生负载。

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