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71. 发明申请

US20090140863A1 COMPUTING DEVICE THAT DETECTS HAND PRESENCE IN ORDER TO AUTOMATE THE TRANSITION OF STATES 有权
标题翻译：检测出自动过渡状态的计算机设备
公开(公告)号：US20090140863A1
公开(公告)日：2009-06-04
申请号：US11948934
申请日：2007-11-30
申请人： Eric Liu , Sagar Savant , Peter Sobczak , Charles Lee , Peter Skillman
发明人： Eric Liu , Sagar Savant , Peter Sobczak , Charles Lee , Peter Skillman
IPC分类号： G08B23/00
CPC分类号： G06F1/3203 , G06F1/1626 , G06F1/3231 , H04M1/72563 , H04M2250/12 , H04M2250/22 , Y02D10/173
摘要： A computing device is configured to make a determination as to whether a device is being held in a hand. In response to determining that the device is being held, the device transitions itself, or one or more of its hardware or software component, into a particular state of operation.
摘要翻译：计算设备被配置为确定设备是否被握在手中。响应于确定设备被保持，设备将其自身或其硬件或软件组件中的一个或多个转换为特定操作状态。

72. 发明申请

US20080098164A1 SRAM Cache & Flash Micro-Controller with Differential Packet Interface 失效
标题翻译：具有差分数据包接口的SRAM缓存和闪存微控制器
公开(公告)号：US20080098164A1
公开(公告)日：2008-04-24
申请号：US11876251
申请日：2007-10-22
申请人： Charles Lee , David Chow , Abraham Ma , Frank Yu , Ming-Shiang Shen
发明人： Charles Lee , David Chow , Abraham Ma , Frank Yu , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F12/0866 , G06F2212/2022 , G06F2212/2515
摘要： A flash microcontroller has a Static Random-Access-Memory (SRAM) buffer that stores several blocks of boot code read from a flash memory. The SRAM buffer also operates as a cache of flash data after booting is complete. Cache read and write hits use the SRAM cache rather than flash memory, while old cache lines and read misses access the flash memory. Both the external host and the microcontroller are booted from boot code buffered in the SRAM buffer. A boot-loader state machine reads the flash ID and programs flash parameter registers with timing parameters for the flash memory. The flash microcontroller uses a differential interface to the external host, with a differential transceiver and a differential serial interface. Frame, packet, and encoded clock processing is also performed by the serial interface.
摘要翻译：闪存微控制器具有静态随机存取存储器（SRAM）缓冲器，其存储从闪存读取的几个引导代码块。引导完成后，SRAM缓冲区还可以作为闪存数据缓存。缓存读取和写入命中使用SRAM缓存而不是闪存，而旧的缓存行和读取未命中访问闪存。外部主机和微控制器均由缓冲在SRAM缓冲区中的引导代码引导。引导加载器状态机读取闪存ID，并使用Flash存储器的时序参数对闪存参数寄存器进行编程。闪存单片机使用与外部主机的差分接口，具有差分收发器和差分串行接口。帧，分组和编码时钟处理也由串行接口执行。

73. 发明申请

US20080071963A1 Express card with extended USB interface 审中-公开
标题翻译：具有扩展USB接口的Express卡
公开(公告)号：US20080071963A1
公开(公告)日：2008-03-20
申请号：US11979103
申请日：2007-10-31
申请人： David Chow , Sidney Young , Charles Lee , Abraham Ma , Ming-Shiang Shen
发明人： David Chow , Sidney Young , Charles Lee , Abraham Ma , Ming-Shiang Shen
IPC分类号： G06F13/20 , G06F12/02
CPC分类号： G06F13/409 , G06F2213/0026 , G06F2213/0042 , Y02D10/14 , Y02D10/151
摘要： An ExpressCard having USB connection has a card case having two opposite first and second end portions and two opposite lateral portions. A card connector is formed at the first end portion of the card case and having a USB interface. Flash chips are implemented in the card case. A USB flash controller implemented in the card case and connected between the USB interface and the flash chips in order to provide a data access to the flash chips through the USB interface. A USB socket, in form factors of Mini-USB or Extended Mini-connector-type, is implemented in the card case and connected to the USB flash controller in order to provide a data access to the one or more flash chips therethrough. An extended Universal-Serial Bus (EUSB) host enters a suspend mode rather than poll an ExpressCard that is busy performing a memory or other operation, thereby saving power.
摘要翻译：具有USB连接的ExpressCard具有具有两个相对的第一和第二端部和两个相对的横向部分的卡盒。卡连接器形成在卡盒的第一端部并且具有USB接口。闪存芯片在卡盒中实现。 USB闪存控制器实现在卡盒中并连接在USB接口和闪存芯片之间，以通过USB接口提供对闪存芯片的数据访问。一个USB插座，以Mini-USB或扩展迷你连接器类型的形式被实现在卡盒中并连接到USB闪存控制器，以便提供对一个或多个闪存芯片的数据访问。扩展的通用串行总线（EUSB）主机进入挂起模式，而不是轮询正忙于执行内存或其他操作的ExpressCard，从而节省电量。

74. 发明申请

US20080065794A1 Chained DMA for Low-Power Extended USB Flash Device Without Polling 失效
标题翻译：用于低功耗扩展USB闪存设备的链接DMA，无轮询
公开(公告)号：US20080065794A1
公开(公告)日：2008-03-13
申请号：US11928124
申请日：2007-10-30
申请人： Charles Lee , David Chow , Abraham Ma , Frank Yu , Ming-Shiang Shen , Horng-Yee Chou
发明人： Charles Lee , David Chow , Abraham Ma , Frank Yu , Ming-Shiang Shen , Horng-Yee Chou
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , Y02D10/14
摘要： An extended Universal-Serial Bus (EUSB) host has reduced loading by using radio frequency (RF) transceivers or direct wiring traces rather than a pair of legacy USB cables. The reduced loading opens the eye pattern. The EUSB device transfers internal data using chained Direct-Memory Access (DMA). Registers in a DMA controller point to a vector table that has vector entries, each pointing to a destination and a source. The source is a memory table for a memory group. The memory table has entries for several memory segments. Each memory-table entry has a pointer to a memory segment and a byte count for the segment. Once all bytes in the segment are transferred, a flag in the entry indicates when another memory segment follows within the memory group. When an END flag is read, then vector table is advanced to the next vector entry, and another memory group of memory segments processed.
摘要翻译：扩展的通用串行总线（EUSB）主机通过使用射频（RF）收发器或直接布线轨迹而不是一对传统的USB电缆减少了负载。减少负荷打开眼睛图案。 EUSB设备使用链接的直接内存访问（DMA）传输内部数据。 DMA控制器中的寄存器指向具有向量条目的向量表，每个向量表指向一个目的地和一个源。源是内存组的内存表。内存表有几个内存段的条目。每个存储表条目具有指向存储器段的指针和段的字节计数。一旦片段中的所有字节都被传送，该条目中的标志表示在存储器组中跟随其他内存段的时间。读取END标志时，向量表前进到下一个向量条目，并处理另一个内存段的内存组。

75. 发明申请

US20080046608A1 Low-Power Extended USB Flash Device Without Polling 审中-公开
标题翻译：低功耗扩展USB闪存设备，无轮询
公开(公告)号：US20080046608A1
公开(公告)日：2008-02-21
申请号：US11925933
申请日：2007-10-27
申请人： Charles Lee , David Chow , Abraham Ma , Frank Yu , Ming-Shiang Shen , Horng-Yee Chou
发明人： Charles Lee , David Chow , Abraham Ma , Frank Yu , Ming-Shiang Shen , Horng-Yee Chou
IPC分类号： G06F3/00
CPC分类号： G06F13/4045 , Y02D10/14 , Y02D10/151
摘要： An extended Universal-Serial Bus (EUSB) host enters a suspend mode rather than poll an EUSB device that is busy performing a memory or other operation. Power is saved since polling is avoided. The busy EUSB device sends a not-yet NYET signal back to the EUSB host to instruct the host to enter the suspend mode. When the EUSB device is ready to continue transfer with the host, the EUSB device wakes up the host by sending a ready RDY signal back to the host. The NYET and RDY signals may be tokens or flags in serial packets sent over a full-duplex connection to the host with two sets of differential pairs. Transfers may be re-started by the host after suspension once the requested data is read from flash memory, or space is made available in a sector buffer by completing earlier writes to flash memory.
摘要翻译：扩展的通用串行总线（EUSB）主机进入暂停模式，而不是轮询正忙于执行内存或其他操作的EUSB设备。省电，因为避免轮询。繁忙的EUSB设备向EUSB主机发送一个尚未发送的NYET信号，指示主机进入挂起模式。当EUSB设备准备好继续与主机进行传输时，EUSB设备通过将准备好的RDY信号发送回主机来唤醒主机。 NYET和RDY信号可以是通过全双工连接发送到具有两组差分对的主机的串行数据包中的令牌或标志。一旦所请求的数据从闪存中读取，主机可以重新启动传输，或者通过完成对闪存的更早写入，在扇区缓冲器中可用空间。

76. 发明申请

US20080037321A1 Partial-Write-Collector Algorithm for Multi Level Cell (MLC) Flash 有权
标题翻译：用于多级单元（MLC）闪存的部分写入 - 收集器算法
公开(公告)号：US20080037321A1
公开(公告)日：2008-02-14
申请号：US11774906
申请日：2007-07-09
申请人： Jianjun Luo , Chris Tsu , Charles Lee , David Chow
发明人： Jianjun Luo , Chris Tsu , Charles Lee , David Chow
IPC分类号： G11C16/06
CPC分类号： G11C16/102 , G06F8/65 , G11C2211/5641
摘要： A flash memory system includes a multi level cell (MLC) flash memory organized into blocks and having pages of information, which has data and spare. The MLC flash memory includes at least a temporary area to store at least a portion of a page of information during a partial write operation. The MLC flash memory stores a page of information into a block identified by a target physical address. The flash memory system further includes a flash card micro-controller causes communication between a host flash card controller and the MLC flash memory and includes a buffer memory configured to store a portion of a page of information, where the micro-controller writes the at least a portion of a page of information to the temporary area and later copies the written at least a portion of a page of information into the block identified by a target physical address.
摘要翻译：闪存系统包括组织成块并具有数据和备用的信息页的多级单元（MLC）闪存。在部分写入操作期间，MLC闪速存储器至少包括用于存储信息页的至少一部分的临时区域。 MLC闪速存储器将一页信息存储到由目标物理地址识别的块中。闪存系统还包括闪存卡微控制器引起主机闪存卡控制器和MLC闪速存储器之间的通信，并且包括被配置为存储信息页的一部分的缓冲存储器，其中微控制器写入至少信息页面的一部分到临时区域，并且稍后将写入信息页的至少一部分复制到由目标物理地址识别的块中。

77. 发明申请

US20070274032A1 Thin Flash-Hard-Drive with Two-Piece Casing 失效
标题翻译：薄型闪存硬盘驱动器与两件式外壳
公开(公告)号：US20070274032A1
公开(公告)日：2007-11-29
申请号：US11309843
申请日：2006-10-11
申请人： Jim Ni , Abraham Ma , Charles Lee , Ming-Shiang Shen
发明人： Jim Ni , Abraham Ma , Charles Lee , Ming-Shiang Shen
IPC分类号： H05K7/12 , H01L21/00
CPC分类号： H05K5/0269
摘要： A flash-memory drive replaces a hard-disk drive using an integrated device electronics (IDE) interface. The flash drive has a printed-circuit board assembly (PCBA) with a circuit board with flash-memory chips and a controller chip. The controller chip includes an input/output interface circuit to an external computer over the IDE interface, and a processing unit to read blocks of data from the flash-memory chips. The PCBA is encased inside an upper case and a lower case, with an IDE connector that fits through and opening between the cases. The cases can be assembled with the PCBA by a snap-together, ultrasonic-press, screw-fastener, or thermal-bond adhesive method. Center lines formed on the inside of the cases fit between rows of flash-memory chips to improve case rigidity. The connector has two rows of pins that straddle the center line of the circuit board for a balanced design.
摘要翻译：闪存驱动器使用集成设备电子（IDE）接口替换硬盘驱动器。闪存驱动器具有带有闪存芯片的电路板和控制器芯片的印刷电路板组件（PCBA）。控制器芯片包括通过IDE接口连接到外部计算机的输入/输出接口电路，以及从闪速存储器芯片读取数据块的处理单元。 PCBA被封装在上壳体和下壳体内，并具有适合通过壳体和壳体之间打开的IDE连接器。这些情况可以通过卡扣，超声波压力机，螺纹紧固件或热粘合粘合剂方法与PCBA组装。形成在壳体内部的中心线适配在闪存芯片的行之间，以提高外壳刚度。连接器具有跨越电路板中心线的两排销，用于平衡设计。

78. 发明申请

US20070192863A1 SYSTEMS AND METHODS FOR PROCESSING DATA FLOWS 审中-公开
标题翻译：用于处理数据流的系统和方法
公开(公告)号：US20070192863A1
公开(公告)日：2007-08-16
申请号：US11610296
申请日：2006-12-13
申请人： Harsh Kapoor , Moisey Akerman , Stephen Justus , JC Ferguson , Yevgeny Korsunsky , Paul Gallo , Charles Lee , Timothy Martin , Chunsheng Fu , Weidong Xu
发明人： Harsh Kapoor , Moisey Akerman , Stephen Justus , JC Ferguson , Yevgeny Korsunsky , Paul Gallo , Charles Lee , Timothy Martin , Chunsheng Fu , Weidong Xu
IPC分类号： G06F12/14
CPC分类号： G06N3/0472 , G06F9/505 , G06F21/55 , G06F21/577 , H04L29/06 , H04L63/0227 , H04L63/1408 , H04L63/1416 , H04L63/1425 , H04L63/1441 , H04L63/145 , H04L63/1483 , H04L63/164 , H04L63/166 , H04L67/10 , H04L67/306 , H04L67/325 , H04L67/327 , H04L67/34 , H04L69/329 , H04L2463/141
摘要： A flow processing facility, which uses a set of artificial neurons for pattern recognition, such as a self-organizing map, in order to provide security and protection to a computer or computer system supports unified threat management based at least in part on patterns relevant to a variety of types of threats that relate to computer systems, including computer networks. Flow processing for switching, security, and other network applications, including a facility that processes a data flow to address patterns relevant to a variety of conditions are directed at internal network security, virtualization, and web connection security. A flow processing facility for inspecting payloads of network traffic packets detects security threats and intrusions across accessible layers of the IP-stack by applying content matching and behavioral anomaly detection techniques based on regular expression matching and self-organizing maps. Exposing threats and intrusions within packet payload at or near real-time rates enhances network security from both external and internal sources while ensuring security policy is rigorously applied to data and system resources. Intrusion Detection and Protection (IDP) is provided by a flow processing facility that processes a data flow to address patterns relevant to a variety of types of network and data integrity threats that relate to computer systems, including computer networks.
摘要翻译：使用一组用于模式识别的人造神经元（例如自组织图）以便向计算机或计算机系统提供安全性和保护的流程处理设备至少部分地基于与与计算机系统（包括计算机网络）相关的各种类型的威胁。用于交换，安全和其他网络应用的流处理，包括处理数据流以处理与各种条件相关的模式的设施，针对内部网络安全性，虚拟化和Web连接安全性。用于检查网络流量包的有效载荷的流处理设备通过应用基于正则表达式匹配和自组织映射的内容匹配和行为异常检测技术来检测IP堆栈的可访问层的安全威胁和入侵。在实时速率或接近实时速率的情况下，在数据包有效载荷中暴露威胁和入侵，从而确保安全策略严格应用于数据和系统资源，从而提高了外部和内部来源的网络安全性。入侵检测和保护（IDP）由处理数据流的流处理设备提供，以处理与包括计算机网络在内的计算机系统相关的各种类型的网络和数据完整性威胁相关的模式。

79. 发明申请

US20070168614A1 Secure-Digital (SD) Flash Card with Auto-Adaptive Protocol and Capacity 审中-公开
标题翻译：具有自适应协议和容量的安全数字（SD）闪存卡
公开(公告)号：US20070168614A1
公开(公告)日：2007-07-19
申请号：US11625310
申请日：2007-01-20
申请人： Jianjun Luo , Chris Tsu , Charles Lee , Ming-Shiang Shen
发明人： Jianjun Luo , Chris Tsu , Charles Lee , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F13/385
摘要： An adaptable-capacity Secure Digital (SD) card operates as a standard-capacity SD card for a standard-capacity SD 2.0 or 1.x host, and operates as a high-capacity SD card when connected to a high-capacity SD 2.0 host. A 32-bit argument received in a SD bus transaction from the host may be a 32-bit address, which can access 4 G bytes of flash memory in standard-capacity mode. For high-capacity mode, the addressable unit is a 512-byte sector, greatly increasing the addressable memory size. A SD protocol interface on a controller chip performs handshaking with the host to determine the SD version and memory capacity of the host. Host addresses are sent as byte or sector addresses to a flash memory manager on the controller chip, depending on the capacity mode agreed on during the handshaking. Memory areas on the adaptable-capacity SD card for high and standard modes can be separate or overlapping.
摘要翻译：适用于容量的安全数字（SD）卡作为标准容量SD 2.0或1.x主机的标准容量SD卡运行，并连接到大容量SD 2.0主机时作为高容量SD卡运行。来自主机的SD总线事务中接收到的32位参数可以是32位地址，可以在标准容量模式下访问4 G字节的闪存。对于高容量模式，可寻址单元是一个512字节的扇区，大大增加了可寻址的存储器大小。控制器芯片上的SD协议接口与主机执行握手，以确定主机的SD版本和内存容量。主机地址作为字节或扇区地址发送到控制器芯片上的闪存管理器，这取决于握手期间商定的容量模式。适用于高容量SD卡的存储区域可以分开或重叠。

80. 发明申请

US20070147157A1 Flash Card and Controller with Integrated Voltage Converter for Attachment to a Bus that can Operate at Either of Two Power-Supply Voltages 失效
标题翻译：具有集成电压转换器的闪存卡和控制器，用于连接到可以在两个电源电压两者中工作的总线
公开(公告)号：US20070147157A1
公开(公告)日：2007-06-28
申请号：US11625309
申请日：2007-01-20
申请人： Jianjun Luo , Chris Tsu , Charles Lee , Ming-Shiang Shen
发明人： Jianjun Luo , Chris Tsu , Charles Lee , Ming-Shiang Shen
IPC分类号： G11C5/14
CPC分类号： G11C5/143 , G11C5/147 , G11C16/30
摘要： A dual-voltage secure digital (SD) card can be inserted into a legacy host or a newer host. Legacy hosts drive a high voltage such as 3.3 volts onto the power line of the SD bus, while newer hosts drive the power line with a reduced voltage such as 1.8 volts. A flash and voltage controller chip on the SD card has a controller core that operates at the reduced voltage. A voltage regulator on the SD card, or a power management unit inside the controller chip generates an internal power voltage of 1.8 volts from the dual-voltage SD bus power line. The internal power voltage is applied to the controller core and to a voltage converter that generates a flash power voltage from the internal power voltage. The flash power voltage is applied to flash-memory chips on the SD card that operate at the higher voltage.
摘要翻译：可以将双电压安全数字（SD）卡插入到旧式主机或更新的主机中。传统主机将高压（例如3.3伏特）驱动到SD总线的电源线上，而较新的主机则以1.8伏特的降低电压驱动电源线。 SD卡上的闪存和电压控制器芯片具有以降低的电压工作的控制器核心。 SD卡上的电压调节器或控制器芯片内的电源管理单元从双电压SD总线电源线产生1.8伏特的内部电源电压。内部电源电压被施加到控制器核心和电压转换器，其从内部电源电压产生闪光电源电压。闪存电源电压被施加到在更高电压下工作的SD卡上的闪存芯片。

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