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71. 发明授权

US07649173B2 Method of preparing a sample for transmission electron microscopy 有权
标题翻译：制备透射电子显微镜样品的方法
公开(公告)号：US07649173B2
公开(公告)日：2010-01-19
申请号：US11618728
申请日：2006-12-29
申请人： Jianqiang Hu , Zhixian Rui , Yanli Zhao , Yanjun Wang , Ming Li , Min Pan
发明人： Jianqiang Hu , Zhixian Rui , Yanli Zhao , Yanjun Wang , Ming Li , Min Pan
IPC分类号： G01N23/00 , G21K7/00
CPC分类号： G01N1/32
摘要： A method for preparing TEM sample, comprising the following steps: providing a sample with two pits and a failure region between the two pits, the failure region comprising a semiconductor device; milling the first surface of the failure region, till the cross section of the semiconductor device is exposed; etching the first surface of the failure region; cleaning the sample; milling the second surface of the failure region, till the failure region can be passed by electron beam. A sample can be prepared for a high resolution TEM through above steps. When the sample is observed, it is easy to distinguish the lightly doped drain, source/drain regions from the silicon substrate and observe the pattern and defects in the lightly doped drain, source/drain regions clearly; in addition, it is easy to distinguish the BPSG from the non-doped silicon dioxide in the failure region.
摘要翻译：一种制备TEM样品的方法，包括以下步骤：提供具有两个凹坑的样品和两个凹坑之间的失效区域，所述失效区域包括半导体器件; 铣削故障区域的第一表面，直到半导体器件的横截面露出; 蚀刻失效区域的第一表面; 清洗样品; 铣削失效区域的第二表面，直到失效区域可以通过电子束。可以通过上述步骤制备用于高分辨率TEM的样品。当观察样品时，很容易区分轻掺杂漏极，源极/漏极区域与硅衬底，并清楚地观察到轻掺杂漏极，源极/漏极区域中的图案和缺陷; 此外，在故障区域中容易区分BPSG和非掺杂二氧化硅。

72. 发明申请

US20090305440A1 Method for Treatment of Samples for Auger Electronic Spectrometer (AES) in the Manufacture of Integrated Circuits 有权
标题翻译：用于俄罗斯电子光谱仪（AES）在集成电路制造中的处理方法
公开(公告)号：US20090305440A1
公开(公告)日：2009-12-10
申请号：US12364977
申请日：2009-02-03
申请人： Qi Hau Zhang , Ming Li , Chorng Shyr Niou , Scott Liao
发明人： Qi Hau Zhang , Ming Li , Chorng Shyr Niou , Scott Liao
IPC分类号： H01L21/66 , C23C14/34
CPC分类号： G01N23/2276 , H01L22/12
摘要： A method for analyzing a sample for the manufacture of integrated circuits, e.g. MOS transistors, application specific integrated circuits, memory devices, microprocessors, system on a chip. The method includes providing an integrated circuit chip, which has a surface area with at least one region of interest, e.g., bond pad. The method includes covering a first portion of the surface area including the region of interest using a blocking material. The method also forms a metal layer on a second portion of the surface area, while the blocking material protects the first portion. The method removes the blocking material to expose the first portion of the surface area including the region of interest. The method also subjects the metal layer to a voltage differential to draw away one or more charged particles from the first portion of the surface area. The method also subjects the surface area including the region of interest to spectrometer analysis.
摘要翻译：用于分析用于制造集成电路的样品的方法，例如， MOS晶体管，专用集成电路，存储器件，微处理器，片上系统。该方法包括提供集成电路芯片，其具有至少一个感兴趣区域的表面区域，例如接合焊盘。该方法包括使用阻挡材料覆盖包括感兴趣区域的表面区域的第一部分。该方法还在表面区域的第二部分上形成金属层，而阻挡材料保护第一部分。该方法去除阻挡材料以暴露包括感兴趣区域的表面区域的第一部分。该方法还使金属层进行电压差以从表面区域的第一部分抽出一个或多个带电粒子。该方法还将包括感兴趣区域的表面区域进行光谱仪分析。

73. 发明申请

US20090275177A1 SEMICONDUCTOR DEVICE WITH MULTIPLE CHANNELS AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有多个通道的半导体器件及其制造方法
公开(公告)号：US20090275177A1
公开(公告)日：2009-11-05
申请号：US12503594
申请日：2009-07-15
申请人： Ming Li , Kyoung-hwan Yeo , Sung-min Kim , Sung-dae Suk , Dong-won Kim
发明人： Ming Li , Kyoung-hwan Yeo , Sung-min Kim , Sung-dae Suk , Dong-won Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/78696 , H01L29/1083 , H01L29/66787
摘要： A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.
摘要翻译：具有多个通道的半导体器件包括半导体衬底和在半导体衬底上彼此间隔开并且具有彼此面对的侧壁的一对导电区域。在导电区域之间的半导体衬底上设置有部分绝缘层。至少两个桥的形式的沟道层接触部分绝缘层，所述至少两个桥在第一方向上彼此间隔开，并且在与第一方向相反的第二方向上将导电区彼此连接到第一个方向。栅极绝缘层在沟道层上，栅极电极层在栅极绝缘层上并围绕沟道层的一部分。

74. 发明申请

US20090158457A1 SPECIFIC EXPRESSION USING TRANSCRIPTIONAL CONTROL SEQUENCES IN PLANTS 有权
标题翻译：在植物中使用转录控制序列的特异性表达
公开(公告)号：US20090158457A1
公开(公告)日：2009-06-18
申请号：US12091401
申请日：2006-10-27
申请人： Sergiy Lopato , Ming Li
发明人： Sergiy Lopato , Ming Li
IPC分类号： C12N15/82 , A01H5/00 , C12N15/11 , C12N5/04
CPC分类号： C07K14/415 , C12N15/8234
摘要： The present invention relates generally to methods and transcriptional control sequences suitable for effecting expression of a nucleotide sequence of interest in a plant. More particularly, the present invention relates to methods and transcriptional control sequences suitable for directing specific or preferential expression of a nucleotide sequence of interest in a plant seed. Of particular interest as a transcriptional control sequence in this invention is the promoter PR602 (SEQ ID NO: 1) found in the 5′-untranslated region of the rice END1-like gene and isolated from a rice panicle library.
摘要翻译：本发明一般涉及适于在植物中实现感兴趣的核苷酸序列的表达的方法和转录调控序列。更具体地说，本发明涉及适于指导在植物种子中感兴趣的核苷酸序列的特异性或优先表达的方法和转录调控序列。在本发明中作为转录控制序列特别感兴趣的是在水稻END1样基因的5'-非翻译区中发现并从稻穗文库中分离的启动子PR602（SEQ ID NO：1）。

75. 发明申请

US20090090952A1 PLASMA SURFACE TREATMENT FOR SI AND METAL NANOCRYSTAL NUCLEATION 有权
标题翻译：用于SI和金属纳米晶核的等离子体表面处理
公开(公告)号：US20090090952A1
公开(公告)日：2009-04-09
申请号：US11866625
申请日：2007-10-03
申请人： Christopher S. Olsen , Sean Seutter , Ming Li , Phillip Allan Kraus
发明人： Christopher S. Olsen , Sean Seutter , Ming Li , Phillip Allan Kraus
IPC分类号： H01L29/00 , H01L21/3205 , H01L29/76
CPC分类号： H01L29/42332 , H01L21/28273 , H01L21/6719
摘要： A device, such as a nonvolatile memory device, and methods for forming the device in an integrated process tool are provided. The method includes depositing a tunnel oxide layer on a substrate, exposing the tunnel oxide layer to a plasma so that the plasma alters a morphology of a surface and near surface of the tunnel oxide to form a plasma altered near surface. Nanocrystals are then deposited on the altered surface of the tunnel oxide.
摘要翻译：提供了诸如非易失性存储器件的装置，以及用于在集成处理工具中形成装置的方法。该方法包括在衬底上沉积隧道氧化物层，将隧道氧化物层暴露于等离子体，使得等离子体改变隧道氧化物的表面和近表面的形态以形成等离子体改变的近表面。然后将纳米晶体沉积在隧道氧化物的改变的表面上。

76. 发明授权

US07486443B1 High extinction ratio and low crosstalk compact optical switches 有权
标题翻译：高消光比和低串扰紧凑型光开关
公开(公告)号：US07486443B1
公开(公告)日：2009-02-03
申请号：US10224748
申请日：2002-08-20
申请人： Ming Li , Song Peng
发明人： Ming Li , Song Peng
IPC分类号： G02B5/30 , G02B27/28
CPC分类号： H04Q11/0005 , G02B6/272 , H04Q2011/0024 , H04Q2011/0026 , H04Q2011/0035
摘要： An improved optical switch utilizes one polarization modulator, with the beam components traversing it twice. Because of the twice traverse, the extinction ratio of the switch is doubled without the addition of another polarization modulator, thus avoiding the costs of additional optical components. With no additional components, the switch is more compact than conventional switches with the same extinction ratio. Fewer components also result in more thermal and long-term stability and less crosstalk.
摘要翻译：改进的光开关利用一个偏振调制器，光束分量穿过它两次。由于两次横移，所以开关的消光比加倍而不增加另一个偏振调制器，从而避免了额外的光学元件的成本。没有附加组件，开关比具有相同消光比的常规开关更紧凑。更少的组件也导致更多的热和长期稳定性和更少的串扰。

77. 发明申请

US20090016344A1 METHOD AND APPARATUS FOR CONTROLLING BEARERS OF SERVICE DATA FLOWS 审中-公开
标题翻译：用于控制服务数据流的轴承的方法和装置
公开(公告)号：US20090016344A1
公开(公告)日：2009-01-15
申请号：US12236860
申请日：2008-09-24
申请人： Huadong Hu , Xiaoqin Duan , Chengzhen Sun , Lan Liu , Ming Li
发明人： Huadong Hu , Xiaoqin Duan , Chengzhen Sun , Lan Liu , Ming Li
IPC分类号： H04L12/56
CPC分类号： H04L47/41 , H04W28/0263 , H04W28/0268 , H04W76/15 , H04W76/22 , H04W80/04
摘要： Embodiments of the present invention provide a method and apparatus for controlling bearers of service data flows, including acquiring a service data flow convergence of service data flows, determining whether the service data flow convergence is able to be multiplexed to an established bearer, and carrying the service data flow convergence in a corresponding bearer according to the determined result. The apparatus of the present invention includes a service data flow convergence acquiring module and a service data flow convergence multiplex handling module for implementing the method of the present invention. In accordance with the method and apparatus of the present invention, it is possible to reduce the bearer information amount necessary to be maintained by various network entities and save the storage and handling resources of system.
摘要翻译：本发明的实施例提供一种用于控制服务数据流的承载的方法和装置，包括获取业务数据流的业务数据流收敛，确定业务数据流收敛能否被复用到已建立的承载，并携带服务数据流根据确定的结果在对应的承载中收敛。本发明的装置包括实现本发明的方法的业务数据流收敛模块和业务数据流收敛多路复用处理模块。根据本发明的方法和装置，可以减少由各种网络实体维护的承载信息量，并节省系统的存储和处理资源。

78. 发明申请

US20080233701A1 Methods of Forming Integrated Circuit Devices Including a Depletion Barrier Layer at Source/Drain Regions 有权
标题翻译：形成集成电路器件的方法包括在源极/漏极区域的耗尽屏障层
公开(公告)号：US20080233701A1
公开(公告)日：2008-09-25
申请号：US12131437
申请日：2008-06-02
申请人： Ming Li
发明人： Ming Li
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L21/26586 , H01L29/0653 , H01L29/1083 , H01L29/41775 , H01L29/66545 , H01L29/66636
摘要： Integrated circuit devices include an integrated circuit substrate having a channel region therein. A gate pattern is disposed on a top surface of the channel region. A depletion barrier layer covers a surface of the integrated circuit substrate adjacent opposite sides of the gate pattern and extending along a portion of a lateral face of the channel region. A source/drain layer is disposed on the depletion barrier layer and electrically contacting the lateral face of the channel region in a region not covered by the depletion barrier layer. The channel region may protrude from a surface of the substrate. The depletion barrier layer may be an L-shaped depletion barrier layer and the device may further include a device isolation layer disposed at a predetermined portion of the substrate through the source/drain layer and the depletion barrier layer. The depletion barrier layer and the device isolation layer may be formed of the same material.
摘要翻译：集成电路器件包括其中具有沟道区的集成电路衬底。栅极图案设置在沟道区域的顶表面上。耗尽屏障层覆盖与栅极图案的相对侧相邻的集成电路基板的表面，并且沿沟道区域的侧面的一部分延伸。源极/漏极层设置在耗尽阻挡层上并与未被耗尽阻挡层覆盖的区域中的沟道区域的侧面电接触。沟道区域可以从衬底的表面突出。耗尽阻挡层可以是L形耗尽阻挡层，并且该器件还可以包括通过源/漏层和耗尽阻挡层设置在衬底的预定部分处的器件隔离层。耗尽阻挡层和器件隔离层可以由相同的材料形成。

79. 发明授权

US07427788B2 Multi bridge channel field effect transistors with nano-wire channels and methods of manufacturing the same 有权
标题翻译：具有纳米线通道的多桥通道场效应晶体管及其制造方法相同
公开(公告)号：US07427788B2
公开(公告)日：2008-09-23
申请号：US11259473
申请日：2005-10-26
申请人： Ming Li , Sung-min Kim
发明人： Ming Li , Sung-min Kim
IPC分类号： H01L29/80
CPC分类号： H01L29/78696 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/1029 , H01L29/42392 , H01L29/66545 , H01L29/66772 , H01L29/78654
摘要： A field effect transistor (FET) includes spaced apart source and drain regions disposed on a substrate and at least one pair of elongate channel regions disposed on the substrate and extending in parallel between the source and drain regions. A gate insulating region surrounds the at least one pair of elongate channel regions, and a gate electrode surrounds the gate insulating region and the at least one pair of elongate channel regions. Support patterns may be interposed between the semiconductor substrate and the source and drain regions. The elongate channel regions may have sufficiently small cross-section to enable complete depletion thereof. For example, a width and a thickness of the elongate channel regions may be in a range from about 10 nanometers to about 20 nanometers. The elongate channel regions may have rounded cross-sections, e.g., each of the elongate channel regions may have an elliptical cross-section. The at least one pair of elongate channel regions may include a plurality of stacked pairs of elongate channel regions.
摘要翻译：场效应晶体管（FET）包括设置在衬底上的间隔开的源极和漏极区域以及设置在衬底上并在源区域和漏极区域之间并联延伸的至少一对细长沟道区域。栅极绝缘区域围绕至少一对细长沟道区域，并且栅极电极围绕栅极绝缘区域和至少一对细长沟道区域。支撑图案可以插入在半导体衬底和源极和漏极区之间。细长通道区域可以具有足够小的横截面以使其能够完全消耗。例如，细长沟道区的宽度和厚度可以在约10纳米至约20纳米的范围内。细长通道区域可以具有圆形横截面，例如每个细长通道区域可以具有椭圆形横截面。所述至少一对细长通道区域可以包括多个堆叠的细长通道区域对。

80. 发明授权

US07396730B2 Integrated circuit devices including an L-shaped depletion barrier layer adjacent opposite sides of a gate pattern and methods of forming the same 失效
标题翻译：集成电路器件包括邻近栅极图案的相对侧的L形耗尽阻挡层及其形成方法
公开(公告)号：US07396730B2
公开(公告)日：2008-07-08
申请号：US11000260
申请日：2004-11-30
申请人： Ming Li
发明人： Ming Li
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L21/26586 , H01L29/0653 , H01L29/1083 , H01L29/41775 , H01L29/66545 , H01L29/66636
摘要： Integrated circuit devices include an integrated circuit substrate having a channel region therein. A gate pattern is disposed on a top surface of the channel region. A depletion barrier layer covers a surface of the integrated circuit substrate adjacent opposite sides of the gate pattern and extending along a portion of a lateral face of the channel region. A source/drain layer is disposed on the depletion barrier layer and electrically contacting the lateral face of the channel region in a region not covered by the depletion barrier layer. The channel region may protrude from a surface of the substrate. The depletion barrier layer may be an L-shaped depletion barrier layer and the device may further include a device isolation layer disposed at a predetermined portion of the substrate through the source/drain layer and the depletion barrier layer. The depletion barrier layer and the device isolation layer may be formed of the same material.
摘要翻译：集成电路器件包括其中具有沟道区的集成电路衬底。栅极图案设置在沟道区域的顶表面上。耗尽屏障层覆盖与栅极图案的相对侧相邻的集成电路基板的表面，并且沿沟道区域的侧面的一部分延伸。源极/漏极层设置在耗尽阻挡层上并与未被耗尽阻挡层覆盖的区域中的沟道区域的侧面电接触。沟道区域可以从衬底的表面突出。耗尽阻挡层可以是L形耗尽势垒层，并且该器件还可以包括通过源/漏层和耗尽阻挡层设置在衬底的预定部分处的器件隔离层。耗尽阻挡层和器件隔离层可以由相同的材料形成。

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