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71. 发明申请

US20070210390A1 Method of making an isolation trench and resulting isolation trench 有权
标题翻译：制造隔离沟槽和产生的隔离沟槽的方法
公开(公告)号：US20070210390A1
公开(公告)日：2007-09-13
申请号：US11714220
申请日：2007-03-06
申请人： Sukesh Sandhu , Gurtej Sandhu
发明人： Sukesh Sandhu , Gurtej Sandhu
IPC分类号： H01L29/76
CPC分类号： H01L21/76232 , H01L21/76229
摘要： A method of forming and resulting isolation region, which allows for densification of an oxide layer in the isolation region. One exemplary embodiment of the method includes the steps of forming a first trench, forming an oxide layer on the bottom and sidewalls of the trench, forming nitride spacers on the lined trench, and thereafter etching the silicon beneath the first trench to form a second trench area. An oxide layer is then deposited to fill the second trench. Densificiation of the isolation region is possible because the silicon is covered with nitride, and therefore will not be oxidized. Light etches are then performed to etch the oxide and nitride spacer area in the first trench region. A conventional oxide fill process can then be implemented to complete the isolation region.
摘要翻译：形成和产生的隔离区域的方法，其允许隔离区域中的氧化物层致密化。该方法的一个示例性实施例包括以下步骤：形成第一沟槽，在沟槽的底部和侧壁上形成氧化物层，在衬里的沟槽上形成氮化物间隔物，之后蚀刻第一沟槽下方的硅以形成第二沟槽区。然后沉积氧化物层以填充第二沟槽。隔离区的密集是可能的，因为硅被氮化物覆盖，因此不会被氧化。然后进行光蚀刻以蚀刻第一沟槽区域中的氧化物和氮化物间隔物区域。然后可以实现常规氧化物填充过程以完成隔离区域。

72. 发明申请

US20070190463A1 METHOD TO ALIGN MASK PATTERNS 有权
标题翻译：对齐掩蔽图案的方法
公开(公告)号：US20070190463A1
公开(公告)日：2007-08-16
申请号：US11691192
申请日：2007-03-26
申请人： Gurtej Sandhu , Randal Chance , William Rericha
发明人： Gurtej Sandhu , Randal Chance , William Rericha
IPC分类号： G03C5/00
CPC分类号： H01L23/50 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L27/1052 , H01L27/10894 , H01L2924/0002 , Y10S438/95 , Y10S438/975 , H01L2924/00
摘要： Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pitch multiplication and the wider mask lines are formed by photolithography. The wider mask lines and are aligned so that one side of those lines is flush with or inset from a corresponding side of the narrow lines. Being wider, the opposite sides of the wider mask lines protrude beyond the corresponding opposite sides of the narrow mask lines. The wider mask lines are formed in negative photoresist having a height less than the height of the narrow mask lines. Advantageously, the narrow mask lines can prevent expansion of the mask lines in one direction, thus increasing alignment tolerances in that direction. In the other direction, use of photolithography and a shadowing effect caused by the relative heights of the photoresist and the narrow mask lines causes the wider mask lines to be formed with a rounded corner, thus increasing alignment tolerances in that direction by increasing the distance to a neighboring narrow mask line.
摘要翻译：在集成电路的阵列区域中用于形成互连的窄掩模线之间的对准公差和用于在集成电路的外围形成互连的较宽的掩模线增加。通过间距倍增形成窄屏蔽线，通过光刻法形成较宽的掩模线。较宽的掩模线对准，使得这些线的一侧与窄线的相应侧齐平或嵌入。较宽的掩模线的相对侧突出超过窄掩模线的对应的相对侧。较宽的掩模线形成在具有小于窄掩模线的高度的高度的负光致抗蚀剂中。有利地，窄掩模线可以防止掩模线在一个方向上的膨胀，从而增加该方向上的对准公差。在另一个方向上，使用光刻法和由光致抗蚀剂和窄掩模线的相对高度引起的阴影效应导致较宽的掩模线形成有圆角，从而通过增加到该方向的距离来增加该方向上的对准公差相邻的窄屏线。

73. 发明申请

US20070161251A1 PITCH REDUCED PATTERNS RELATIVE TO PHOTOLITHOGRAPHY FEATURES 失效
标题翻译：相对于光刻特征的PITCH减少图案
公开(公告)号：US20070161251A1
公开(公告)日：2007-07-12
申请号：US11681027
申请日：2007-03-01
申请人： Luan Tran , William Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi Bai , Zhiping Yin , Paul Morgan , Mirzafer Abatchev , Gurtej Sandhu , D. Durcan
发明人： Luan Tran , William Rericha , John Lee , Ramakanth Alapati , Sheron Honarkhah , Shuang Meng , Puneet Sharma , Jingyi Bai , Zhiping Yin , Paul Morgan , Mirzafer Abatchev , Gurtej Sandhu , D. Durcan
IPC分类号： H01L21/302
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/3086 , H01L21/3088
摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.
摘要翻译：通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。间距乘法用于形成第一图案的相对较小的特征以及用于形成第二图案的较大特征的常规光刻。间距倍增通过对光致抗蚀剂进行图案化，然后将该图案蚀刻成无定形碳层来实现。然后在无定形碳的侧壁上形成侧壁间隔物。去除无定形碳，留下限定第一掩模图案的侧壁间隔物。然后将底部抗反射涂层（BARC）沉积在间隔物周围以形成平坦表面，并且在BARC上形成光致抗蚀剂层。接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，然后将其转印到BARC。通过第一图案和第二图案形成的组合图案被转印到下面的非晶硅层，并且图案经受碳带以去除BARC和光致抗蚀剂材料。然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。具有不同尺寸特征的组合掩模图案然后通过无定形碳硬掩模层蚀刻到下面的衬底中。

74. 发明申请

US20070148984A1 METHOD FOR INTEGRATED CIRCUIT FABRICATION USING PITCH MULTIPLICATION 失效
标题翻译：使用PITCH MULTIPLICATION的集成电路制造方法
公开(公告)号：US20070148984A1
公开(公告)日：2007-06-28
申请号：US11683518
申请日：2007-03-08
申请人： Mirzafer Abatchev , Gurtej Sandhu , Luan Tran , William Rericha , D. Durcan
发明人： Mirzafer Abatchev , Gurtej Sandhu , Luan Tran , William Rericha , D. Durcan
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/0337 , H01L21/0332 , H01L21/0338 , H01L21/3081 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/32139 , Y10S438/947 , Y10S438/95
摘要： Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.
摘要翻译：集成电路的阵列和周边中的不同尺寸的特征在单个步骤中在衬底上图案化。特别地，组合两个单独形成的图案的混合图案形成在单个掩模层上，然后转移到下面的基底。单独形成的图案中的第一个通过间距倍增形成，并且通过常规光刻形成第二个单独形成的图案。单独形成的图案中的第一个包括低于用于形成第二个单独形成的图案的光刻工艺的分辨率的线。这些线通过在光致抗蚀剂上形成图案然后将该图案刻蚀成无定形碳层而制成。在无定形碳的侧壁上形成宽度小于无定形碳的未蚀刻部分的宽度的侧壁盘。然后去除无定形碳，留下侧壁间隔物作为掩模图案。因此，间隔物形成具有小于用于在光致抗蚀剂上形成图案的光刻工艺的分辨率的特征尺寸的掩模。保护材料沉积在间隔物周围。使用硬掩模进一步保护间隔物，然后在硬掩模上形成并图案化光致抗蚀剂。光致抗蚀剂图案通过硬掩模转印到保护材料上。然后将由间隔物和临时材料制成的图案转移到下面的无定形碳硬掩模层。具有不同尺寸特征的图案然后被转移到下面的基底。

75. 发明申请

US20070138577A1 Transistor Structures 审中-公开
标题翻译：晶体管结构
公开(公告)号：US20070138577A1
公开(公告)日：2007-06-21
申请号：US11677923
申请日：2007-02-22
申请人： Gurtej Sandhu , John Moore , Neal Rueger
发明人： Gurtej Sandhu , John Moore , Neal Rueger
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L21/02332 , H01L21/0234 , H01L21/265 , H01L21/28061 , H01L21/28167 , H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L29/513 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer. Source/drain regions are formed within the semiconductive substrate, and are gatedly connected to one another by the at least one conductive layer. The invention also encompasses transistor structures.
摘要翻译：本发明包括将氮掺入含氧化硅的层中的方法。将含氧化硅的层暴露于含氮等离子体中以将氮引入层中。氮气随后在层内热退火以将至少一些氮与硅结合在层内。本发明还包括形成晶体管的方法。在半导体衬底上形成栅氧化层。栅氧化层包括二氧化硅。将栅极氧化层暴露于含氮等离子体中以将氮引入层中，并且在暴露期间该层保持在小于或等于400℃。随后，层内的氮被热退火以将至少大部分氮与硅结合。在栅极氧化物层上形成至少一个导电层。源极/漏极区域形成在半导体衬底内，并且通过至少一个导电层彼此门控连接。本发明还包括晶体管结构。

76. 发明申请

US20070117335A1 DOUBLE-SIDED CONTAINER CAPACITORS USING A SACRIFICIAL LAYER 有权
标题翻译：双面集装箱电容器使用一个真正的层
公开(公告)号：US20070117335A1
公开(公告)日：2007-05-24
申请号：US11625130
申请日：2007-01-19
申请人： Gurtej Sandhu , Kevin Shea , Chris Hill , Kevin Torek
发明人： Gurtej Sandhu , Kevin Shea , Chris Hill , Kevin Torek
IPC分类号： H01L21/336
CPC分类号： H01L28/91 , H01L27/10852
摘要： Double-sided container capacitors are formed using sacrificial layers. A sacrificial layer is formed within a recess in a structural layer. A lower electrode is formed within the recess. The sacrificial layer is removed to create a space to allow access to the sides of the structural layer. The structural layer is removed, creating an isolated lower electrode. The lower electrode can be covered with a capacitor dielectric and upper electrode to form a double-sided container capacitor.
摘要翻译：使用牺牲层形成双面容器电容器。在结构层的凹部内形成牺牲层。下部电极形成在凹部内。去除牺牲层以产生允许接近结构层的侧面的空间。去除结构层，形成隔离的下电极。下电极可以用电容器电介质和上电极覆盖以形成双面容器电容器。

77. 发明申请

US20070102705A1 Thin film transistors and semiconductor constructions 失效
标题翻译：薄膜晶体管和半导体结构
公开(公告)号：US20070102705A1
公开(公告)日：2007-05-10
申请号：US11644863
申请日：2006-12-21
申请人： Gurtej Sandhu , Shubneesh Batra , Pierre Fazan
发明人： Gurtej Sandhu , Shubneesh Batra , Pierre Fazan
IPC分类号： H01L29/04 , H01L29/786
CPC分类号： H01L29/78678 , H01L27/1214 , H01L27/127 , H01L29/04 , H01L29/6675 , H01L29/66757 , H01L29/66765 , H01L29/78672 , H01L29/78675
摘要： A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.
摘要翻译：相对于衬底形成薄膜晶体管的方法包括：a）在衬底上提供多晶材料的薄膜晶体管层，所述多晶材料包括晶界; b）在多晶薄膜层附近提供含氟层; c）在一段温度和一段时间内退火含氟层，所述时间段有效地将氟从含氟层驱动到多晶薄膜层中，并且在晶界内引入氟以钝化所述晶界; 以及d）提供与所述薄膜晶体管层可操作地相邻的晶体管栅极。薄膜晶体管可以被制造为底部门控或顶部门控。可以在薄膜晶体管层和含氟层之间设置缓冲层，缓冲层在退火期间从含氟层透过氟。优选地，退火温度足够高以将氟从含氟层驱动到多晶薄膜层中并且在晶界内引入氟以使所述晶界钝化，但是足够低以防止含氟层与多晶薄膜层。

78. 发明申请

US20070048630A1 Methods of forming capacitors 有权
标题翻译：形成电容器的方法
公开(公告)号：US20070048630A1
公开(公告)日：2007-03-01
申请号：US11472598
申请日：2006-06-21
申请人： Gurtej Sandhu
发明人： Gurtej Sandhu
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： H01L28/91 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/31144 , H01L27/10852
摘要： The invention includes methods of forming reticles configured for imprint lithography, methods of forming capacitor container openings, and methods in which capacitor container openings are incorporated into DRAM arrays. An exemplary method of forming a reticle includes formation of a radiation-imageable layer over a material. A lattice pattern is then formed within the radiation-imageable layer, with the lattice pattern defining a plurality of islands of the radiation-imageable layer. The lattice-patterned radiation-imageable layer is utilized as a mask while subjecting the material under the lattice-patterned layer to an etch which transfers the lattice pattern into the material. The etch forms a plurality of pillars which extend only partially into the material, with the pillars being spaced from one another by gaps. The gaps are subsequently narrowed with a second material which only partially fills the gaps.
摘要翻译：本发明包括形成用于压印光刻的掩模版的方法，形成电容器容器开口的方法，以及将电容器容器开口并入到DRAM阵列中的方法。形成掩模版的示例性方法包括在材料上形成可辐射成像层。然后在可辐射成像层内形成格子图案，其中格子图案限定可辐射成像层的多个岛。将格子图案的可辐射成像层用作掩模，同时使晶格图案层下的材料经历将晶格图案转移到材料中的蚀刻。蚀刻形成多个柱，其仅部分地延伸到材料中，柱通过间隙彼此间隔开。间隙随后仅用部分填充间隙的第二材料变窄。

79. 发明申请

US20070045119A1 Methods and apparatus for sorting and/or depositing nanotubes 有权
标题翻译：用于分选和/或沉积纳米管的方法和设备
公开(公告)号：US20070045119A1
公开(公告)日：2007-03-01
申请号：US11217170
申请日：2005-09-01
申请人： Gurtej Sandhu
发明人： Gurtej Sandhu
IPC分类号： C25D9/04
CPC分类号： C25D15/00 , B82Y30/00 , B82Y99/00 , C25D13/02
摘要： Methods and apparatus for forming devices using nanotubes. In one embodiment, an apparatus for depositing nanotubes onto a workpiece comprises a vessel configured to contain a deposition fluid having a plurality of nanotubes including first nanotubes having a first characteristic and second nanotubes having a second characteristic. The apparatus further includes a sorting unit in the vessel configured to selectively isolate or otherwise sort the first nanotubes from the second nanotubes, and a field unit in the vessel configured to attach the first nanotubes to the workpiece. For example, the field unit can attach the first nanotubes to the workpiece such that the first nanotubes are at least generally parallel to each other and in a desired orientation relative to the workpiece.
摘要翻译：使用纳米管形成器件的方法和装置。在一个实施例中，用于将纳米管沉积到工件上的装置包括：容器，其构造成容纳具有多个纳米管的沉积流体，所述多个纳米管包括具有第一特征的第一纳米管和具有第二特征的第二纳米管。该装置还包括在容器中的分选单元，其被配置为选择性地将第一纳米管与第二纳米管分离或以其他方式分类，并且容器中的场单元被配置为将第一纳米管附接到工件。例如，场单元可以将第一纳米管附接到工件，使得第一纳米管至少大体上彼此平行并且相对于工件以期望的取向。

80. 发明申请

US20070020870A1 Semiconductor capacitor structure and method to form same 失效
标题翻译：半导体电容器的结构与方法形成相同
公开(公告)号：US20070020870A1
公开(公告)日：2007-01-25
申请号：US11495655
申请日：2006-07-28
申请人： Gurtej Sandhu
发明人： Gurtej Sandhu
IPC分类号： H01L21/20
CPC分类号： H01L27/10852 , H01L21/28518 , H01L21/28568 , H01L27/10817 , H01L27/1085 , H01L28/84 , H01L28/90
摘要： A semiconductor capacitor structure comprising sidewalls of conductive hemispherical grained material, a base of metal silicide material, and a metal nitride material overlying the conductive hemispherical grained material and the metal silicide material. The semiconductor capacitor structure is fabricated by forming a base of metal silicide material along the sidewalls of an insulative material having an opening therein, forming sidewalls of conductive hemispherical grained material on the metal silicide material, and forming a metal nitride material overlying the conductive hemispherical grained material and the metal silicide material.
摘要翻译：一种半导体电容器结构，包括导电半球形颗粒材料的侧壁，金属硅化物材料的基底和覆盖在导电半球形颗粒材料和金属硅化物材料上的金属氮化物材料。半导体电容器结构通过沿着其中具有开口的绝缘材料的侧壁形成金属硅化物材料的基底来制造，在金属硅化物材料上形成导电半球状晶粒材料的侧壁，并且形成覆盖导电半球形晶粒的金属氮化物材料材料和金属硅化物材料。

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