专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20080098198A1 INFORMATION PROCESSING DEVICE, DATA TRANSFER METHOD, AND INFORMATION STORAGE MEDIUM 有权
标题翻译：信息处理设备，数据传输方法和信息存储介质
公开(公告)号：US20080098198A1
公开(公告)日：2008-04-24
申请号：US11834074
申请日：2007-08-06
申请人： Yuji Kawamura , Takeshi Yamazaki
发明人： Yuji Kawamura , Takeshi Yamazaki
IPC分类号： G06F12/00
CPC分类号： G06F12/1081 , G06F12/1072
摘要： The present invention has been conceived in view of the above described situation, and an object of the invention is to provide an information processing device, data transfer method and information storage medium that can commence data transfer to an I/O device immediately, and can stably exhibit data transfer performance. In an information processing device provided with hardware for sharing an address translation table, for translating logical addresses of a memory to physical addresses, between a main processor and a sub-processor, one of the sub-processors is caused to function as means for receiving a transfer request designating a logical address of the memory, means for translating the logical address that has been designated in the transfer request to a physical address using the shared address translation table, and means for executing transfer processing for data stored in the memory 14 according to the translated physical address.
摘要翻译：鉴于上述情况，本发明是考虑到的，其目的在于提供一种信息处理装置，数据传送方法和信息存储介质，可以立即开始数据传送到I / O装置，并且可以稳定展现数据传输性能。在具有用于共享地址转换表的硬件的信息处理装置中，为了将存储器的逻辑地址转换为物理地址，在主处理器和子处理器之间，使得一个子处理器用作接收装置指定存储器的逻辑地址的传送请求，用于使用共享地址转换表将已经在传送请求中指定的逻辑地址转换为物理地址的装置，以及用于对存储在存储器14中的数据执行传送处理的装置，到翻译的物理地址。

72. 发明申请

US20070205679A1 Brushless Motor 审中-公开
标题翻译：无刷电机
公开(公告)号：US20070205679A1
公开(公告)日：2007-09-06
申请号：US11578400
申请日：2005-04-12
申请人： Takahiro Terauchi , Chikahumi Sugai , Takeshi Yamazaki , Satoru Negishi
发明人： Takahiro Terauchi , Chikahumi Sugai , Takeshi Yamazaki , Satoru Negishi
IPC分类号： H02K1/04 , H02K11/00
CPC分类号： H02K29/12 , H02K3/522 , H02K5/08 , H02K5/225 , H02K2203/09
摘要： This brushless motor includes: stators respectively having wires and cores around which the wires are respectively wound; a housing which houses the stators; a rotor rotatably attached to the housing; and a bracket having conductive bodies to which terminal leading lines of the wires are respectively connected and an insulating body supporting the conductive bodies, and installed in an opening of the housing; wherein the conductive bodies are insert-molded to the insulating body.
摘要翻译：该无刷电动机包括：分别具有分别缠绕线的线和芯的定子; 一个住房的房子; 可旋转地连接到壳体的转子; 以及支架，其具有分别与所述导线的端子引线相连接的导电体和支撑所述导电体的绝缘体，并且安装在所述壳体的开口中; 其中所述导电体被插入模制到所述绝缘体。

73. 发明授权

US07243200B2 Establishing command order in an out of order DMA command queue 失效
标题翻译：在命令行DMA命令队列中建立命令顺序
公开(公告)号：US07243200B2
公开(公告)日：2007-07-10
申请号：US10891772
申请日：2004-07-15
申请人： Michael Norman Day , Charles Ray Johns , Peichun Peter Liu , Thuong Truong , Takeshi Yamazaki
发明人： Michael Norman Day , Charles Ray Johns , Peichun Peter Liu , Thuong Truong , Takeshi Yamazaki
IPC分类号： G06F12/00
CPC分类号： G06F13/28
摘要： A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.
摘要翻译：提供了一种用于控制存储器访问的方法，装置和计算机程序。直接存储器访问（DMA）单元已经在许多总线架构中变得普遍。然而，管理有限的系统资源已成为多个DMA单元的挑战。为了管理生成的多个命令并保留依赖关系，使用命令中的嵌入式标志或障碍命令。这些操作然后可以控制执行命令的顺序，以便保留依赖性。

74. 发明授权

US07204355B2 Shock absorbing structure of two-wheeled vehicle 失效
标题翻译：两轮车的减震结构
公开(公告)号：US07204355B2
公开(公告)日：2007-04-17
申请号：US10059325
申请日：2002-01-31
申请人： Hideki Akiyama , Toyokazu Nakamura , Takeshi Yamazaki
发明人： Hideki Akiyama , Toyokazu Nakamura , Takeshi Yamazaki
IPC分类号： F16F7/12
CPC分类号： B62J27/00 , B62J17/02 , F16F7/121 , F16F7/123
摘要： A shock absorbing structure of a two-wheeled vehicle capable of sufficiently absorbing shock and desirably maintain the steerability of the two-wheeled vehicle. The structure includes a shock absorbing member projecting from a front wheel, wherein the shock absorbing member is crashed when the vehicle collides with an obstacle so as to absorb shock. A ceiling wall of the shock absorbing member is located at such a position that the ceiling wall does not block a forward viewing area for a driver. A center of a leading end contact surface of the shock absorbing member is located at a position higher than a vertical position of a center of gravity G of both a motorcycle and the driver, and right and left side surfaces of the shock absorbing member are offset to a center of a vehicular body from right and left side surfaces of the motorcycle.
摘要翻译：一种能够充分吸收冲击并期望地保持两轮车辆的操纵性的两轮车辆的减震结构。该结构包括从前轮突出的减震构件，其中当车辆与障碍物碰撞时，减震构件坠毁，以便吸收冲击。冲击吸收构件的顶壁位于这样的位置，即顶壁不阻挡驾驶员的向前观察区域。减震构件的前端接触面的中心位于高于摩托车和驾驶员的重心G的垂直位置的位置，并且减震构件的左右侧面偏移从摩托车的右侧和左侧表面到车身的中心。

75. 发明申请

US20060179275A1 Methods and apparatus for processing instructions in a multi-processor system 审中-公开
标题翻译：用于在多处理器系统中处理指令的方法和装置
公开(公告)号：US20060179275A1
公开(公告)日：2006-08-10
申请号：US11053487
申请日：2005-02-08
申请人： Takeshi Yamazaki
发明人： Takeshi Yamazaki
IPC分类号： G06F9/40
CPC分类号： G06F9/3802 , G06F9/30087 , G06F9/3814 , G06F9/3838 , G06F9/3853 , G06F9/3867 , G06F9/3885
摘要： Methods and apparatus provide for transferring blocks of data between a shared memory and one or more of a plurality of parallel processors, each processor including a local memory; executing one or more programs within the local memory of one or more of the processors, wherein the one or more programs are coded such that they do not rely on data caching within the processor; and buffering not more than about three instructions from any local memory in any instruction buffer of any processor, wherein the instruction buffer of each processor is adapted to process instructions with substantially maximal efficiency when the one or more programs are coded such that they do not rely on data caching within the processor.
摘要翻译：方法和装置提供用于在共享存储器与多个并行处理器中的一个或多个并行处理器之间传送数据块，每个处理器包括本地存储器; 在一个或多个处理器的本地存储器内执行一个或多个程序，其中所述一个或多个程序被编码，使得它们不依赖于处理器内的数据高速缓存; 并且在任何处理器的任何指令缓冲器中从任何本地存储器缓冲不超过约三条指令，其中每个处理器的指令缓冲器适于在一个或多个程序被编码时基本上最大效率地处理指令，使得它们不依赖在处理器内的数据缓存。

76. 发明申请

US20060179255A1 Methods and apparatus for synchronizing data access to a local memory in a multi-processor system 有权
公开(公告)号：US20060179255A1
公开(公告)日：2006-08-10
申请号：US11053689
申请日：2005-02-08
申请人： Takeshi Yamazaki
发明人： Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F15/167
摘要： Methods and apparatus provide for receiving a request from an initiating device to initiate a data transfer into a local memory for execution of one or more programs therein, the local memory being operatively coupled to a first of a plurality of parallel processors capable of operative communication with a shared memory; facilitating the data transfer into the local memory; and producing a synchronization signal indicating that the data transfer into the local memory has been completed.

77. 发明申请

US20060149861A1 Methods and apparatus for list transfers using DMA transfers in a multi-processor system 有权
标题翻译：在多处理器系统中使用DMA传输的列表传输的方法和装置
公开(公告)号：US20060149861A1
公开(公告)日：2006-07-06
申请号：US11029891
申请日：2005-01-05
申请人： Takeshi Yamazaki , Tsutomu Horikawa , James Kahle , Charles Johns , Michael Day , Peichun Liu
发明人： Takeshi Yamazaki , Tsutomu Horikawa , James Kahle , Charles Johns , Michael Day , Peichun Liu
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , Y02D10/14
摘要： Methods and apparatus provide for transferring a plurality of data blocks between a shared memory and a local memory of a processor in response to a single DMA command issued by the processor to a direct memory access controller (DMAC), wherein the processor is capable of operative communication with the shared memory and the DMAC is operatively coupled to the local memory.
摘要翻译：方法和装置提供了响应于处理器向直接存储器访问控制器（DMAC）发出的单个DMA命令，在处理器的共享存储器和本地存储器之间传送多个数据块，其中处理器能够操作与共享存储器和DMAC的通信可操作地耦合到本地存储器。

78. 发明授权

US07032923B2 Air bag apparatus for a small size vehicle 有权
标题翻译：用于小型车辆的气囊装置
公开(公告)号：US07032923B2
公开(公告)日：2006-04-25
申请号：US10419136
申请日：2003-04-21
申请人： Norihiro Kurata , Takeshi Yamazaki , Takeshi Kuroe
发明人： Norihiro Kurata , Takeshi Yamazaki , Takeshi Kuroe
IPC分类号： B60R21/16
CPC分类号： B60R21/2338 , B60R21/20 , B60R21/2171 , B60R2021/0088 , B60R2021/23107 , B60R2021/23386 , B62J27/00
摘要： To provide an air bag apparatus for a small size vehicle, wherein a seat for a driver is provided at a rear portion of a vehicle body and an instrument panel, which a driver on the seat can visually observe is provided at a front portion of the vehicle body. The air bag apparatus assures a wide range of inflation and expansion of an air bag and can be applied to a conventional small size vehicle without a significant design change. A plurality of air bags which can constrain a driver on a seat from a forward direction are connected to each other by a connection mechanism and are accommodated in a folded state in an instrument panel.
摘要翻译：为了提供一种用于小型车辆的气囊装置，其中在车身的后部设置有用于驾驶员的座椅和仪表板，座椅上的驾驶员可以在视觉上观察到座椅，该前部部分车身。气囊装置确保了气囊的宽范围膨胀和膨胀，并且可以应用于传统的小型车辆而没有显着的设计变化。可以通过连接机构将能够将驾驶员从前方向限制在座椅上的多个气囊，并且以折叠状态容纳在仪表板中。

79. 发明申请

US20050251649A1 Methods and apparatus for address map optimization on a multi-scalar extension 审中-公开
标题翻译：用于多标量扩展的地址映射优化的方法和装置
公开(公告)号：US20050251649A1
公开(公告)日：2005-11-10
申请号：US11110492
申请日：2005-04-20
申请人： Takeshi Yamazaki
发明人： Takeshi Yamazaki
IPC分类号： G06F9/38 , G06F12/06 , G06F15/00 , G06F15/80
CPC分类号： G06F9/3891 , G06F9/3824 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F12/0607
摘要： Methods and systems are disclosed for staggered address mapping of memory regions in shared memory for use in multi-threaded processing of single instruction multiple data (SIMD) threads and multi-scalar threads without inter-thread memory region conflicts and permitting transition from SIMD mode to multi-scalar mode without the need for rearrangement of data stored in the memory regions.
摘要翻译：公开了用于共享存储器中的存储器区域的交错地址映射的方法和系统，用于单线程多数据（SIMD）线程和多标量线程的多线程处理，而不需要线程间存储器区域冲突，并允许从SIMD模式转换到多标量模式，而不需要重新排列存储在存储器区域中的数据。

80. 发明申请

US20050251648A1 Methods and apparatus for multi-processor pipeline parallelism 失效
标题翻译：多处理器管道并行性的方法和装置
公开(公告)号：US20050251648A1
公开(公告)日：2005-11-10
申请号：US11108959
申请日：2005-04-19
申请人： Takeshi Yamazaki
发明人： Takeshi Yamazaki
IPC分类号： G06F9/38 , G06F9/318 , G06F15/00 , G06F17/50
CPC分类号： G06F9/3885 , G06F9/30036 , G06F9/3012 , G06F9/3822 , G06F9/3851 , G06F17/5045
摘要： A processor is provided which has a modular organization including at least one local store operable to store data and instructions for execution, at least one functional unit operable to execute instructions on data provided from the local store, and at least one issue logic unit operable to convert instructions provided from the local store into operations of the functional unit for executing the instructions. Each such issue logic unit is operable to control execution of the instruction by one or more functional units according to a common instruction set. When the processor includes a plurality of functional units, the at least one issue logic unit is operable to decode a unitary instruction provided from the local store to simultaneously operate all of the functional units according to the unitary instruction. Each issue logic unit is further operable to decode multiple instructions to separately operate first and second subsets of the plurality of functional units, wherein each subset is operated according to a respective one of the multiple instructions.
摘要翻译：提供一种具有模块化组织的处理器，该模块化组织包括至少一个可操作以存储用于执行的数据和指令的本地存储器，至少一个功能单元，可操作以执行从本地存储器提供的数据上的指令，以及至少一个发行逻辑单元，将从本地商店提供的指令转换为用于执行指令的功能单元的操作。每个这样的发行逻辑单元可操作以根据公共指令集来控制由一个或多个功能单元执行指令。当处理器包括多个功能单元时，至少一个发行逻辑单元可操作以解码从本地存储器提供的统一指令，以根据单一指令同时操作所有功能单元。每个问题逻辑单元进一步可操作以解码多个指令以单独操作多个功能单元的第一和第二子集，其中每个子集根据多个指令中的相应一个来操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式