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71. 发明申请

US20110049462A1 FLAT LOWER BOTTOM ELECTRODE FOR PHASE CHANGE MEMORY CELL 有权
标题翻译：平底下电极用于相变记忆体
公开(公告)号：US20110049462A1
公开(公告)日：2011-03-03
申请号：US12550048
申请日：2009-08-28
申请人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Hsiang-Lan Lung , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Hsiang-Lan Lung , Alejandro G. Schrott
IPC分类号： H01L45/00 , H01L21/768 , H01L29/40
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts.
摘要翻译：一种具有平底下电极的相变存储单元及其制造方法。该方法包括在包括导电触点阵列的基板上形成电介质层，图案化，具有低纵横比以使得通孔的深度小于其宽度的通孔到对应于每个的基板的接触表面导电触头的阵列阵列连接到存取电路，蚀刻电介质层并在蚀刻后的介电层上和每个通孔内沉积电极材料，并平面化电极材料，以在每个导电触头上形成多个下部底部电极。

72. 发明申请

US20110038199A1 MEASUREMENT METHOD FOR READING MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION 失效
标题翻译：用于读取多级存储器单元的测量方法使用测量时间延迟作为等级定义的特性参数
公开(公告)号：US20110038199A1
公开(公告)日：2011-02-17
申请号：US12542146
申请日：2009-08-17
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
IPC分类号： G11C11/00 , G11C7/06 , G11C7/00
CPC分类号： G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0061 , G11C2013/0054
摘要： A memory system includes a memory cell configured to represent at least two binary values, a bit line coupled to the memory cell, and first and second comparators coupled to the bit line that, respectively, compare a first and second reference value to a value of a parameter of the bit-line. The system also includes a first and second timers configured to measures a time for the parameter of the bit line to decay. The system also includes a logic unit coupled to the first and second timers that selects the time for the parameter of the bit line to decay from to a first value or a second value.
摘要翻译：存储器系统包括被配置为表示至少两个二进制值的存储器单元，耦合到存储单元的位线，以及耦合到位线的第一和第二比较器，其分别将第一和第二参考值与位线的参数。该系统还包括配置成测量位线参数衰减的时间的第一和第二定时器。该系统还包括耦合到第一和第二定时器的逻辑单元，其选择位线的参数从第一值或第二值衰减的时间。

73. 发明授权

US07864566B2 Phase change memory programming method without reset over-write 有权
标题翻译：相位改变存储器编程方法，无复位重写
公开(公告)号：US07864566B2
公开(公告)日：2011-01-04
申请号：US12166934
申请日：2008-07-02
申请人： Matthew J. Breitwisch , Chung H. Lam
发明人： Matthew J. Breitwisch , Chung H. Lam
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0064 , G11C2013/0076 , G11C2013/0078 , G11C2013/0092
摘要： A method for programming a phase change memory device that avoids RESET overwrite. The method partially comprised of applying a reset write current pulse through the phase change memory element such that the reset write current pulse produces a voltage drop across the phase change memory element less than a reset threshold voltage and greater than a set threshold voltage. The reset write current pulse writing a RESET state to the phase change memory cell. The method additionally comprised of applying a set write current pulse through the phase change memory element such that the set write current pulse produces a voltage drop across the phase change memory element that is equal to or greater than the reset threshold voltage. The set write current pulse writing a SET state to the phase change memory cell.
摘要翻译：一种编程避免RESET重写的相变存储器件的方法。所述方法部分地包括通过将所述复位写入电流脉冲施加到所述相变存储元件，使得所述复位写入电流脉冲在所述相变存储元件上产生小于复位阈值电压并大于设定阈值电压的电压降。复位写入电流脉冲将RESET状态写入相变存储单元。该方法还包括通过相变存储元件施加设置的写入电流脉冲，使得所设置的写入电流脉冲在相变存储器元件上产生等于或大于复位阈值电压的电压降。该设定的写入电流脉冲将SET状态写入相变存储单元。

74. 发明申请

US20100328994A1 PHASE CHANGE MEMORY WITH FINITE ANNULAR CONDUCTIVE PATH 有权
标题翻译：相位变化记忆与有限的环形导电路径
公开(公告)号：US20100328994A1
公开(公告)日：2010-12-30
申请号：US12491816
申请日：2009-06-25
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
IPC分类号： G11C11/00 , H01S4/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/16 , Y10T29/49002
摘要： A phase change memory device and a method for programming the same. The method includes determining a maximum possible resistance for the memory cells in the phase change memory device. The method includes determining a high resistance state for the memory cells in the phase change memory device. The method includes receiving a request to program a target memory cell in the phase change memory device to the high resistance state. The method also includes resetting the target memory cell in the phase change memory device to the high resistance state such that the high resistance state of the target memory cell is of less resistance than the maximum possible resistance. In one embodiment of the invention, the high resistance state for the memory cells in the phase change memory device is at least 10% less than the maximum possible resistance.
摘要翻译：相变存储器件及其编程方法。该方法包括确定相变存储器件中的存储器单元的最大可能电阻。该方法包括确定相变存储器件中存储单元的高电阻状态。该方法包括接收将相变存储器件中的目标存储单元编程为高电阻状态的请求。该方法还包括将相变存储器件中的目标存储单元重置为高电阻状态，使得目标存储单元的高电阻状态的阻抗比最大可能的电阻小。在本发明的一个实施例中，相变存储器件中的存储单元的高电阻状态比最大可能电阻小至少10％。

75. 发明申请

US20100301409A1 VERTICAL FIELD EFFECT TRANSISTOR ARRAYS AND METHODS FOR FABRICATION THEREOF 有权
标题翻译：垂直场效应晶体管阵列及其制造方法
公开(公告)号：US20100301409A1
公开(公告)日：2010-12-02
申请号：US12851232
申请日：2010-08-05
申请人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L21/336
CPC分类号： H01L21/823487 , H01L27/088
摘要： Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.
摘要翻译：垂直场效应晶体管半导体结构和用于制造垂直场效应晶体管半导体结构的方法提供半导体柱阵列。半导体柱阵列中的每个半导体柱的每个垂直部分具有大于与相邻半导体柱的间隔距离的线宽。或者，阵列可以包括具有不同线宽的半导体柱，任选地在上述线宽和间隔距离限制的上下文中。用于制造半导体柱阵列的方法使用最小光刻尺寸的柱掩模层，其在被用作蚀刻掩模之前用至少一个间隔层环形增强。

76. 发明授权

US07825460B2 Vertical field effect transistor arrays and methods for fabrication thereof 有权
标题翻译：垂直场效应晶体管阵列及其制造方法
公开(公告)号：US07825460B2
公开(公告)日：2010-11-02
申请号：US11516208
申请日：2006-09-06
申请人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L29/78
CPC分类号： H01L21/823487 , H01L27/088
摘要： Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.
摘要翻译：垂直场效应晶体管半导体结构和用于制造垂直场效应晶体管半导体结构的方法提供半导体柱阵列。半导体柱阵列中的每个半导体柱的每个垂直部分具有大于与相邻半导体柱的间隔距离的线宽。或者，阵列可以包括具有不同线宽的半导体柱，任选地在前述线宽和间隔距离限制的上下文中。用于制造半导体柱阵列的方法使用最小光刻尺寸的柱掩模层，其在被用作蚀刻掩模之前用至少一个间隔层环形增强。

77. 发明申请

US20100135085A1 MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION 有权
标题翻译：多级存储单元利用测量时间延迟作为等级定义的特征参数
公开(公告)号：US20100135085A1
公开(公告)日：2010-06-03
申请号：US12698141
申请日：2010-02-02
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
IPC分类号： G11C16/06
CPC分类号： G11C13/0061 , G11C11/5628 , G11C11/565 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C16/32 , G11C2013/0054
摘要： A computer program product for operating a memory cell and memory array. The computer program product of memory cell operation entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage. A word-line in the electronic circuit is then activated. A discharging operation discharges the bit-line capacitor through the said memory cell in the electronic circuit to the word-line. Additionally, an electron discharge time measurement is started when the word-line is activated. The electron discharge time measurement is stopped when the voltage level in the bit-line falls below a pre-defined reference voltage. A determining operation determines the binary value from the measured electron discharge time.
摘要翻译：一种用于操作存储器单元和存储器阵列的计算机程序产品。存储单元操作的计算机程序产品需要接收读取存储在存储单元中的二进制值的请求。预充电操作将由存储器单元形成的电子电路中的位线电容器预先充电到预充电电压。然后激活电子电路中的字线。放电操作通过电子电路中的所述存储单元将位线电容器放电到字线。此外，当字线被激活时，电子放电时间测量开始。当位线中的电压电平低于预定义的参考电压时，停止电子放电时间测量。确定操作根据测量的电子放电时间确定二进制值。

78. 发明申请

US20090294850A1 METHOD TO TAILOR LOCATION OF PEAK ELECTRIC FIELD DIRECTLY UNDERNEATH AN EXTENSION SPACER FOR ENHANCED PROGRAMMABILITY OF A PROMPT-SHIFT DEVICE 有权
标题翻译：用于增强扬声器位置的方法，用于增强扬声器设备的增强可编程性的扩展间隔器
公开(公告)号：US20090294850A1
公开(公告)日：2009-12-03
申请号：US12130460
申请日：2008-05-30
申请人： Matthew J. Breitwisch , Roger W. Cheek , Jeffrey B. Johnson , Chung H. Lam , Beth A. Rainey , Michael J. Zierak
发明人： Matthew J. Breitwisch , Roger W. Cheek , Jeffrey B. Johnson , Chung H. Lam , Beth A. Rainey , Michael J. Zierak
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66477 , H01L21/26513 , H01L21/26586 , H01L21/266 , H01L29/1083 , H01L29/6659 , H01L29/66833 , H01L29/7834 , H01L29/792
摘要： The invention provides a method to enhance the programmability of a prompt-shift device, which reduces the programming time to sub-millisecond times, by altering the extension and halo implants, instead of simply omitting the same from one side of the device as is the case in the prior art prompt-shift devices. The invention includes an embodiment in which no additional masks are employed, or one additional mask is employed. The altered extension implant is performed at a reduced ion dose as compared to a conventional extension implant process, while the altered halo implant is performed at a higher ion dose than a conventional halo implant. The altered halo/extension implant shifts the peak of the electrical field to under an extension dielectric spacer.
摘要翻译：本发明提供了一种通过改变扩展和光晕注入来提高快速移位设备的可编程性的方法，其将编程时间缩短到几毫秒，而不是从设备的一侧简单地省略它现有技术中的瞬时移位装置。本发明包括其中不使用附加掩模的实施例，或者采用一个附加掩模。与常规的延伸植入过程相比，改变的延伸植入物以降低的离子剂量进行，而改变的晕轮植入物以比常规的晕轮植入物更高的离子剂量进行。改变的光晕/延伸注入将电场的峰值移动到延伸电介质间隔物下方。

79. 发明授权

US07426134B2 Sense circuit for resistive memory 有权
标题翻译：电阻式存储器感应电路
公开(公告)号：US07426134B2
公开(公告)日：2008-09-16
申请号：US11361811
申请日：2006-02-24
申请人： Thomas Happ , Matthew J. Breitwisch , Hsiang-Lang Lung
发明人： Thomas Happ , Matthew J. Breitwisch , Hsiang-Lang Lung
IPC分类号： G11C11/00
CPC分类号： G11C7/062 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C2013/0054 , G11C2211/5634
摘要： A memory includes a phase-change memory cell and a circuit. The phase-change memory cell can be set to at least three different states including a substantially crystalline state, a substantially amorphous state, and at least one partially crystalline and partially amorphous state. The circuit applies a first voltage across the memory cell to determine whether the memory cell is set at the substantially crystalline state and applies a second voltage across the memory cell to determine whether the memory cell is set at a partially crystalline and partially amorphous state.
摘要翻译：存储器包括相变存储器单元和电路。相变存储单元可以被设置为至少三种不同的状态，包括基本上为结晶状态，基本为非晶状态，以及至少一种部分结晶和部分非晶状态。电路在存储器单元两端施加第一电压以确定存储器单元是否被设置在基本上为结晶状态，并且在该存储单元上施加第二电压以确定存储器单元是否被设置为部分结晶和部分非晶态。

80. 发明申请

US20080185649A1 Substrate backgate for trigate FET 有权
标题翻译：基板背板用于触发FET
公开(公告)号：US20080185649A1
公开(公告)日：2008-08-07
申请号：US12099211
申请日：2008-04-08
申请人： Brent A. Anderson , Matthew J. Breitwisch , Edward J. Nowak
发明人： Brent A. Anderson , Matthew J. Breitwisch , Edward J. Nowak
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back gate can be used to control the threshold voltage of the FET. In one embodiment the back gate extends to an n-well in a p-type silicon substrate. A contact to the n-well allows electrical voltage to be applied to the back gate. A diode created between the n-well and p-substrate isolates the current flowing through the n-well from other devices on the substrate so that the back gate can be independently biased. In another embodiment the back gate extends to n-type polysilicon layer on an insulator layer on a p-type silicon substrate. A contact to the n-type polysilicon layer allows electrical voltage to be applied to the back gate. A trench isolation structure extending through the polysilicon layer to the insulator layer isolates current flowing through the polysilicon layer from other devices on the silicon substrate.
摘要翻译：公开了具有背栅的三栅场效应晶体管和形成晶体管的相关方法。具体地说，后门结合在翅片的下部。三栅结构形成在翅片上并与后门电隔离。背栅可用于控制FET的阈值电压。在一个实施例中，背栅极延伸到p型硅衬底中的n阱。与n阱的接触允许将电压施加到后门。在n阱和p衬底之间产生的二极管将流过n阱的电流与衬底上的其他器件隔离，使得后栅极可以被独立地偏置。在另一个实施例中，背栅极延伸到p型硅衬底上的绝缘体层上的n型多晶硅层。与n型多晶硅层的接触允许电压施加到后门。通过多晶硅层延伸到绝缘体层的沟槽隔离结构将流过多晶硅层的电流与硅衬底上的其它器件隔离。

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