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71. 发明申请

US20120061766A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120061766A1
公开(公告)日：2012-03-15
申请号：US13053611
申请日：2011-03-22
申请人： Tatsuo Izumi , Kikuko Sugimae , Hiroyuki Kutsukake , Keisuke Yonehama
发明人： Tatsuo Izumi , Kikuko Sugimae , Hiroyuki Kutsukake , Keisuke Yonehama
IPC分类号： H01L27/092 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/26586 , H01L21/76814 , H01L21/76825 , H01L21/823814 , H01L21/823871 , H01L27/11524 , H01L29/66575 , H01L29/7833
摘要： In the device, first and second transistors have first and second gates and first and second source/drain regions, respectively. First and second contacts are electrically connected to the first and the second source/drain regions, respectively. A width of a first bottom surface if the first contacts in a gate width direction of the first-gate is wider than a width of the first bottom in a gate length direction of the first-gate. Widths of a second bottom surface of the second-contact are narrower than the longitudinal direction width of the first bottom. The high-concentration region is formed between the first source/drain regions and the first-contact. Extending widths of an outline of the high-concentration region extending from an outline of the first bottom in the longitudinal direction is larger than extending widths of an outline of the high-concentration region extending from an outline thereof in the short direction.
摘要翻译：在器件中，第一和第二晶体管分别具有第一和第二栅极以及第一和第二源极/漏极区域。第一和第二触点分别电连接到第一和第二源极/漏极区域。如果第一栅极的栅极宽度方向上的第一接触宽度大于第一栅极的栅极长度方向上的第一底部的宽度，则第一底面的宽度。第二接触件的第二底面的宽度比第一底部的纵向宽度窄。高浓度区形成在第一源/漏区和第一接触之间。从第一底部的轮廓在纵向方向延伸的高浓度区域的轮廓的宽度的扩展大于从其沿短边方向的轮廓延伸的高浓度区域的轮廓的延伸宽度。

72. 发明申请

US20110193152A1 HIGH-VOLTAGE TRANSISTOR HAVING SHIELDING GATE 有权
标题翻译：具有屏蔽门的高压晶体管
公开(公告)号：US20110193152A1
公开(公告)日：2011-08-11
申请号：US13086478
申请日：2011-04-14
申请人： Hiroyuki Kutsukake , Kikuko Sugimae , Takeshi Kamigaichi
发明人： Hiroyuki Kutsukake , Kikuko Sugimae , Takeshi Kamigaichi
IPC分类号： H01L27/115 , H01L27/105
CPC分类号： H01L27/11526 , G11C16/0408 , G11C16/08 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/0649 , H01L29/402 , H01L29/404
摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
摘要翻译：半导体器件包括在半导体衬底的主表面上以矩阵形式布置的多个高电压绝缘栅场效应晶体管，每个具有栅电极，形成在栅电极上的栅电极接触和布线形成在栅极电极上的层在栅极宽度方向上相邻地接触以电连接沿栅极宽度方向布置的栅电极。并且该器件包括设置在位于栅极宽度方向和栅极长度方向相邻的晶体管之间的元件隔离区域的部分上的屏蔽栅极，用于施加与施加到栅极宽度方向上的电位的极性不同的参考电位或电位晶体管的栅极，以将晶体管的电流路径导通到元件隔离区域。

73. 发明申请

US20100052173A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD 失效
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：US20100052173A1
公开(公告)日：2010-03-04
申请号：US12548820
申请日：2009-08-27
申请人： Hidefumi Nawata , Kikuko Sugimae , Akihiro Kajita , Takamichi Tsuchiya
发明人： Hidefumi Nawata , Kikuko Sugimae , Akihiro Kajita , Takamichi Tsuchiya
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53295 , H01L21/76802 , H01L21/76816 , H01L21/76877 , H01L21/76883 , H01L23/5226 , H01L23/53238 , H01L23/53266 , H01L27/105 , H01L27/11526 , H01L27/11573 , H01L2924/0002 , H01L2924/00
摘要： A first impurity diffusion layer in a memory cell portion and a second impurity diffusion layer in a peripheral circuit portion are provided in a surface of a semiconductor substrate and having upper faces substantially flush with each other. First and second insulating films are formed to cover the upper faces of the impurity diffusion layers, and having substantially uniform film thicknesses. A first metal plug is formed in the insulating films, and connected to the first impurity diffusion layer. A second metal plug is formed in the first insulating film, to have a lower height than the first metal plug, and is connected to the second impurity diffusion layer. A first metal interconnection is connected to an upper end portion of the first metal plug, and having an upper face embedded in and flush with the second insulating film. A second metal interconnection is connected to an upper end portion of the second metal plug, and having an upper face embedded in and flush with the second insulating film.
摘要翻译：存储单元部分中的第一杂质扩散层和外围电路部分中的第二杂质扩散层设置在半导体衬底的表面中，并且具有大致彼此齐平的上表面。形成第一和第二绝缘膜以覆盖杂质扩散层的上表面，并且具有基本上均匀的膜厚度。第一金属插塞形成在绝缘膜中，并连接到第一杂质扩散层。第二金属插塞形成在第一绝缘膜中，具有比第一金属插塞低的高度，并且连接到第二杂质扩散层。第一金属互连件连接到第一金属插塞的上端部分，并且具有嵌入第二绝缘膜并与第二绝缘膜齐平的上表面。第二金属互连件连接到第二金属插塞的上端部分，并且具有嵌入第二绝缘膜并与第二绝缘膜齐平的上表面。

74. 发明授权

US07371643B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07371643B2
公开(公告)日：2008-05-13
申请号：US11672834
申请日：2007-02-08
申请人： Kikuko Sugimae , Hiroyuki Kutsukake
发明人： Kikuko Sugimae , Hiroyuki Kutsukake
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A memory cell and a selection transistor for selecting the memory cell are provided. The memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in the substrate, first and second control gates formed on the opposite sides of the floating gate to drive the floating gate, and an inter-gate insulation film formed between the first and second control gates and the floating gate. The selection transistor includes a selection gate wiring including a first portion constituted of the same conductive layer as the first conductive layer, and a second portion constituted of the same conductive layer as the second conductive layer, and a second diffusion layer formed in the substrate, facing the second portion of the selection gate wiring.
摘要翻译：提供了用于选择存储单元的存储单元和选择晶体管。存储单元包括通过第一栅极绝缘膜在半导体衬底上形成的浮置栅极，位于浮置栅极的相对侧并形成在衬底中的一对第一扩散层，形成在相对侧上的第一和第二控制栅极的栅极驱动浮栅，以及形成在第一和第二控制栅极与浮置栅极之间的栅极间绝缘膜。选择晶体管包括选择栅极布线，其包括由与第一导电层相同的导电层构成的第一部分和由与第二导电层相同的导电层构成的第二部分，以及形成在该基板中的第二扩散层，面对选择栅极布线的第二部分。

75. 发明申请

US20080061357A1 Semiconductor device with double barrier film 审中-公开
标题翻译：具有双阻挡膜的半导体器件
公开(公告)号：US20080061357A1
公开(公告)日：2008-03-13
申请号：US11980561
申请日：2007-10-31
申请人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
发明人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.
摘要翻译：一种半导体器件，包括第一绝缘层，第二绝缘层，第一阻挡膜，第二阻挡膜，扩散层。该装置还包括上接触孔，下接触孔和接触塞。上接触孔穿透第二绝缘层，并且在第二阻挡膜中具有底部。底部的宽度大于在与沟槽宽度方向交叉的方向上测量的在第一绝缘层中形成的沟槽。下接触孔穿过第一绝缘层和第一阻挡膜，经由沟槽与第一接触孔连通并设置在扩散层上。下接触孔的上部具有与沟槽相同的宽度。接触塞设置在上接触孔和下接触孔中。

76. 发明授权

US07119413B2 High-voltage transistor having shielding gate 有权
公开(公告)号：US07119413B2
公开(公告)日：2006-10-10
申请号：US10967128
申请日：2004-10-19
申请人： Hiroyuki Kutsukake , Kikuko Sugimae , Takeshi Kamigaichi
发明人： Hiroyuki Kutsukake , Kikuko Sugimae , Takeshi Kamigaichi
IPC分类号： H01L29/00
CPC分类号： H01L27/11526 , G11C16/0408 , G11C16/08 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/0649 , H01L29/402 , H01L29/404
摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.

77. 发明申请

US20060091466A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20060091466A1
公开(公告)日：2006-05-04
申请号：US11304580
申请日：2005-12-16
申请人： Kikuko Sugimae , Hiroyuki Kutsukake
发明人： Kikuko Sugimae , Hiroyuki Kutsukake
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A memory cell and a selection transistor for selecting the memory cell are provided. The memory cell includes a floating gate formed on a semiconductor substrate via a first gate insulation film, a pair of first diffusion layers positioned on the opposite sides of the floating gate and formed in the substrate, first and second control gates formed on the opposite sides of the floating gate to drive the floating gate, and an inter-gate insulation film formed between the first and second control gates and the floating gate. The selection transistor includes a selection gate•wiring including a first portion constituted of the same conductive layer as the first conductive layer, and a second portion constituted of the same conductive layer as the second conductive layer, and a second diffusion layer formed in the substrate, facing the second portion of the selection gate•wiring.
摘要翻译：提供了用于选择存储单元的存储单元和选择晶体管。存储单元包括通过第一栅极绝缘膜在半导体衬底上形成的浮置栅极，位于浮置栅极的相对侧并形成在衬底中的一对第一扩散层，形成在相对侧上的第一和第二控制栅极的栅极驱动浮栅，以及形成在第一和第二控制栅极与浮置栅极之间的栅极间绝缘膜。选择晶体管包括选择栅极布线，其包括由与第一导电层相同的导电层构成的第一部分和由与第二导电层相同的导电层构成的第二部分，以及形成在基板中的第二扩散层，面向选择门的第二部分。

78. 发明申请

US20060038232A1 High-voltage transistor having shielding gate 有权
公开(公告)号：US20060038232A1
公开(公告)日：2006-02-23
申请号：US10967128
申请日：2004-10-19
申请人： Hiroyuki Kutsukake , Kikuko Sugimae , Takeshi Kamigaichi
发明人： Hiroyuki Kutsukake , Kikuko Sugimae , Takeshi Kamigaichi
IPC分类号： H01L29/76
CPC分类号： H01L27/11526 , G11C16/0408 , G11C16/08 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/0649 , H01L29/402 , H01L29/404
摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.

79. 发明申请

US20050139904A1 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20050139904A1
公开(公告)日：2005-06-30
申请号：US10983744
申请日：2004-11-09
申请人： Takeshi Kamigaichi , Hiroyuki Kutsukake , Kikuko Sugimae
发明人： Takeshi Kamigaichi , Hiroyuki Kutsukake , Kikuko Sugimae
IPC分类号： H01L21/28 , G11C5/02 , G11C16/04 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/8247 , H01L27/06 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C5/025 , G11C16/04 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： A nonvolatile semiconductor memory on a semiconductor chip includes: a cell array region configured with a memory cell transistor having a first metallic salicide film, a first control gate electrode electrically coupled with the first metallic salicide film, and a floating gate electrode adjacent to the first control gate electrode; a high voltage circuit region including a high voltage transistor made of a second metallic salicide film, a first source region and a first drain region, and a first gate region arranged between the first source region and the first drain region; and a low voltage circuit region including a low voltage transistor made of a third metallic salicide film, a second source region and a second drain region electrically coupled with the third metallic salicide film, and a second gate region arranged between the second source region and the second drain region and is electrically coupled with the third metallic salicide film.
摘要翻译：半导体芯片上的非易失性半导体存储器包括：单元阵列区域，其配置有具有第一金属自对离硅化物膜的存储单元晶体管，与第一金属硅化物膜电耦合的第一控制栅电极和与第一金属化物质相邻的浮置栅电极控制栅电极; 包括由第二金属硅化物膜制成的高压晶体管，第一源极区和第一漏极区以及布置在第一源极区和第一漏极区之间的第一栅极区的高电压电路区; 以及包括由第三金属硅化物膜制成的低压晶体管的低电压电路区域，与第三金属硅化物膜电耦合的第二源极区域和第二漏极区域，以及布置在第二源极区域和第二源极区域之间的第二栅极区域第二漏区，并与第三金属硅化物膜电耦合。

80. 发明授权

US08681556B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08681556B2
公开(公告)日：2014-03-25
申请号：US13425704
申请日：2012-03-21
申请人： Hiroyuki Kutsukake , Kikuko Sugimae
发明人： Hiroyuki Kutsukake , Kikuko Sugimae
IPC分类号： G11C11/34
CPC分类号： H01L21/761 , H01L21/823481 , H01L21/823493 , H01L27/11546
摘要： A non-volatile semiconductor memory device according to an embodiment includes: a p-type semiconductor substrate; a p-type first p well which is formed in the semiconductor substrate and in which a bit line connecting transistor configured to connect a bit line of a memory cell and a sense amplifier unit is formed; and an n-type first N well which surrounds the first P well and which is configured to electrically isolate the first P well from the semiconductor substrate.
摘要翻译：根据实施例的非易失性半导体存储器件包括：p型半导体衬底; 形成在半导体衬底中的p型第一p阱，其中形成连接存储单元的位线和读出放大器单元的位线连接晶体管; 以及包围第一P阱并被配置为将第一P阱与半导体衬底电隔离的n型第一N阱。

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