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71. 发明授权

US07808806B2 Semiconductor apparatus having a large-size bus connection 有权
公开(公告)号：US07808806B2
公开(公告)日：2010-10-05
申请号：US11984932
申请日：2007-11-26
申请人： Yasurou Matsuzaki , Yasuharu Sato , Tadao Aikawa , Masafumi Yamazaki , Takaaki Suzuki
发明人： Yasurou Matsuzaki , Yasuharu Sato , Tadao Aikawa , Masafumi Yamazaki , Takaaki Suzuki
IPC分类号： G11C5/06
摘要： In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

72. 发明申请

US20070201292A1 Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function 有权
公开(公告)号：US20070201292A1
公开(公告)日：2007-08-30
申请号：US11790831
申请日：2007-04-27
申请人： Yasurou Matsuzaki
发明人： Yasurou Matsuzaki
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/4072 , G11C11/4094 , G11C2211/4061 , G11C2211/4065
摘要： According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, e.g., a refresh command, internally in a prescribed refresh cycle. And an internal circuit, according to said first internal command, executes corresponding control through clock-synchronous operations, and when said refresh command is issued, sequentially executes control corresponding to the refresh command and control corresponding to said first internal command through clock-asynchronous operations. According to the present invention, when a refresh timing signal is generated, the refresh operation can be intrupted among the external command operations.

73. 发明申请

US20060187732A1 Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function 有权
标题翻译：具有自动预充功能的记忆电路，具有自动内部指令功能的集成电路器件
公开(公告)号：US20060187732A1
公开(公告)日：2006-08-24
申请号：US11413204
申请日：2006-04-28
申请人： Yasurou Matsuzaki
发明人： Yasurou Matsuzaki
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/4072 , G11C11/4094 , G11C2211/4061 , G11C2211/4065
摘要： According to the present invention, a memory circuit requiring refresh operations a first circuit which receives a command in synchronization with a clock signal, and which generates a first internal command internally and a second circuit which generates a second internal command, e.g., a refresh command, internally in a prescribed refresh cycle. And an internal circuit, according to said first internal command, executes corresponding control through clock-synchronous operations, and when said refresh command is issued, sequentially executes control corresponding to the refresh command and control corresponding to said first internal command through clock-asynchronous operations. According to the present invention, when a refresh timing signal is generated, the refresh operation can be intrupted among the external command operations.
摘要翻译：根据本发明，一种需要刷新操作的存储电路，第一电路接收与时钟信号同步的命令，并且内部产生第一内部命令，第二电路产生第二内部命令，例如刷新命令在规定的刷新周期内部。并且根据所述第一内部命令，内部电路通过时钟同步操作执行相应的控制，并且当发出所述刷新命令时，通过时钟异步操作顺序执行对应于刷新命令的控制和对应于所述第一内部命令的控制。根据本发明，当产生刷新定时信号时，可以在外部命令操作中中断刷新操作。

74. 发明授权

US07064997B2 Memory circuit with automatic precharge function, and integrated circuit device with automatic internal command function 失效
标题翻译：具有自动预充功能的记忆电路，具有自动内部指令功能的集成电路器件
公开(公告)号：US07064997B2
公开(公告)日：2006-06-20
申请号：US10830149
申请日：2004-04-23
申请人： Yasurou Matsuzaki
发明人： Yasurou Matsuzaki
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/4072 , G11C11/4094 , G11C2211/4061 , G11C2211/4065
摘要： A memory circuit requiring refresh operations, the memory circuit includes a memory core having memory cells, and a memory control circuit which, for M external operation cycles, where M is greater than or equal to 2, has N internal operation cycles, where N is greater than M and less than 2M. The memory circuit also includes a refresh command generation circuit which generates refresh commands, and wherein the N internal operation cycles includes first internal operation cycles which execute external commands corresponding to the external operation cycles, and second internal operation cycles which execute the refresh commands, and the refresh command generation circuit generates the refresh commands according to a reception of the external command.
摘要翻译：一种需要刷新操作的存储器电路，该存储电路包括一个具有存储单元的存储器芯，以及一个存储器控制电路，对于M个大于或等于2的M个外部操作周期，具有N个内部操作周期，其中N是大于M且小于2M。存储电路还包括产生刷新命令的刷新命令产生电路，其中N个内部操作周期包括执行与外部操作周期相对应的外部命令的第一内部操作周期和执行刷新命令的第二内部操作周期，以及刷新命令生成电路根据外部命令的接收生成刷新命令。

75. 发明授权

US06769044B2 Input/output interface and semiconductor integrated circuit having input/output interface 有权
标题翻译：输入/输出接口和具有输入/输出接口的半导体集成电路
公开(公告)号：US06769044B2
公开(公告)日：2004-07-27
申请号：US10003048
申请日：2001-12-06
申请人： Yasurou Matsuzaki
发明人： Yasurou Matsuzaki
IPC分类号： G06F1314
CPC分类号： H04L25/493 , H03M5/02
摘要： A logical value is expressed by an order that transition edges appear in a plurality of transmission signals transmitting respectively on a plurality of signal lines. Otherwise, the logical value is expressed by a time difference between the transition edge of the transmission signal transmitting on the signal line and a transition edge of a standard timing signal. Therefore, a large amount of data can be transmitted through one signal line. Since a large amount of data can be transmitted by one transmission, it is possible to substantially increase the data transfer rate. Since only a small number of the signal lines are necessary, it is possible to reduce the number of input circuits and output circuits of the transmission signals, to reduce power consumption, and to reduce the wiring area of the signal lines.
摘要翻译：逻辑值由在多个信号线上分别发送的多个发送信号中出现过渡边缘的顺序表示。否则，逻辑值由在信号线上发送的发送信号的过渡边缘与标准定时信号的过渡边缘之间的时间差表示。因此，可以通过一条信号线传输大量的数据。由于通过一次发送可以发送大量数据，因此可以显着增加数据传送速率。由于仅需要少量的信号线，所以可以减少传输信号的输入电路和输出电路的数量，以减少功耗，并且减少信号线的布线面积。

76. 发明授权

US06628562B2 Method and apparatus for high-speed read operation in semiconductor memory 有权
公开(公告)号：US06628562B2
公开(公告)日：2003-09-30
申请号：US10001790
申请日：2001-12-05
申请人： Toshiya Uchida , Yasurou Matsuzaki
发明人： Toshiya Uchida , Yasurou Matsuzaki
IPC分类号： G11C800
CPC分类号： G11C7/22 , G11C7/1072
摘要： Data is stored into a plurality of first memory blocks, and regeneration data for regenerating this data is stored into a second memory block. In a read operation, either a first operation for reading the data directly from a first memory block selected or a second operation for regenerating the data from the data stored in unselected first memory blocks and the regeneration data stored in the second memory block is performed. This makes it possible to perform an additional read operation on a first memory block during the read operation of this first memory block. Therefore, requests for read operations from exterior can be received at intervals shorter than read cycles. That is, the semiconductor memory can be operated at higher speed, with an improvement in data read rate.

77. 发明授权

US06215714B1 Semiconductor memory device capable of reducing power consumption in self-refresh operation 有权
标题翻译：能够降低自刷新操作中的功耗的半导体存储器件
公开(公告)号：US06215714B1
公开(公告)日：2001-04-10
申请号：US09517279
申请日：2000-03-02
申请人： Yoshihiro Takemae , Yasurou Matsuzaki
发明人： Yoshihiro Takemae , Yasurou Matsuzaki
IPC分类号： G11C700
CPC分类号： G11C11/40622 , G11C11/406
摘要： A semiconductor memory device, which refreshes memory cells to retain data, has a first refresh mode and a second refresh mode. The first refresh mode is a mode for refreshing all of the memory cells, and the second refresh mode is a mode for refreshing a part of the memory cells. By refreshing only designated areas where data must be retained, power consumption in a refresh operation can be reduced, drastically cutting power consumption in a power-down mode.
摘要翻译：刷新存储单元以保留数据的半导体存储器件具有第一刷新模式和第二刷新模式。第一刷新模式是用于刷新所有存储单元的模式，第二刷新模式是用于刷新存储单元的一部分的模式。通过仅刷新必须保留数据的指定区域，可以减少刷新操作中的功耗，从而在掉电模式下大幅度地削减功耗。

78. 发明授权

US06198689B1 Integrated circuit device with built-in self timing control circuit 有权
标题翻译：具有内置自定时控制电路的集成电路器件
公开(公告)号：US06198689B1
公开(公告)日：2001-03-06
申请号：US09440667
申请日：1999-11-16
申请人： Masafumi Yamazaki , Hiroyoshi Tomita , Yasurou Matsuzaki
发明人： Masafumi Yamazaki , Hiroyoshi Tomita , Yasurou Matsuzaki
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C7/1072 , G11C7/22
摘要： The present invention is an integrated circuit device having a self timing control circuit for generating an input loading timing signal whose phase is adjusted with an external clock, where loading of input signals supplied from outside, such as a command input signal, address input signal and data input signal, to internal circuits is forbidden when the self timing control circuit is adjusting phase. And when the self timing control circuit finishes adjusting the phase to a certain degree, the loading operation of an input signal at the input circuit using the input loading timing signal is enabled. To execute such an operation, the input circuit generates an input loading control signal based on a lock-on signal or adjustment signal of the DLL circuit, or based on an input stop cancellation signal, for example. The input circuit controls the stop and restart of loading of the input signal according to this input loading control signal.
摘要翻译：本发明是一种具有自定时控制电路的集成电路装置，该自定时控制电路用于产生输入负载定时信号，该输入负载定时信号的相位是用外部时钟调整的，其中从外部输入的输入信号如命令输入信号，地址输入信号和数据输入信号，当自定时控制电路正在调整相位时，禁止内部电路。并且当自定时控制电路在一定程度上完成相位调整时，可以使用输入负载定时信号在输入电路处的输入信号的加载操作。为了执行这种操作，输入电路基于例如DLL电路的锁定信号或调整信号，或者基于输入停止消除信号，生成输入负载控制信号。输入电路根据该输入负载控制信号控制输入信号的停止和重新启动。

79. 发明授权

US06194932B1 Integrated circuit device 有权
标题翻译：集成电路器件
公开(公告)号：US06194932B1
公开(公告)日：2001-02-27
申请号：US09383015
申请日：1999-08-25
申请人： Yoshihiro Takemae , Yasurou Matsuzaki , Hiroyoshi Tomita , Nobutaka Taniguchi
发明人： Yoshihiro Takemae , Yasurou Matsuzaki , Hiroyoshi Tomita , Nobutaka Taniguchi
IPC分类号： H03L700
CPC分类号： G11C7/222 , G06F1/10 , G11C7/22 , H03L7/0814
摘要： The present invention omits a variable delay circuit (10 in FIG. 1) inside a DLL circuit, and instead, creates a timing synchronization circuit, which generates a second reference clock. The timing synchronization circuit shifts the phase of a first reference clock generated by a frequency divider to the timing of a timing signal generated from the other variable delay circuit so that the second reference clock matches to the timing signal. Then, a phase comparator compares the divided first reference clock to a variable clock that delays the second reference clock, and controls the delay time of the variable delay circuit so that both clocks are in phase. As a result, one variable delay circuit can be omitted, and a DLL circuit that uses a divided clock can be configured.
摘要翻译：本发明省略了DLL电路内部的可变延迟电路（图1中的10），而是产生产生第二参考时钟的定时同步电路。定时同步电路将由分频器产生的第一参考时钟的相位移位到从另一个可变延迟电路产生的定时信号的定时，使得第二参考时钟与定时信号相匹配。然后，相位比较器将分频的第一参考时钟与延迟第二参考时钟的可变时钟进行比较，并且控制可变延迟电路的延迟时间，使得两个时钟同相。结果，可以省略一个可变延迟电路，并且可以配置使用分频时钟的DLL电路。

80. 发明授权

US06181174B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06181174B2
公开(公告)日：2001-01-30
申请号：US09404221
申请日：1999-09-23
申请人： Waichirou Fujieda , Yasuharu Sato , Nobutaka Taniguchi , Hiroyoshi Tomita , Yasurou Matsuzaki
发明人： Waichirou Fujieda , Yasuharu Sato , Nobutaka Taniguchi , Hiroyoshi Tomita , Yasurou Matsuzaki
IPC分类号： H03L706
CPC分类号： H03L7/0805 , G06F1/08 , G06F1/10 , G11C7/1039 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , H03K5/133 , H03K23/58 , H03L7/0814
摘要： A semiconductor integrated circuit device includes a DLL circuit. The DLL circuit includes a frequency divider which frequency-divides an input clock at a frequency dividing ratio which is varied depending on a frequency of the input clock and thus results in a dummy clock and a reference clock. A delay system includes a variable delay circuit which delays the dummy clock. A control circuit controls a delay amount of the variable delay circuit so that a phase of a delayed dummy clock from the delay system and the reference clock becomes zero.
摘要翻译：半导体集成电路装置包括DLL电路。 DLL电路包括分频器，该分频器以分频比对输入时钟进行分频，该分频比根据输入时钟的频率而变化，从而产生虚拟时钟和参考时钟。延迟系统包括延迟虚拟时钟的可变延迟电路。控制电路控制可变延迟电路的延迟量，使得来自延迟系统和参考时钟的延迟的虚拟时钟的相位变为零。

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