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71. 发明授权

US06211074B1 Methods and arrangements for reducing stress and preventing cracking in a silicide layer 失效
标题翻译：降低应力并防止硅化物层开裂的方法和装置
公开(公告)号：US06211074B1
公开(公告)日：2001-04-03
申请号：US09076584
申请日：1998-05-12
申请人： Richard J. Huang , Guarionex Morales
发明人： Richard J. Huang , Guarionex Morales
IPC分类号： H01L214763
CPC分类号： H01L27/11521 , H01L21/32053 , H01L27/115
摘要： Methods and arrangements that increase the process control during the fabrication of the control gate configuration in a non-volatile memory semiconductor device are provided. The methods and arrangements effectively prevent cracks from developing within a tungsten suicide layer that is part of a control gate structure within a non-volatile memory cell. Cracks within the tungsten silicide layer can affect the performance of the memory cell by increasing the resistance of the control gate configuration. The methods and arrangements prevent cracking of the tungsten silicide layer by minimizing the relative difference between temperatures associated with the deposition of the tungsten suicide layer and deposition of a subsequent overlying cap layer.
摘要翻译：提供了在制造非易失性存储器半导体器件中的控制栅极配置期间增加过程控制的方法和布置。该方法和装置有效地防止在作为非易失性存储单元内的控制栅极结构的一部分的硅化钨层内发生裂纹。硅化钨层内的裂纹可以通过增加控制栅极配置的电阻来影响存储单元的性能。所述方法和装置通过使与硅化钨层的沉积相关的温度之间的相对差异和随后的上覆盖层的沉积最小化来防止硅化钨层的破裂。

72. 发明授权

US6080639A Semiconductor device containing P-HDP interdielectric layer 有权
标题翻译：含有P-HDP介电层的半导体器件
公开(公告)号：US6080639A
公开(公告)日：2000-06-27
申请号：US199265
申请日：1998-11-25
申请人： Richard J. Huang , Chi Chang
发明人： Richard J. Huang , Chi Chang
IPC分类号： H01L21/316 , H01L21/762 , H01L21/8247 , H01L21/76 , H01L21/4763
CPC分类号： H01L27/11521 , H01L21/02129 , H01L21/02211 , H01L21/02274 , H01L21/02362 , H01L21/31625 , H01L21/76202 , H01L21/76235
摘要： Void formation is avoided without thermal treatment by a gap filling between electrically conductive elements such as stacked gates which are formed atop of isolation regions, with an oxide layer using a HDP technique. The oxide layer is doped with phosphorus to getter mobile ionic contaminants.
摘要翻译：通过在形成于隔离区域顶部的层叠栅极之间的导电元件之间的间隙填充，使用HDP技术的氧化物层，避免了空隙形成。氧化物层掺杂磷以吸收移动离子污染物。

73. 发明授权

US6030891A Vacuum baked HSQ gap fill layer for high integrity borderless vias 失效
标题翻译：真空烘烤HSQ间隙填充层，用于高完整性无边界通孔
公开(公告)号：US6030891A
公开(公告)日：2000-02-29
申请号：US993052
申请日：1997-12-18
申请人： Khanh Tran , Richard J. Huang , Guarionex Morales
发明人： Khanh Tran , Richard J. Huang , Guarionex Morales
IPC分类号： H01L21/3105 , H01L21/312 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76852 , H01L21/02134 , H01L21/02164 , H01L21/022 , H01L21/02282 , H01L21/3124 , H01L21/76814 , H01L21/76826 , H01L21/76843 , H01L21/31058 , Y10S438/958
摘要： Borderless vias are formed in electrical connection with a lower metal feature of a metal patterned later gap filled with HSQ. Vacuum baking is conducted before filling the through-hole to outgas water absorbed during solvent cleaning, thereby reducing void formation and improving via integrity. Embodiments include vacuum baking at a temperature of about 300.degree. C. to about 400.degree. C., for about 45 seconds to about 2 minutes, at a pressure of no greater than about 10.sup.-6 Torr, preferably in the same tool employed for depositing the barrier layer in filling the through-hole.
摘要翻译：无边界通孔形成为与填充有HSQ的金属图案化的后续间隙的下部金属特征电连接。在填充通孔之前进行真空烘烤以排出在溶剂清洗期间吸收的水，从而减少空隙形成并改进通过完整性。实施方案包括在约300℃至约400℃的温度下，在不大于约10 -6乇的压力下进行约45秒至约2分钟的真空烘烤，优选在用于沉积的相同工具中进行真空烘烤阻挡层填充通孔。

74. 发明授权

US5801095A Production worthy interconnect process for deep sub-half micrometer back-end-of-line technology 失效
标题翻译：深层次半微米后端技术的生产价值互连过程
公开(公告)号：US5801095A
公开(公告)日：1998-09-01
申请号：US710071
申请日：1996-09-10
申请人： Richard J. Huang , Christy M.-C. Woo
发明人： Richard J. Huang , Christy M.-C. Woo
IPC分类号： H01L21/768 , H01L23/485 , H01L23/522 , H01L29/45 , H01L21/28
CPC分类号： H01L21/76843 , H01L21/7684 , H01L21/76841 , H01L21/76895 , H01L23/485 , H01L23/5226 , H01L29/456 , H01L2924/0002 , Y10S257/915
摘要： The present invention is directed to improving the throughput of the process for fabricating multilayer interconnects. Tungsten plugs, formed in contact/via openings etched in an interlayer dielectric, have been widely used in industry to form interconnection between different metal layers. An adhesion layer comprising a Ti/TiN stack is typically employed to support the adhesion of the tungsten plug in the contact/via openings. The present invention is directed to a process involving the formation of a Ti/TiN landing pad at the base of contact/via openings prior to the deposition of the interlayer dielectric. The process of the present invention enables the removal of the Ti under-layer and the reduction of the TiN thickness in the Ti/TiN stack. The throughput of the process for fabricating multilayer interconnects is thus greatly improved while the integrity of the devices are maintained.
摘要翻译：本发明旨在改进用于制造多层互连的工艺的生产量。形成在层间电介质中蚀刻的接触/通孔开口的钨塞已被广泛用于工业中以形成不同金属层之间的互连。通常使用包含Ti / TiN叠层的粘合层来支撑钨丝塞在接触/通孔中的粘附。本发明涉及在沉积层间电介质之前在接触/通孔开口的底部形成Ti / TiN着陆焊盘的方法。本发明的方法能够在Ti / TiN叠层中除去Ti底层和TiN厚度的降低。因此，在保持装置的完整性的同时，大大提高了用于制造多层互连的工艺的生产量。

75. 发明授权

US5686761A Production worthy interconnect process for deep sub-half micrometer back-end-of-line technology 失效
标题翻译：深层次半微米后端技术的生产价值互连过程
公开(公告)号：US5686761A
公开(公告)日：1997-11-11
申请号：US608913
申请日：1996-02-29
申请人： Richard J. Huang , Christy M.-C. Woo
发明人： Richard J. Huang , Christy M.-C. Woo
IPC分类号： H01L21/768 , H01L23/485 , H01L23/522 , H01L29/45 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76843 , H01L21/7684 , H01L21/76841 , H01L21/76895 , H01L23/485 , H01L23/5226 , H01L29/456 , H01L2924/0002 , Y10S257/915
摘要： The present invention is directed to improving the throughput of the process for fabricating multilayer interconnects. Tungsten plugs, formed in contact/via openings etched in an interlayer dielectric, have been widely used in industry to form interconnection between different metal layers. An adhesion layer comprising a Ti/TiN stack is typically employed to support the adhesion of the tungsten plug in the contact/via openings. The present invention is directed to a process involving the formation of a Ti/TiN landing pad at the base of contact/via openings prior to the deposition of the interlayer dielectric. The process of the present invention enables the removal of the Ti under-layer and the reduction of the TiN thickness in the Ti/TiN stack. The throughput of the process for fabricating multilayer interconnects is thus greatly improved while the integrity of the devices are maintained.
摘要翻译：本发明旨在改进用于制造多层互连的工艺的生产量。形成在层间电介质中蚀刻的接触/通孔开口的钨塞已被广泛用于工业中以形成不同金属层之间的互连。通常使用包含Ti / TiN叠层的粘合层来支撑钨丝塞在接触/通孔中的粘附。本发明涉及在沉积层间电介质之前在接触/通孔开口的底部形成Ti / TiN着陆焊盘的方法。本发明的方法能够在Ti / TiN叠层中除去Ti底层和TiN厚度的降低。因此，在保持装置的完整性的同时，大大提高了用于制造多层互连的工艺的生产量。

76. 发明授权

US5674781A Landing pad technology doubled up as a local interconnect and borderless contact for deep sub-half micrometer IC application 失效
标题翻译：作为本地互连和无边界接触，着陆垫技术加倍，用于深度二分之一微米IC应用
公开(公告)号：US5674781A
公开(公告)日：1997-10-07
申请号：US608377
申请日：1996-02-28
申请人： Richard J. Huang , Robin W. Cheung , Rajat Rakkhit , Raymond T. Lee
发明人： Richard J. Huang , Robin W. Cheung , Rajat Rakkhit , Raymond T. Lee
IPC分类号： H01L23/522 , H01L23/532 , H01L21/441
CPC分类号： H01L21/76895 , H01L21/28518 , H01L23/485 , H01L23/53257 , H01L2924/0002 , Y10S257/915
摘要： The present invention is directed to a technology that simplifies the process of fabricating multilayer interconnects and reduces capacitance in integrated circuits employing multilayer interconnects. The novel landing pad technology of the present invention simplifies the current process steps involved in the formation of multilayer interconnects. The same contact/via etch, the same PVD TiN deposition, etc., can be modularized and repeated to build up multilayer metalization. The process of the present invention for forming multilayer interconnects involves the formation of Ti/TiN stack interconnect structures that can be used as local interconnects and contact landing pads on the same level. The contact landing pads facilitate the use of a borderless contact approach which enables a reduction in the size of the source-drain area. As the source-drain area is reduced, junction capacitance decreases, and packing density can be increased. Source-drain real estate can be also be minimized by using the Ti/TiN stack interconnect structures as contact landing pads in the implementation of raised source-drain technology. The Ti/TiN stack interconnect structures can also be used as short local interconnects in SRAM devices.
摘要翻译：本发明涉及一种简化多层互连的制造工艺并减少采用多层互连的集成电路中的电容的技术。本发明的新型着陆垫技术简化了形成多层互连所涉及的当前工艺步骤。相同的接触/通孔蚀刻，相同的PVD TiN沉积等可以被模块化和重复以建立多层金属化。用于形成多层互连的本发明的方法涉及形成可用作局部互连的Ti / TiN叠层互连结构并且在相同的层上接触着陆焊盘。接触着陆垫有利于使用无边界接触方法，这使得能够减小源极 - 漏极区域的尺寸。随着源极 - 漏极面积的减小，结电容降低，堆积密度增加。在实施升高的源极 - 漏极技术中，通过使用Ti / TiN堆叠互连结构作为接触着陆焊盘，也可以最大限度地减少源极漏极空间。 Ti / TiN堆叠互连结构也可以用作SRAM器件中的短局部互连。

77. 发明授权

US5654589A Landing pad technology doubled up as local interconnect and borderless contact for deep sub-half micrometer IC application 失效
标题翻译：作为本地互连和无边界接触，着陆垫技术加倍，用于深半微米IC应用
公开(公告)号：US5654589A
公开(公告)日：1997-08-05
申请号：US466649
申请日：1995-06-06
申请人： Richard J. Huang , Robin W. Cheung , Rajat Rakkhit , Raymond T. Lee
发明人： Richard J. Huang , Robin W. Cheung , Rajat Rakkhit , Raymond T. Lee
IPC分类号： H01L23/522 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76895 , H01L21/28518 , H01L23/485 , H01L23/53257 , H01L2924/0002 , Y10S257/915
摘要： The present invention is directed to a technology that simplifies the process of fabricating multilayer interconnects and reduces capacitance in integrated circuits employing multilayer interconnects. The novel landing pad technology of the present invention simplifies the current process steps involved in the formation of multilayer interconnects. The same contact/via etch, the same PVD TiN deposition, etc., can be modularized and repeated to build up multilayer metalization. The process of the present invention for forming multilayer interconnects involves the formation of Ti/TiN stack interconnect structures that can be used as local interconnects and contact landing pads on the same level. The contact landing pads facilitate the use of a borderless contact approach which enables a reduction in the size of the source-drain area. As the source-drain area is reduced, junction capacitance decreases, and packing density can be increased. Source-drain real estate can be also be minimized by using the Ti/TiN stack interconnect structures as contact landing pads in the implementation of raised source-drain technology. The Ti/TiN stack interconnect structures can also be used as short local interconnects in SRAM devices.
摘要翻译：本发明涉及一种简化多层互连的制造工艺并减少采用多层互连的集成电路中的电容的技术。本发明的新型着陆垫技术简化了形成多层互连所涉及的当前工艺步骤。相同的接触/通孔蚀刻，相同的PVD TiN沉积等可以被模块化和重复以建立多层金属化。用于形成多层互连的本发明的方法涉及形成可用作局部互连的Ti / TiN叠层互连结构并且在相同的层上接触着陆焊盘。接触着陆垫有利于使用无边界接触方法，这使得能够减小源极 - 漏极区域的尺寸。随着源极 - 漏极面积的减小，结电容降低，堆积密度增加。在实施升高的源极 - 漏极技术中，通过使用Ti / TiN堆叠互连结构作为接触着陆焊盘，也可以最大限度地减少源极漏极空间。 Ti / TiN堆叠互连结构也可以用作SRAM器件中的短局部互连。

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