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71. 发明授权

US07715501B2 Partial response receiver 有权
标题翻译：部分响应接收器
公开(公告)号：US07715501B2
公开(公告)日：2010-05-11
申请号：US10966070
申请日：2004-10-18
申请人： Vladimir M. Stojanovic , Mark A. Horowitz , Jared L. Zerbe , Anthony Bessios , Andrew C. C. Ho , Jason C. Wei , Grace Tsang , Bruno W. Garlepp
发明人： Vladimir M. Stojanovic , Mark A. Horowitz , Jared L. Zerbe , Anthony Bessios , Andrew C. C. Ho , Jason C. Wei , Grace Tsang , Bruno W. Garlepp
IPC分类号： H04L27/06
CPC分类号： H04L25/03057 , H04L7/0276 , H04L25/063 , H04L25/497 , H04L2025/03369 , H04L2025/03503
摘要： A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.
摘要翻译：用于接收经由电信号导体发送的信号的接收电路。第一采样电路产生指示信号是否超过第一阈值电平的第一采样值，并且第二采样电路产生指示信号是否超过第二阈值电平的第二采样值。第一选择电路从第一和第二采样电路接收第一和第二采样值，并根据先前产生的采样值选择作为选择的采样值输出的第一采样值或第二采样值。

72. 发明授权

US07706524B2 Signal line routing to reduce crosstalk effects 失效
标题翻译：信号线路由减少串扰效应
公开(公告)号：US07706524B2
公开(公告)日：2010-04-27
申请号：US09993138
申请日：2001-11-16
申请人： Jared L. Zerbe
发明人： Jared L. Zerbe
IPC分类号： H04M1/00
CPC分类号： H04B3/32 , H01R13/6467 , H05K1/0228 , H05K2201/09245 , H05K2201/10689
摘要： Described herein is a technique for reducing the effects of crosstalk between adjacent signal lines of a data path. The data path is formed by multiple signal lines arranged adjacent each other and traversing multiple segments. The signal lines are transposed between segments in a manner that is chosen to reduce differences in interline couplings between different pairs of the signal lines. The interline coupling of a pair of signal lines is represented as a function of coupling terms. A coupling term corresponds to each segment of a pair of signal lines, and is a function of the distance between the signal lines over that segment. Prior to transmitting a digital signal over the data path, the digital signal is encoded to reduce variations over time in a collective signal level of the digital signal.
摘要翻译：这里描述了一种用于减少数据路径的相邻信号线之间串扰的影响的技术。数据路径由彼此相邻布置并遍历多个段的多个信号线形成。信号线以选择以减少不同对的信号线之间的线间耦合的差异的方式在段之间转置。一对信号线的线间耦合表示为耦合项的函数。耦合项对应于一对信号线的每个段，并且是该段上的信号线之间的距离的函数。在通过数据路径发送数字信号之前，数字信号被编码以减少数字信号的集体信号电平中随时间的变化。

73. 发明授权

US07706480B2 Partial response receiver 有权
标题翻译：部分响应接收器
公开(公告)号：US07706480B2
公开(公告)日：2010-04-27
申请号：US12508030
申请日：2009-07-23
申请人： Vladimir M. Stojanovic , Mark A. Horowitz , Jared L. Zerbe , Anthony Bessios , Andrew C. C. Ho , Jason C. Wei , Grace Tsang , Bruno W. Garlepp
发明人： Vladimir M. Stojanovic , Mark A. Horowitz , Jared L. Zerbe , Anthony Bessios , Andrew C. C. Ho , Jason C. Wei , Grace Tsang , Bruno W. Garlepp
IPC分类号： H04L27/06
CPC分类号： H04L25/03057 , H04L7/0276 , H04L25/063 , H04L25/497 , H04L2025/03369 , H04L2025/03503
摘要： An integrated circuit device having a receive circuit is disclosed. The receive circuit generates first and second sets of samples of incoming symbols during first and second time intervals, respectively. A select circuit selects, based at least in part on the first set of samples, at least one sample from the second set to be output as a received data value. The integrated circuit device further includes a transmit circuit to generate an output symbol during a third time interval. The output symbol has an amplitude based, at least in part, on a transmit data value for which an output symbol was generated during a time interval prior to the third time interval.
摘要翻译：公开了一种具有接收电路的集成电路装置。接收电路分别在第一和第二时间间隔期间产生输入符号的第一和第二组样本。选择电路至少部分地基于第一组采样选择要作为接收数据值输出的来自第二组的至少一个采样。集成电路装置还包括在第三时间间隔期间产生输出符号的发送电路。输出符号至少部分地基于在第三时间间隔之前的时间间隔期间产生输出符号的发送数据值。

74. 发明授权

US07565468B2 Integrated circuit memory device and signaling method for adjusting drive strength based on topography of integrated circuit devices 有权
标题翻译：集成电路存储器件和基于集成电路器件形貌调整驱动强度的信令方法
公开(公告)号：US07565468B2
公开(公告)日：2009-07-21
申请号：US11929974
申请日：2007-10-30
申请人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
发明人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
IPC分类号： G06F13/00 , G05F1/10
CPC分类号： G06F13/4291 , G06F3/061 , G06F3/0611 , G06F3/0619 , G06F3/0658 , G06F3/0661 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/1081 , G06F13/102 , G06F13/1689 , G06F13/364 , G06F13/4072 , G06F13/4086 , G06F13/4234 , G06F13/4243 , G06F2206/1014 , G06F2212/7201 , G11C5/04 , G11C5/063 , G11C7/1048 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C16/32 , G11C19/00 , H03K19/00384 , H03K19/018585
摘要： An integrated circuit device includes an output driver, a first register to store a value representative of a drive strength setting of the output driver, wherein the value is determined based on information stored in a supplemental memory device external to the integrated circuit memory device, and a transmitter circuit configurable to receive the value representative of a drive strength setting of the output driver. The output driver is configurable to output data synchronously with respect to an external clock signal.
摘要翻译：集成电路装置包括输出驱动器，第一寄存器，用于存储代表输出驱动器的驱动强度设置的值，其中该值基于存储在集成电路存储器件外部的补充存储器件中的信息确定，以及发射机电路可配置为接收代表输出驱动器的驱动强度设置的值。输出驱动器可配置为相对于外部时钟信号同步输出数据。

75. 发明申请

US20090175326A1 PARTIAL RESPONSE RECEIVER 有权
标题翻译：部分响应接收者
公开(公告)号：US20090175326A1
公开(公告)日：2009-07-09
申请号：US12403340
申请日：2009-03-12
申请人： Vladimir M. Stojanovic , Mark A. Horowitz , Jared L. Zerbe , Anthony Bessios , Andrew C.C. Ho , Jason C. Wei , Grace Tsang , Bruno w. Garlepp
发明人： Vladimir M. Stojanovic , Mark A. Horowitz , Jared L. Zerbe , Anthony Bessios , Andrew C.C. Ho , Jason C. Wei , Grace Tsang , Bruno w. Garlepp
IPC分类号： H03H7/30 , H03H7/40
CPC分类号： H04L25/03057 , H04L7/0276 , H04L25/063 , H04L25/497 , H04L2025/03369 , H04L2025/03503
摘要： A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.
摘要翻译：用于接收经由电信号导体发送的信号的接收电路。第一采样电路产生指示信号是否超过第一阈值电平的第一采样值，并且第二采样电路产生指示信号是否超过第二阈值电平的第二采样值。第一选择电路从第一和第二采样电路接收第一和第二采样值，并根据先前产生的采样值选择作为选择的采样值输出的第一采样值或第二采样值。

76. 发明授权

US07308058B2 Transparent multi-mode PAM interface 有权
标题翻译：透明多模PAM接口
公开(公告)号：US07308058B2
公开(公告)日：2007-12-11
申请号：US10805413
申请日：2004-03-19
申请人： Jared L. Zerbe , Carl W. Werner , William F. Stonecypher , Fred F. Chen
发明人： Jared L. Zerbe , Carl W. Werner , William F. Stonecypher , Fred F. Chen
IPC分类号： H03K9/02
CPC分类号： H04L27/08 , H04L1/0003 , H04L5/1438 , H04L25/028 , H04L25/0292 , H04L25/4917 , H04L2025/03585
摘要： Provided are a method and apparatus for high-speed, multi-mode PAM symbol transmission. A multi-mode PAM output driver drives one or more symbols, the number of levels used in the PAM modulation of the one or more symbols depending on the state of a PAM mode signal. Additionally, the one or more symbols are driven at a symbol rate, the symbol rate selected in accordance with the PAM mode signal so that a data rate of the driven symbols is constant with respect to changes in the state of the PAM mode signal. Further provided are methods for determining the optimal number of PAM levels for symbol transmission and reception in a given physical environment.
摘要翻译：提供了一种用于高速，多模式PAM符号传输的方法和装置。多模式PAM输出驱动器根据PAM模式信号的状态驱动一个或多个符号，用于一个或多个符号的PAM调制中使用的级别数。另外，一个或多个符号以符号率被驱动，符号率是根据PAM模式信号选择的，使得驱动符号的数据速率相对于PAM模式信号的状态的变化是恒定的。还提供了用于在给定物理环境中确定用于符号传输和接收的PAM最优数量的方法。

77. 发明授权

US07174400B2 Integrated circuit device that stores a value representative of an equalization co-efficient setting 有权
标题翻译：集成电路装置，其存储代表均衡系数设定的值
公开(公告)号：US07174400B2
公开(公告)日：2007-02-06
申请号：US11181411
申请日：2005-07-13
申请人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
发明人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
IPC分类号： G06F13/00
CPC分类号： G06F13/4291 , G06F3/061 , G06F3/0611 , G06F3/0619 , G06F3/0658 , G06F3/0661 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/1081 , G06F13/102 , G06F13/1689 , G06F13/364 , G06F13/4072 , G06F13/4086 , G06F13/4234 , G06F13/4243 , G06F2206/1014 , G06F2212/7201 , G11C5/04 , G11C5/063 , G11C7/1048 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C16/32 , G11C19/00 , H03K19/00384 , H03K19/018585
摘要： An integrated circuit device is described. The integrated circuit device includes a transmitter circuit having an output driver to output data, and a register to store a value representative of an equalization co-efficient setting of the output driver. The value may be determined based on information stored in a supplemental memory device.
摘要翻译：描述集成电路器件。集成电路装置包括具有用于输出数据的输出驱动器的发送器电路和用于存储表示输出驱动器的均衡均衡设置的值的寄存器。该值可以基于存储在补充存储器件中的信息来确定。

78. 发明授权

US07051129B2 Memory device having programmable drive strength setting 有权
标题翻译：具有可编程驱动强度设置的存储器
公开(公告)号：US07051129B2
公开(公告)日：2006-05-23
申请号：US10881433
申请日：2004-06-29
申请人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
发明人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
IPC分类号： G06F13/00
CPC分类号： G06F13/4291 , G06F3/061 , G06F3/0611 , G06F3/0619 , G06F3/0658 , G06F3/0661 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/1081 , G06F13/102 , G06F13/1689 , G06F13/364 , G06F13/4072 , G06F13/4086 , G06F13/4234 , G06F13/4243 , G06F2206/1014 , G06F2212/7201 , G11C5/04 , G11C5/063 , G11C7/1048 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C16/32 , G11C19/00 , H03K19/00384 , H03K19/018585
摘要： Bus communications are optimized by adjusting signal characteristics in accordance with one or more topography dependent parameters. In a bus transmitter, a transmit signal characteristic is adjusted in accordance with a topography dependent parameter. A port in the bus transmitter receives the topography dependent parameter for later use by the parameter adjustment circuitry. The parameter adjustment circuitry adjusts a parameter control signal in accordance with the topography dependent parameter, which is coupled to the output driver. Prior to driving an output signal onto a bus, the output driver adjusts the transmit signal characteristic in accordance with the parameter control signal. Similarly, in a bus receiver, a receive signal characteristic is adjusted in response to a topography dependent parameter.
摘要翻译：通过根据一个或多个地形相关参数调整信号特性来优化总线通信。在总线发送器中，根据地形相关参数来调整发送信号特性。总线发射器中的端口接收地形相关参数，供以后由参数调整电路使用。参数调整电路根据与输出驱动器耦合的地形相关参数来调整参数控制信号。在将输出信号驱动到总线之前，输出驱动器根据参数控制信号调整发送信号特性。类似地，在总线接收器中，响应于地形相关参数来调整接收信号特性。

79. 发明授权

US07005939B2 Input/output circuit with on-chip inductor to reduce parasitic capacitance 有权
标题翻译：具有片上电感的输入/输出电路，以减少寄生电容
公开(公告)号：US07005939B2
公开(公告)日：2006-02-28
申请号：US10431147
申请日：2003-05-06
申请人： Jared L. Zerbe , Vladimir M. Stojanovic , Mark A. Horowitz , Pak S. Chau
发明人： Jared L. Zerbe , Vladimir M. Stojanovic , Mark A. Horowitz , Pak S. Chau
IPC分类号： H01P5/12
CPC分类号： H04L25/0278 , H01L27/0251 , H01L2224/48091 , H01L2924/13091 , H01L2924/30107 , H01L2924/3011 , H04L25/0272 , H04L25/028 , H04L25/0292 , H04L25/0298 , H01L2924/00014 , H01L2924/00
摘要： An I/O circuit disposed on an integrated circuit substrate and having reduced parasitic capacitance. The I/O circuit includes a signal line segmented into a first signal line segment and a second signal line segment, and an inductive structure disposed between the first and second signal line segments. An on-chip termination element is coupled to the first signal line segment, and an electrostatic discharge (ESD) element is coupled to the second signal line segment.
摘要翻译：布置在集成电路基板上并具有降低的寄生电容的I / O电路。 I / O电路包括被分割成第一信号线段和第二信号线段的信号线，以及设置在第一和第二信号线段之间的感应结构。片上终端元件耦合到第一信号线段，并且静电放电（ESD）元件耦合到第二信号线段。

80. 发明授权

US06965262B2 Method and apparatus for receiving high speed signals with low latency 失效
标题翻译：用于接收低延迟的高速信号的方法和装置
公开(公告)号：US06965262B2
公开(公告)日：2005-11-15
申请号：US10123370
申请日：2002-04-15
申请人： Jared L. Zerbe
发明人： Jared L. Zerbe
IPC分类号： G11C7/10 , H04L7/033 , H04L25/02 , H04L25/03 , G06F7/64
CPC分类号： H04L25/0276 , G11C7/02 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/1096 , G11C7/22 , G11C7/222 , G11C8/10 , H03K3/356034 , H03K5/131 , H03K5/133 , H03K17/162 , H03K19/00323 , H03K19/018528 , H03K2005/00065 , H03M5/20 , H04L7/0332 , H04L25/028 , H04L25/0292 , H04L25/03878
摘要： An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time interval to produce an output voltage. A sense amplifier samples and converts the output voltage of the integrator to a logic signal; and a latch stores the logic signal. In an alternate embodiment, a preamplifier conditions the input signal prior to being integrated. In another embodiment using multiple receivers, circuitry is added to the receiver to compensate for timing errors associated with the distribution of the timing signals. In yet another embodiment, the integrator is coupled to an equalization circuit that compensates for intersymbol interference. In another embodiment, another circuit compensates for accumulated voltage offset errors in the integrator.
摘要翻译：一种用于接收具有低输入到输出等待时间的宽共模范围的高速信号的装置和方法。在一个实施例中，接收机包括积分器，以在积分时间间隔期间根据输入信号累积电荷以产生输出电压。读出放大器对积分器的输出电压进行采样并转换为逻辑信号; 并且锁存器存储逻辑信号。在替代实施例中，前置放大器在被积分之前调节输入信号。在使用多个接收机的另一实施例中，将电路添加到接收机以补偿与定时信号的分布相关联的定时误差。在另一个实施例中，积分器耦合到补偿符号间干扰的均衡电路。在另一个实施例中，另一个电路补偿积分器中的累积电压偏移误差。

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