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71. 发明授权

US06970999B2 Counting latencies of an instruction table flush, refill and instruction execution using a plurality of assigned counters 失效
标题翻译：使用多个分配的计数器计数指令表的等待时间，刷新，补充和指令执行
公开(公告)号：US06970999B2
公开(公告)日：2005-11-29
申请号：US10210415
申请日：2002-07-31
申请人： Toshihiko Kurihara , Hung Qui Le , Alexander Erik Mericas , Robert Dominick Mirabella , Hideki Mitsubayashi , Michitaka Okuno , Masahiro Tokoro
发明人： Toshihiko Kurihara , Hung Qui Le , Alexander Erik Mericas , Robert Dominick Mirabella , Hideki Mitsubayashi , Michitaka Okuno , Masahiro Tokoro
IPC分类号： G06F9/38 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3885 , G06F9/3836 , G06F9/3855
摘要： A method and system for analyzing cycles per instruction (CPI) performance in a processor. A completion table corresponds to the instructions in a group to be processed by the processor. An empty completion table indicates that there has been some type of catastrophe that caused a table flush. While the table is empty, a performance monitoring counter (PMC), located in a performance monitoring unit (PMU) in the processor, counts the number of clock cycles that the table is empty. Preferably, a separate PMC is utilized depending on the reason that the completion table is empty. A second PMC likewise counts the number of clock cycles spent re-filling the empty completion table. A third PMC counts the number of clock cycles spent actually executing the instructions in the completion table. The information in the PMC's can be used to evaluate the true cause for degradation of CPI performance.
摘要翻译：一种用于分析处理器中每条指令（CPI）性能的循环的方法和系统。完成表对应于要由处理器处理的组中的指令。一个空的完成表表明有一些类型的灾难导致表冲洗。当表为空时，位于处理器中的性能监视单元（PMU）中的性能监视计数器（PMC）会计数表为空的时钟周期数。优选地，根据完成表为空的原因，使用单独的PMC。第二个PMC同样计算重新填充空完成表的时钟周期数。第三个PMC计算在完成表中实际执行指令花费的时钟周期数。 PMC中的信息可用于评估CPI性能下降的真正原因。

72. 发明授权

US06658555B1 Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipeline 有权
公开(公告)号：US06658555B1
公开(公告)日：2003-12-02
申请号：US09435077
申请日：1999-11-04
申请人： James Allan Kahle , Hung Qui Le , Charles Roberts Moore , David James Shippy , Larry Edward Thatcher
发明人： James Allan Kahle , Hung Qui Le , Charles Roberts Moore , David James Shippy , Larry Edward Thatcher
IPC分类号： G06F930
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/3865 , G06F9/3867 , G06F9/3885
摘要： A microprocessor and related method and data processing system are disclosed. The microprocessor includes a dispatch unit suitable for issuing an instruction executable by the microprocessor, an execution pipeline configured to receive the issued instruction, and a pending instruction unit. The pending instruction unit includes a set of pending instruction entries. A copy of the issued instruction is maintained in one of the set of pending instruction entries. The execution pipeline is adapted to record, in response detecting to a condition preventing the instruction from successfully completing one of the stages in the pipeline during a current cycle, an exception status with the copy of the instruction in the pending instruction unit and to advance the instruction to a next stage in the pipeline in the next cycle thereby preventing the condition from stalling the pipeline. Preferably, the dispatch unit, in response to the instruction finishing pipeline execution with an exception status, is adapted to use the copy of the instruction to re-issue the instruction to the execution pipeline in a subsequent cycle. In one embodiment, the dispatch unit is adapted to deallocate the copy of the instruction in the pending instruction unit in response to the instruction successfully completing pipeline execution. The pending instruction unit may detect successful completion of the instruction by detecting when the instruction has been pending for a predetermined number of cycles without recording an exception status. In this embodiment, each entry in the pending instruction unit may include a timer field comprising a set of bits wherein the number of bits in the time field equals the predetermined number of cycles. The pending instruction unit may set, in successive cycles, successive bits in the timer field such that successful completion of an instruction is indicated when a last bit in the time field is set. In one embodiment, pending instruction unit includes a set of copies of instructions corresponding to each of a set of instructions pending in the execution pipeline at any given time. In various embodiments, the execution pipeline may comprise a load/store pipeline, a floating point pipeline, or a fixed point pipeline.

73. 发明授权

US06336183B1 System and method for executing store instructions 失效
标题翻译：执行存储指令的系统和方法
公开(公告)号：US06336183B1
公开(公告)日：2002-01-01
申请号：US09259140
申请日：1999-02-26
申请人： Hung Qui Le , Robert Greg McDonald , David James Shippy , Larry Edward Thatcher
发明人： Hung Qui Le , Robert Greg McDonald , David James Shippy , Larry Edward Thatcher
IPC分类号： G06F9312
CPC分类号： G06F9/3889 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857
摘要： In a processor, store instructions are divided or cracked into store data and store address generation portions for separate and parallel execution within two execution units. The address generation portion of the store instruction is executed within the load store unit, while the store data portion of the instruction is executed in an execution unit other than the load store unit. If the store instruction is a fixed point execution unit, then the store data portion is executed within the fixed point unit. If the store instruction is a floating point store instruction, then the store data portion of the store instruction is executed within the floating point unit.
摘要翻译：在处理器中，存储指令被划分或破解为存储数据，并且存储地址生成部分用于在两个执行单元内进行单独和并行执行。存储指令的地址生成部分在加载存储单元内执行，而指令的存储数据部分在除加载存储单元之外的执行单元中执行。如果存储指令是固定点执行单元，则在固定点单元内执行存储数据部分。如果存储指令是浮点存储指令，则在浮点单元内执行存储指令的存储数据部分。

74. 发明授权

US06286094B1 Method and system for optimizing the fetching of dispatch groups in a superscalar processor 有权
标题翻译：用于优化超标量处理器中调度组的获取的方法和系统
公开(公告)号：US06286094B1
公开(公告)日：2001-09-04
申请号：US09263663
申请日：1999-03-05
申请人： John Edward Derrick , Lee Evan Eisen , Hung Qui Le , Brian R. Konigsburg
发明人： John Edward Derrick , Lee Evan Eisen , Hung Qui Le , Brian R. Konigsburg
IPC分类号： G06F930
CPC分类号： G06F9/382 , G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857
摘要： A method and system for determining if a dispatch slot is required in a processing system is disclosed. The method and system comprises a plurality of predecode bits to provide routing information and utilizing the predecode bits to allow instructions to be directed to specific decode slots and to obey dispatch constraints without examining the instructions. The purpose of this precode encoding system scheme is to provide the most information possible about the grouping of the instructions without increasing the complexity of the logic which uses this information for decode and group formation. In a preferred embodiment, pre-decode bits for each instruction that may be issued in parallel are analyzed and the multiplexer controls are retained for each of the possible starting positions within the stream of instructions.
摘要翻译：公开了一种用于确定处理系统中是否需要调度槽的方法和系统。所述方法和系统包括多个预解码比特，以提供路由信息并利用所述预解码比特来允许指令被引导到特定解码时隙，并且在不检查指令的情况下服从调度约束。该预编码系统方案的目的是为了提供关于指令分组的可能性最大的信息，而不增加使用该信息进行解码和组形成的逻辑的复杂性。在优选实施例中，分析可以并行发出的每个指令的预解码位，并且为指令流内的每个可能的起始位置保留多路复用器控制。

75. 发明授权

US5963723A System for pairing dependent instructions having non-contiguous addresses during dispatch 失效
标题翻译：用于配对在调度期间具有不连续地址的相关指令的系统
公开(公告)号：US5963723A
公开(公告)日：1999-10-05
申请号：US827076
申请日：1997-03-26
申请人： Hung Qui Le
发明人： Hung Qui Le
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F9/3885
摘要： In a superscalar data processing system, instructions, which are dependent upon each other, are paired for dispatch to a plurality of execution units. Pairing results in instructions being paired that may not necessarily be located at contiguous addresses. Pairing may be performed by comparing general purpose register source pointers and general purpose register target pointers of the various instructions. Pairing may also be accomplished by comparing target identification numbers of source operands with target identification numbers of target instructions.
摘要翻译：在超标量数据处理系统中，依赖于彼此的指令被配对用于调度到多个执行单元。配对导致配对的指令可能不一定位于连续的地址。可以通过比较各种指令的通用寄存器源指针和通用寄存器目标指针来执行配对。配对也可以通过将源操作数的目标识别号与目标指令的目标识别号进行比较来实现。

76. 发明授权

US5870582A Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched 失效
标题翻译：在发出指令前完成不可中断指令的方法和装置
公开(公告)号：US5870582A
公开(公告)日：1999-02-09
申请号：US829671
申请日：1997-03-31
申请人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
发明人： Hoichi Cheong , Hung Qui Le , John Stephen Muhich , Steven Wayne White
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3857 , G06F9/3863
摘要： In a method and apparatus for allocating processor resources in a data processing system, instructions are dispatched and tagged for processing. A processor resource snoops to obtain execution results for the tagged instructions. Such an instruction is logically "finished" in response to determining that it will not cause an interrupt (which includes not changing the sequence of completing instructions), and "completed" in response to finishing all earlier dispatched instructions. Information is entered for such an instructions in rename buffer in response to the instruction targeting an architected register, and such a rename buffer entry is released in response to completing the entry's instruction. The rename buffer may comprise a history buffer. Also, information for the instructions is entered in a completion queue in response to dispatching the instructions, and the queue entry for such an instruction is released in response to completion of the instruction. Also, the instructions are grouped, a group having solely a single interruptible instruction, and further including non-interruptible instructions dispatched following the interruptible instruction. Thus, there may be numerous non-interruptible instructions in such a group. Such an interruptible instruction is logically "finished" in response to determining that it will not cause an interrupt, and "completed" in response to finishing all earlier dispatched instructions. Such a non-interruptible instruction is logically "finished" and "completed" in response to completion of its associated interruptible instruction, so that such a non-interruptible instruction may complete before it is dispatched.
摘要翻译：在用于在数据处理系统中分配处理器资源的方法和装置中，调度和标记用于处理的指令。处理器资源被窥探以获得标记指令的执行结果。响应于确定不会导致中断（其不包括改变完成指令的顺序），并且响应于完成所有先前分派的指令而“完成”，这样的指令在逻辑上“完成”。响应于针对架构化寄存器的指令，在重命名缓冲器中输入这样的指令的信息，并且响应于完成条目的指令而释放这样的重命名缓冲器条目。重命名缓冲器可以包括历史缓冲器。此外，响应于分派指令，将指令的信息输入到完成队列中，并且响应于指令的完成而释放这样的指令的队列条目。此外，指令被分组，仅具有单个可中断指令的组，并且还包括在可中断指令之后分派的不可中断指令。因此，在这样的组中可能存在许多不可中断的指令。这种可中断指令在逻辑上“完成”以响应于确定它不会引起中断，并且响应于完成所有先前分派的指令而“完成”。响应于其相关联的可中断指令的完成，这种不可中断指令被逻辑地“完成”和“完成”，使得这种不可中断指令可以在其被分派之前完成。

77. 发明授权

US5864341A Instruction dispatch unit and method for dynamically classifying and issuing instructions to execution units with non-uniform forwarding 失效
标题翻译：指令调度单元和方法，用于向不均匀转发的执行单元动态分类和发布指令
公开(公告)号：US5864341A
公开(公告)日：1999-01-26
申请号：US761875
申请日：1996-12-06
申请人： Troy Neal Hicks , Hung Qui Le , John Stephen Muhich , Steven Wayne White
发明人： Troy Neal Hicks , Hung Qui Le , John Stephen Muhich , Steven Wayne White
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3891 , G06F9/3824 , G06F9/3853 , G06F9/3885
摘要： The present invention is directed to a method and apparatus for dispatching instructions in an information handling system. A pre-execution queue stores instructions, and at least one execution cluster is operably coupled to the pre-execution queue. An execution cluster comprises an early execution unit for executing a first instruction dispatched from the pre-execution queue to generate and forward a first result and a late execution unit for executing a second instruction dispatched from the pre-execution queue to generate and forward a second result after the first execution unit forwards the first result. The invention further includes circuitry operably associated with the pre-execution queue, and a method for prioritizing the order in which the instructions in the pre-execution queue are dispatched to the execution cluster.
摘要翻译：本发明涉及一种用于在信息处理系统中调度指令的方法和装置。预执行队列存储指令，并且至少一个执行群集可操作地耦合到预执行队列。执行群包括一个早期执行单元，用于执行从预执行队列发出的第一指令，以产生和转发第一结果;以及后期执行单元，用于执行从预执行队列发出的第二指令，以产生和转发第二个第一执行单元转发第一个结果后的结果。本发明还包括可操作地与预执行队列相关联的电路，以及用于将预执行队列中的指令分派到执行群集的顺序的优先级的方法。

78. 发明授权

US5841999A Information handling system having a register remap structure using a content addressable table 失效
标题翻译：具有使用内容寻址表的寄存器重映射结构的信息处理系统
公开(公告)号：US5841999A
公开(公告)日：1998-11-24
申请号：US633327
申请日：1996-04-17
申请人： Hung Qui Le , Erdem Hokenek
发明人： Hung Qui Le , Erdem Hokenek
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： An information handling system includes an instruction unit, one or more execution units, a memory management unit, connected to the instruction unit, to a memory system, a cache management unit, one or more levels of cache memory associated with the one or more execution units, one or more I/O controllers connected to a bus which connects to the execution units and to the memory systems and to cache, and a completion unit for tracking sequence of instruction dispatch and instruction completion. The completion unit includes a Content Addressable Register Buffer Assignment Table, a Register Status Table, an Instruction Queue, and a Completion Table to control order of execution and completion of instructions in a sequence dependent on availability of operands.
摘要翻译：信息处理系统包括指令单元，一个或多个执行单元，连接到指令单元的存储器管理单元，存储器系统，高速缓存管理单元，与一个或多个执行相关联的一个或多个高速缓冲存储器级连接到连接到执行单元和存储器系统的总线的一个或多个I / O控制器和缓存，以及用于跟踪指令分派和指令完成的顺序的完成单元。完成单元包括内容可寻址寄存器缓冲器分配表，寄存器状态表，指令队列和完成表，以根据操作数的可用性来控制顺序执行和完成指令。

79. 发明授权

US5805906A Method and apparatus for writing information to registers in a data processing system using a number of registers for processing instructions 失效
标题翻译：使用多个用于处理指令的寄存器在数据处理系统中向寄存器写入信息的方法和装置
公开(公告)号：US5805906A
公开(公告)日：1998-09-08
申请号：US729308
申请日：1996-10-15
申请人： Hoichi Cheong , Hung Qui Le , Paul Joseph Jordan
发明人： Hoichi Cheong , Hung Qui Le , Paul Joseph Jordan
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46
CPC分类号： G06F9/3855 , G06F9/30141 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F9/3861
摘要： In a data processing system using a number of registers for processing instructions, a method and apparatus for writing information to the registers. Ports are accessed for writing back to processor registers, information ("results") resulting from and associated with executing instructions. Certain of the results are stored for restoring to the registers. In response to an interruption at least one of the ports is accessed for restoring stored results to the registers. Accesses to the ports are arbitrated in response to comparing writeback and restoration results. A result includes identification of the instruction the result is associated with (a "TID"), and a register that is targeted by the result (a "TR"). The comparing includes comparing TID's and TR's for the results.
摘要翻译：在使用多个用于处理指令的寄存器的数据处理系统中，用于将信息写入寄存器的方法和装置。访问端口以写回处理器寄存器，由执行指令产生并与执行指令相关联的信息（“结果”）。某些结果存储用于恢复到寄存器。响应于中断，访问至少一个端口以将存储的结果恢复到寄存器。响应于回写和恢复结果的比较，对端口的访问进行仲裁。结果包括与结果相关联的指令的识别（“TID”）和由结果（“TR”）定向的寄存器。比较包括比较TID和TR的结果。

80. 发明授权

US07380066B2 Store stream prefetching in a microprocessor 失效
标题翻译：在微处理器中存储流预取
公开(公告)号：US07380066B2
公开(公告)日：2008-05-27
申请号：US11054871
申请日：2005-02-10
申请人： John Barry Griswell, Jr. , Hung Qui Le , Francis Patrick O'Connell , William J. Starke , Jeffrey Adam Stuecheli , Albert Thomas Williams
发明人： John Barry Griswell, Jr. , Hung Qui Le , Francis Patrick O'Connell , William J. Starke , Jeffrey Adam Stuecheli , Albert Thomas Williams
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F12/0862 , G06F9/30043 , G06F9/30047 , G06F9/383 , G06F12/0811
摘要： In a microprocessor having a load/store unit and prefetch hardware, the prefetch hardware includes a prefetch queue containing entries indicative of allocated data streams. A prefetch engine receives an address associated with a store instruction executed by the load/store unit. The prefetch engine determines whether to allocate an entry in the prefetch queue corresponding to the store instruction by comparing entries in the queue to a window of addresses encompassing multiple cache blocks, where the window of addresses is derived from the received address. The prefetch engine compares entries in the prefetch queue to a window of 2M contiguous cache blocks. The prefetch engine suppresses allocation of a new entry when any entry in the prefetch queue is within the address window. The prefetch engine further suppresses allocation of a new entry when the data address of the store instruction is equal to an address in a border area of the address window.
摘要翻译：在具有加载/存储单元和预取硬件的微处理器中，预取硬件包括预取队列，其包含指示分配的数据流的条目。预取引擎接收与由加载/存储单元执行的存储指令相关联的地址。预取引擎通过将队列中的条目与包含多个高速缓存块的地址的窗口进行比较来确定是否对与存储指令相对应的预取队列中的条目进行分配，其中地址窗口从接收到的地址导出。预取引擎将预取队列中的条目与两个连续高速缓存块的窗口进行比较。当预取队列中的任何条目都在地址窗口内时，预取引擎抑制新条目的分配。当存储指令的数据地址等于地址窗口的边界区域中的地址时，预取引擎进一步抑制新条目的分配。

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