专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US08445374B2 Soft error rate mitigation by interconnect structure 有权
标题翻译：通过互连结构缓解软错误率
公开(公告)号：US08445374B2
公开(公告)日：2013-05-21
申请号：US13361057
申请日：2012-01-30
申请人： Mukta G. Farooq , Ian D. Melville , Kevin S. Petrarca
发明人： Mukta G. Farooq , Ian D. Melville , Kevin S. Petrarca
IPC分类号： H01L21/44
CPC分类号： H01L24/16 , H01L24/11 , H01L24/13 , H01L24/81 , H01L2224/05001 , H01L2224/05023 , H01L2224/05568 , H01L2224/10126 , H01L2224/1147 , H01L2224/1148 , H01L2224/1191 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/81801 , H01L2924/00013 , H01L2924/01005 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/15787 , H01L2224/29099 , H01L2924/00 , H01L2224/05541 , H01L2224/05005
摘要： A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.
摘要翻译：一种方法产生一种结构，其包括通过柱和开口连接到集成电路芯片的载体。因此，在这种结构中，至少一个导电柱与集成电路芯片的表面延伸一段距离或高度，并且阻挡层围绕导电柱的下部，使得阻挡层覆盖柱的高度的至少一部分最接近芯片表面。载体中至少有一个开口足够大以容纳导电柱和屏障，并且导电柱和屏障位于开口中。在开口的底部使用焊料将导电柱连接到开口的底部。屏障防止焊料接触由屏障保护的导电柱的部分。

72. 发明授权

US08349729B2 Hybrid bonding interface for 3-dimensional chip integration 有权
标题翻译：混合键合界面，用于三维芯片集成
公开(公告)号：US08349729B2
公开(公告)日：2013-01-08
申请号：US13418716
申请日：2012-03-13
申请人： Karl W. Barth , Ricardo A. Donaton , Spyridon Galis , Kevin S. Petrarca , Shahab Siddiqui
发明人： Karl W. Barth , Ricardo A. Donaton , Spyridon Galis , Kevin S. Petrarca , Shahab Siddiqui
IPC分类号： H01L21/4763
CPC分类号： H01L23/5389 , H01L21/76898 , H01L24/80 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/9202 , H01L2924/12044
摘要： Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions.
摘要翻译：第一基板和第二基板中的每一个包括具有耐扩散电介质材料如氮化硅的表面。凹陷区域形成在耐扩散电介质材料中，并且填充有可粘结介电材料。第一和第二基板中的金属焊盘和可接合的介质材料部分的图案可以具有镜面对称性。第一和第二基板通过金属焊盘和可接合的介电材料部分之间的触点之间的触点进行物理接触和接合。通过基底通孔（TSV）结构通过键合介电材料部分形成。位于TSV结构周围的每对键合的电介质材料部分之间的界面由两个扩散电阻的介电材料层封装，使得接合界面处的金属的扩散被包含在每对键合介电材料部分内。

73. 发明申请

US20120304138A1 CIRCUIT DESIGN CHECKING FOR THREE DIMENSIONAL CHIP TECHNOLOGY 有权
标题翻译：电路设计检查三维芯片技术
公开(公告)号：US20120304138A1
公开(公告)日：2012-11-29
申请号：US13113421
申请日：2011-05-23
申请人： Mukta G. Farooq , John A. Griesemer , William Francis Landers , Kevin S. Petrarca , Richard Paul Volant
发明人： Mukta G. Farooq , John A. Griesemer , William Francis Landers , Kevin S. Petrarca , Richard Paul Volant
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A tool that allows three dimensional chip circuit designs to be checked subsequent to 3D design layer mirroring. The 3D chip design is converted to a corresponding 2D chip design by mirroring one or more design layers from the mirrored side of a 3D design and merging those design layers with unmirrored design layers from the unmirrored side of a 3D design. The converted circuit design can be processed by standard verification checks. The tool may also receive design layers corresponding to an integrated circuit that will pass through multiple semiconductor chips. Each design cell is examined to determine if it corresponds to a mirrored or unmirrored side of its respective semiconductor chip. If the respective design cell corresponds to the mirrored side, the design cell is mirrored. All mirrored cells are then merged with the unmirrored design cells in the correct order. The merged design is processed by standard verification checks. The tool also has the capability to create terminal metal abstracts for two adjoining chips. One of the abstracts is mirrored and then merged with the other for connectivity and alignment checking.
摘要翻译：一种允许在3D设计层镜像之后检查三维芯片电路设计的工具。通过从3D设计的镜像侧镜像一个或多个设计层，将3D芯片设计转换为相应的2D芯片设计，并将这些设计层与未设计的设计层从3D设计的非镜面合并。转换电路设计可以通过标准验证检查进行处理。该工具还可以接收对应于将通过多个半导体芯片的集成电路的设计层。检查每个设计单元以确定它是否对应于其相应的半导体芯片的镜像或非镜像侧。如果相应的设计单元对应于镜像侧，则设计单元被镜像。然后所有镜像单元格以正确的顺序与未设计的设计单元合并。合并设计通过标准验证检查进行处理。该工具还可以为两个相邻的芯片创建终端金属摘要。其中一个摘要被镜像，然后与另一个摘要进行连接和对齐检查。

74. 发明申请

US20120126937A1 ASSET MANAGEMENT INFRASTRUCTURE 有权
标题翻译：资产管理基础设施
公开(公告)号：US20120126937A1
公开(公告)日：2012-05-24
申请号：US13296242
申请日：2011-11-15
申请人： Lawrence A. Clevenger , Rainer K. Krause , Kevin S. Petrarca , Carl J. Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Rainer K. Krause , Kevin S. Petrarca , Carl J. Radens , Brian C. Sapp
IPC分类号： G08B29/00
CPC分类号： G08B13/14 , G06Q10/087
摘要： Asset management for control of electric appliances comprises a keycode unit and an equipment unit embedded in an appliance. The keycode unit is located in a protected environment and relates to an asset management area. The equipment unit may store an appliance identification code. The keycode unit and the equipment unit may be in communication contact, whereby the equipment unit sends positioning coordinates to the keycode unit, and wherein the equipment unit is adapted to lock the appliance via the lock unit, in response to a lock signal that the equipment unit receives from the keycode unit, if the appliance moves outside the asset management area.
摘要翻译：用于控制电器的资产管理包括密码单元和嵌入在器具中的设备单元。键码单元位于受保护的环境中，与资产管理区域有关。设备单元可以存储设备标识码。键码单元和设备单元可以是通信接触的，由此设备单元向键码单元发送定位坐标，并且其中设备单元适于经由锁定单元锁定设备，响应于锁定信号，设备如果设备移动到资产管理区域外，则单元从密钥单元接收。

75. 发明申请

US20100163949A1 VERTICAL METAL-INSULATOR-METAL (MIM) CAPACITOR USING GATE STACK, GATE SPACER AND CONTACT VIA 有权
标题翻译：垂直金属绝缘子金属（MIM）电容器使用盖板，隔板和接触器
公开(公告)号：US20100163949A1
公开(公告)日：2010-07-01
申请号：US12344697
申请日：2008-12-29
申请人： Ramachandra Divakaruni , Mukta G. Farooq , Jeffrey P. Gambino , Kevin S. Petrarca
发明人： Ramachandra Divakaruni , Mukta G. Farooq , Jeffrey P. Gambino , Kevin S. Petrarca
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L28/60 , H01L21/76897 , H01L23/485 , H01L27/0629 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure including a vertical metal-insulator-metal capacitor, and a method for fabricating the semiconductor structure including the vertical metal-insulator-metal capacitor, each use structural components from a dummy metal oxide semiconductor field effect transistor located and formed over an isolation region located over a semiconductor substrate. The dummy metal oxide field effect transistor may be formed simultaneously with a metal oxide semiconductor field effect transistor located over a semiconductor substrate that includes the isolation region. The metal-insulator-metal capacitor uses a gate as a capacitor plate, a uniform thickness gate spacer as a gate dielectric and a contact via as another capacitor plate. The uniform thickness gate spacer may include a conductor layer for enhanced capacitance. A mirrored metal-insulator-metal capacitor structure that uses a single contact via may also be used for enhanced capacitance.
摘要翻译：包括垂直金属 - 绝缘体 - 金属电容器的半导体结构以及包括垂直金属 - 绝缘体 - 金属电容器的半导体结构的制造方法，每个都使用位于隔离层上并形成的虚设金属氧化物半导体场效应晶体管的结构部件区域位于半导体衬底上。虚拟金属氧化物场效应晶体管可以与位于包括隔离区域的半导体衬底之上的金属氧化物半导体场效应晶体管同时形成。金属 - 绝缘体 - 金属电容器使用栅极作为电容器板，均匀厚度的栅极间隔物作为栅极电介质和作为另一个电容器板的接触通孔。均匀厚度的栅极间隔物可以包括用于增强电容的导体层。使用单个接触通孔的镜像金属 - 绝缘体 - 金属电容器结构也可用于增强电容。

76. 发明授权

US07468124B2 Method and apparatus for copper corrosion prevention during wet clean 失效
标题翻译：湿法清洁时铜腐蚀预防的方法和装置
公开(公告)号：US07468124B2
公开(公告)日：2008-12-23
申请号：US11382802
申请日：2006-05-11
申请人： Nancy A. Greco , Kimberly F. Hooper , Kevin S. Petrarca
发明人： Nancy A. Greco , Kimberly F. Hooper , Kevin S. Petrarca
IPC分类号： C23F13/04
CPC分类号： C23F13/04 , H01L21/02063 , H01L21/67057
摘要： A method and apparatus for cleaning a wafer with a metal exposed through an insulator, through the use of a wet cleaning tank in concert with a feedback system on the potential difference between two leads of the wet cleaning tank. The cleaning tank has a bath in which the wafer and the two leads are immersed. The potential difference between the two leads is regulated when the feedback system detects a change in the potential across the two leads.
摘要翻译：一种通过使用湿式清洗槽与反馈系统一起使用通过绝缘子暴露的金属来清洁晶片的方法和装置，该方法和装置关于湿式清洗槽的两根引线之间的电位差。清洗槽具有浸没晶片和两根引线的槽。当反馈系统检测到两个引线上的电位变化时，两个引线之间的电位差被调节。

77. 发明申请

US20080156636A1 Homogeneous Copper Interconnects for BEOL 审中-公开
标题翻译： BEOL的均匀铜互连
公开(公告)号：US20080156636A1
公开(公告)日：2008-07-03
申请号：US11971488
申请日：2008-01-09
申请人： Kevin S. Petrarca , Mahadevaiyer Krishnan , Michael Lofaro , Kenneth P. Rodbell
发明人： Kevin S. Petrarca , Mahadevaiyer Krishnan , Michael Lofaro , Kenneth P. Rodbell
IPC分类号： C23C14/16
CPC分类号： H01L21/76873 , H01L21/2855 , H01L21/7684 , H01L21/76877
摘要： Defects on the edge of copper interconnects for back end of the line semiconductor devices are alleviated by an interconnect that comprises an impure copper seed layer. The impure copper seed layer covers a barrier layer, which covers an insulating layer that has an opening. Electroplated copper fills the opening in the insulating layer. Through a chemical mechanical polish, the barrier layer, the impure an impure copper seed layer derived from an electroplated copper bath copper seed layer, and the electroplated copper are planarized to the insulating layer.
摘要翻译：通过包括不纯铜种子层的互连可以减轻线半导体器件后端的铜互连边缘的缺陷。不纯铜种子层覆盖阻挡层，其覆盖具有开口的绝缘层。电镀铜填充绝缘层中的开口。通过化学机械抛光，阻挡层，不纯的由电镀铜浴铜籽晶层衍生的铜籽晶层和电镀铜平坦化到绝缘层。

78. 发明申请

US20070275552A1 STRUCTURE FOR REDUCING LATERAL FRINGE CAPACITANCE IN SEMICONDUCTOR DEVICES AND METHOD OF FORMING THE SAME 失效
标题翻译：用于减少半导体器件中的侧向电容的结构及其形成方法
公开(公告)号：US20070275552A1
公开(公告)日：2007-11-29
申请号：US11420253
申请日：2006-05-25
申请人： Lawrence A. Clevenger , Stephan Grunow , Kaushik A. Kumar , Kevin S. Petrarca , Vidhya Ramachandran , Theodorus E. Standaert
发明人： Lawrence A. Clevenger , Stephan Grunow , Kaushik A. Kumar , Kevin S. Petrarca , Vidhya Ramachandran , Theodorus E. Standaert
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a plurality of conductive lines formed within an interlevel dielectric (ILD) layer and a non-planar cap layer formed over the ILD layer and the conductive lines, wherein the cap layer is raised with respect to the conductive lines at locations between the conductive lines.
摘要翻译：半导体结构包括形成在层间电介质（ILD）层内的多个导电线和形成在ILD层和导电线之上的非平面覆盖层，其中覆盖层相对于导电线在第导线。

79. 发明授权

US09511918B2 Self-locking container 有权
标题翻译：自锁容器
公开(公告)号：US09511918B2
公开(公告)日：2016-12-06
申请号：US13340776
申请日：2011-12-30
申请人： Ira L. Allen , Lawrence A. Clevenger , Kevin S. Petrarca , Carl J. Radens
发明人： Ira L. Allen , Lawrence A. Clevenger , Kevin S. Petrarca , Carl J. Radens
IPC分类号： B65D79/02 , B65D55/10 , B65D41/04 , A61J1/03
CPC分类号： B65D79/02 , A61J1/03 , A61J2200/72 , B65D41/04 , B65D55/10 , B65D2213/00
摘要： Method and apparatus to provide a self-locking container to prevent unwanted access to materials stored in the container as a result of exposure to conditions that compromise the effectiveness or safety of the materials. A container may be threaded to receive a threaded lid, and the container may comprise a bolt movable within a channel from a retracted position, which allows the lid to be threadably connected or removed, to a locked position, which prevents removal of the lid. The bolt is movable to the locked position by a drive member, such as a bimetallic strip or a shape-memory element that drive the bolt in response to exposure to the condition that compromises the material.
摘要翻译：提供自锁容器的方法和装置，以防止由于暴露于损害材料的有效性或安全性的条件而导致存储在容器中的材料的不期望的访问。容器可以是螺纹以接收带螺纹的盖子，并且容器可以包括螺栓，该螺栓可在通道内从缩回位置移动，该缩回位置允许盖子被螺纹连接或移除到锁定位置，从而防止盖子移除。螺栓通过驱动构件（例如双金属条或形状记忆元件）可移动到锁定位置，该双金属条或形状记忆元件响应于暴露于损害材料的状况而驱动螺栓。

80. 发明授权

US08665575B2 Solar module with overheat protection 有权
标题翻译：太阳能组件具有过热保护功能
公开(公告)号：US08665575B2
公开(公告)日：2014-03-04
申请号：US13166842
申请日：2011-06-23
申请人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Krause , Zhengwen Li , Kevin S. Petrarca , Gerd Pfeiffer , Kevin Prettyman , Carl J. Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Krause , Zhengwen Li , Kevin S. Petrarca , Gerd Pfeiffer , Kevin Prettyman , Carl J. Radens , Brian C. Sapp
IPC分类号： H02H5/04
CPC分类号： H02H7/20 , H01L31/02021 , H02H5/047 , Y02E10/50
摘要： A photovoltaic module (10) with a plurality of solar cells (20) interconnected in serial and/or parallel arrangement within the module (10) is equipped with an overheat protection system (30) for suppressing damages of the photovoltaic module (10) due to defects of the solar cells (20). The overheat protection system (30) comprises a heat sensor (32) which is thermally coupled to a solar cell (20). The heat sensor (32) is physically integrated into an electrical switch (34, 36, 38) which is electrically connected to said solar cell (20).
摘要翻译：具有在模块（10）内以串联和/或并联布置互连的多个太阳能电池（20）的光伏模块（10）装备有过热保护系统（30），用于抑制光伏模块（10）的损坏涉及太阳能电池的缺陷（20）。过热保护系统（30）包括热耦合到太阳能电池（20）的热传感器（32）。热传感器（32）物理地集成在电连接到所述太阳能电池（20）的电开关（34,36,38）中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式