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71. 发明授权

US07356716B2 System and method for automatic calibration of a reference voltage 失效
标题翻译：用于自动校准参考电压的系统和方法
公开(公告)号：US07356716B2
公开(公告)日：2008-04-08
申请号：US11065549
申请日：2005-02-24
申请人： David William Boerstler , Eskinder Hailu , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： A system and system for automatic voltage calibration is presented. A voltage calibration system includes three main units, which are a voltage level trimming unit, a trim detection unit, and a trim control unit. The three units work in conjunction with each other during a trimming operation in order to identify a tap voltage that is closest to a target voltage. In one embodiment, the voltage calibration system may be used to calibrate a voltage regulator. Upon commencement of calibration, the voltage regulator's feedback loop is open, and the target voltage is selected as the input for the feedback port of the amplifier. The voltage regulator serves as a voltage comparator that compares each tap voltage to the target voltage. When the calibration is complete, regulator's feedback loop is closed and the closest tap voltage to the target voltage is used as the regulator's input.
摘要翻译：提出了一种用于自动电压校准的系统和系统。电压校准系统包括三个主要单元，它们是电压调整单元，微调检测单元和微调控制单元。三个单元在微调操作期间相互协调工作，以便识别最接近目标电压的抽头电压。在一个实施例中，电压校准系统可用于校准电压调节器。校准开始后，电压调节器的反馈回路打开，目标电压被选为放大器反馈端口的输入。电压调节器用作将每个抽头电压与目标电压进行比较的电压比较器。当校准完成时，调节器的反馈回路闭合，并将最接近的目标电压的抽头电压用作调节器的输入。

72. 发明授权

US07333905B2 Method and apparatus for measuring the duty cycle of a digital signal 有权
标题翻译：用于测量数字信号占空比的方法和装置
公开(公告)号：US07333905B2
公开(公告)日：2008-02-19
申请号：US11383570
申请日：2006-05-16
申请人： David William Boerstler , Eskinder Hailu , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G01R29/02
CPC分类号： G01R29/02 , G01R31/31725 , G01R31/31726
摘要： The disclosed methodology and apparatus measures the duty cycle of a clock signal. A variable duty cycle circuit receives a clock signal from a clock signal generator. The variable duty cycle circuit adjusts the duty cycle of the clock signal by an amount dependent on a duty cycle index value that it receives. The variable duty cycle circuit supplies a duty-cycle adjusted clock signal to a divider circuit. The apparatus sweeps the frequency of the clock signal from a starting value up to a maximum frequency above which the divider circuit fails. The apparatus then determines the duty cycle of the duty-cycle adjusted clock signal from the maximum frequency.
摘要翻译：所公开的方法和装置测量时钟信号的占空比。可变占空比电路从时钟信号发生器接收时钟信号。可变占空比电路根据其接收的占空比指数值来调整时钟信号的占空比。可变占空比电路将占空比调整的时钟信号提供给分频器电路。该装置将时钟信号的频率从起始值扫描到高于分频器电路故障的最大频率。然后，该装置从最大频率确定占空比调整的时钟信号的占空比。

73. 发明申请

US20080018408A1 INTERLEAVED VOLTAGE CONTROLLED OSCILLATOR 有权
标题翻译：交流电压控制振荡器
公开(公告)号：US20080018408A1
公开(公告)日：2008-01-24
申请号：US11458753
申请日：2006-07-20
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
IPC分类号： H03K3/03
CPC分类号： H03L7/0995 , H03K3/0315 , H03K5/133
摘要： An interleaved voltage-controlled oscillator (VCO) is disclosed. The VCO includes a ring circuit comprising a series connection of main logic inverter gates, a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates, at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistors, the field effect transistor responsive to a compensating voltage input that is proportional to temperature, and an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature. Each delay element includes a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages, and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate.
摘要翻译：公开了一种交错压控振荡器（VCO）。 VCO包括环形电路，其包括主逻辑反相器门的串联连接，与主逻辑反相器门的选定序列并联连接的多个延迟元件，至少一个温度补偿电路，包括与一个或多个场效应晶体管，所述场效应晶体管响应于与温度成比例的补偿电压输入;以及电子电路，其与所述至少一个温度补偿电路进行信号通信，并且被配置为提供响应于温度的电压信号。每个延迟元件包括前馈部分，其包括用于响应于一个或多个控制电压来调节通过前馈元件的信号传输的控制，以及比例部分，包括用于调节通过至少一个逻辑反相器门的信号传输的控制。

74. 发明申请

US20070075370A1 Thermal sensing method and apparatus using existing ESD devices 有权
标题翻译：使用现有ESD器件的热感测方法和设备
公开(公告)号：US20070075370A1
公开(公告)日：2007-04-05
申请号：US11242675
申请日：2005-10-04
申请人： David Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
IPC分类号： H01L23/62
CPC分类号： G01K7/01 , G01K2217/00
摘要： The present invention provides a method, an apparatus, and a computer program product for measuring the temperature of a microprocessor through the use of ESD circuitry. The present invention uses diodes and an I/O pad within ESD circuits to determine the temperature at the location of the ESD circuitry. First, a current measuring device connects to a diode. A user or a computer program disables the protected component or circuitry, and subsequently applies a predetermined voltage to the I/O pad. This creates a reverse saturation current through the diode, which is measured by the current measuring device. From this current the user or a computer program determines the temperature of the microprocessor at the diode through the use of a graphical representation of diode reverse saturation current and corresponding temperature.
摘要翻译：本发明提供了一种通过使用ESD电路来测量微处理器的温度的方法，装置和计算机程序产品。本发明在ESD电路中使用二极管和I / O焊盘来确定ESD电路位置处的温度。首先，电流测量装置连接到二极管。用户或计算机程序禁用受保护的组件或电路，然后将预定电压施加到I / O焊盘。这通过二极管产生反向饱和电流，由电流测量装置测量。从该电流，用户或计算机程序通过使用二极管反向饱和电流和相应温度的图形表示来确定微处理器在二极管处的温度。

75. 发明申请

US20070071155A1 Information handling system capable of detecting frequency lock of signals downstream from a signal synthesized by frequency synthesizer 失效
标题翻译：信号处理系统能够检测由频率合成器合成的信号下行信号的频率锁定
公开(公告)号：US20070071155A1
公开(公告)日：2007-03-29
申请号：US11236834
申请日：2005-09-27
申请人： David Boerstler , Matthew Fernsler , Eskinder Hailu , Jieming Qi , Mack Riley
发明人： David Boerstler , Matthew Fernsler , Eskinder Hailu , Jieming Qi , Mack Riley
IPC分类号： H04B17/00 , H03D3/24
CPC分类号： G06F1/10 , H03L7/095
摘要： An information handling system including a frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.
摘要翻译：公开了一种包括频率合成器锁定检测系统的信息处理系统，其将分频网络上的频率合成器输出信号分配到一个或多个接收器电路。分配网络可能表现出延迟和其他失真，这些失真可能导致下游信号到达接收器电路，同时使用频率合成器输出信号和控制合成器输出信号频率的参考时钟信号来失去频率锁定。锁定检测系统测试下行信号以确定下游信号是否相对于确定频率合成器的工作频率的参考时钟呈现锁定。以这种方式，可以在一个实施例中精确地评估下行信号到参考时钟信号的锁定。

76. 发明申请

US20070043798A1 Random number generator 失效
标题翻译：随机数发生器
公开(公告)号：US20070043798A1
公开(公告)日：2007-02-22
申请号：US11204402
申请日：2005-08-16
申请人： David Boerstler , Eskinder Hailu , Harm Hofstee , John Liberty
发明人： David Boerstler , Eskinder Hailu , Harm Hofstee , John Liberty
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , H04L9/001 , H04L9/0869
摘要： A random number generator, a method, and a computer program product are provided for producing a random number seed. Each oscillator within an array of oscillators operates at a different frequency. The operating frequencies of each oscillator are not harmonically related, such that no integer multiple exists between the frequencies of any two oscillators. In one embodiment, the outputs of the array of oscillators connect to a multiple input latch. The multiple input latch also receives a sample signal, which is a clock signal. The clock signal samples the outputs of the array of oscillators, and the multiple input latch in conjunction with the random number determination logic (“RNDL”) produces a digital output (0 or 1) for each oscillator within the array. The RNDL uses these digital outputs to create a random number seed.
摘要翻译：提供随机数生成器，方法和计算机程序产品用于产生随机数种子。振荡器阵列内的每个振荡器以不同的频率工作。每个振荡器的工作频率不是谐波相关的，使得在任何两个振荡器的频率之间不存在整数倍。在一个实施例中，振荡器阵列的输出连接到多输入锁存器。多输入锁存器还接收作为时钟信号的采样信号。时钟信号对振荡器阵列的输出采样，并且多输入锁存器与随机数确定逻辑（“RNDL”）一起为阵列内的每个振荡器产生数字输出（0或1）。 RNDL使用这些数字输出创建一个随机数字种子。

77. 发明授权

US07171318B2 PLL filter leakage sensor 失效
标题翻译： PLL滤波器泄漏传感器
公开(公告)号：US07171318B2
公开(公告)日：2007-01-30
申请号：US10870533
申请日：2004-06-17
申请人： David William Boerstler , Eskinder Hailu , Kazuhiko Miki
发明人： David William Boerstler , Eskinder Hailu , Kazuhiko Miki
IPC分类号： G01R19/00
CPC分类号： H03L7/093
摘要： The present invention provides a method, apparatus, and computer program for measuring the current leakage in a Low Pass Filter (LPF) capacitor of a Phased Locked Loop (PLL). As a result of thinner and thinner film capacitors in Complementary Metal-Oxide Semiconductor (CMOS) technology, leakage current, which causes a PLL to drift out of phase lock, has become an increasingly difficult problem. To overcome the leakage current problems, knowing the leakage current of an LPF capacitor is important to implement the correction circuitry. In the present invention, an external interface and a time interface analyzer are used to charge the LPF capacitor and measure the output frequency of the PLL's Voltage Controlled Oscillator. Because of the change in the output frequency, the leakage current can be determined.
摘要翻译：本发明提供一种用于测量相位锁定环（PLL）的低通滤波器（LPF）电容器中的电流泄漏的方法，装置和计算机程序。由于互补金属氧化物半导体（CMOS）技术中薄膜电容器越来越薄，导致PLL漂移出相位锁定的漏电流已经成为越来越难的问题。为了克服漏电流问题，知道LPF电容器的漏电流对于实现校正电路是重要的。在本发明中，使用外部接口和时间接口分析器对LPF电容器充电并测量PLL的压控振荡器的输出频率。由于输出频率的变化，可以确定漏电流。

78. 发明申请

US20060212739A1 Digital circuit to measure and/or correct duty cycles 有权
标题翻译：用于测量和/或校正占空比的数字电路
公开(公告)号：US20060212739A1
公开(公告)日：2006-09-21
申请号：US11082973
申请日：2005-03-17
申请人： David Boerstler , Eskinder Hailu , Byron Krauter , Kazuhiko Miki , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Byron Krauter , Kazuhiko Miki , Jieming Qi
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , H03K5/1565
摘要： A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.
摘要翻译：提供了一种方法，装置和计算机程序来测量和/或校正占空比。各种信号的占空比，特别是时钟信号是很重要的。然而，测量非常高频率的信号，芯片外和实验室环境可能是非常困难的并且存在许多问题。为了解决与片外测量和信号占空比调整相关的问题，可以比较输入信号和分频输入信号，从而便于测量和调整片上信号，包括时钟信号。

79. 发明申请

US20060190746A1 System and method for automatic calibration of a reference voltage 失效
标题翻译：用于自动校准参考电压的系统和方法
公开(公告)号：US20060190746A1
公开(公告)日：2006-08-24
申请号：US11065549
申请日：2005-02-24
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： A system and system for automatic voltage calibration is presented. A voltage calibration system includes three main units, which are a voltage level trimming unit, a trim detection unit, and a trim control unit. The three units work in conjunction with each other during a trimming operation in order to identify a tap voltage that is closest to a target voltage. In one embodiment, the voltage calibration system may be used to calibrate a voltage regulator. Upon commencement of calibration, the voltage regulator's feedback loop is open, and the target voltage is selected as the input for the feedback port of the amplifier. The voltage regulator serves as a voltage comparator that compares each tap voltage to the target voltage. When the calibration is complete, regulator's feedback loop is closed and the closest tap voltage to the target voltage is used as the regulator's input.
摘要翻译：提出了一种用于自动电压校准的系统和系统。电压校准系统包括三个主要单元，它们是电压调整单元，微调检测单元和微调控制单元。三个单元在微调操作期间相互协调工作，以便识别最接近目标电压的抽头电压。在一个实施例中，电压校准系统可用于校准电压调节器。校准开始后，电压调节器的反馈回路打开，目标电压被选为放大器反馈端口的输入。电压调节器用作将每个抽头电压与目标电压进行比较的电压比较器。当校准完成时，调节器的反馈回路闭合，并将最接近目标电压的分接电压用作调节器的输入。

80. 发明申请

US20060091965A1 Novel circuit for minimizing filter capacitance leakage induced jitter in phase locked loops (PLLs) 有权
标题翻译：用于最大限度地减少锁相环（PLL）中滤波电容泄漏引起的抖动的新型电路
公开(公告)号：US20060091965A1
公开(公告)日：2006-05-04
申请号：US10981155
申请日：2004-11-04
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03L7/00
CPC分类号： H03L7/0893 , H03L7/093 , H03L7/095
摘要： A method, an apparatus, and a computer program are provided to minimize filter capacitor leakage in a Phased Locked Loop (PLL). In high frequency processors and devices, filter leakage currents can cause substantial problems by causing PLLs to drift out of phase lock. To combat the leakage currents, a dummy filter and other components are employed to provide additional charge or voltage to a low pass filter during lock. The provision of the charge or voltage exponentially decreases the rate of decay of voltage across the low pass filter caused by leakage currents.
摘要翻译：提供了一种方法，装置和计算机程序以最小化相位锁定环（PLL）中的滤波电容器泄漏。在高频处理器和器件中，滤波器漏电流可能会导致相位锁相位漂移出现相当大的问题。为了防止泄漏电流，使用虚拟滤波器和其他组件在锁定期间向低通滤波器提供额外的充电或电压。充电或电压的提供以指数方式降低由漏电流引起的低通滤波器的电压衰减速率。

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