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71. 发明授权

US07737503B2 Semiconductor device and method for manufacturing the same 失效
公开(公告)号：US07737503B2
公开(公告)日：2010-06-15
申请号：US11687834
申请日：2007-03-19
申请人： Yoshinori Tsuchiya , Masato Koyama , Masahiko Yoshiki
发明人： Yoshinori Tsuchiya , Masato Koyama , Masahiko Yoshiki
IPC分类号： H01L29/49
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/28097 , H01L21/823835 , H01L21/823857 , H01L27/092 , H01L29/495 , H01L29/4975 , H01L29/517 , H01L29/665
摘要： A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source/drain regions; and a first gate electrode having a stack structure formed with a first metal layer and a first compound layer. The first metal layer is formed on the first gate insulating film and made of a first metal having a work function of 4.3 eV or smaller, and the first compound layer is formed on the first metal layer and contains a compound of a second metal and a IV-group semiconductor. The second metal is different from the first metal. A p-channel MIS transistor includes a second gate electrode having a second compound layer containing a compound of the same composition as the first compound layer.

72. 发明申请

US20090317951A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090317951A1
公开(公告)日：2009-12-24
申请号：US12554339
申请日：2009-09-04
申请人： Reika Ichihara , Yoshinori Tsuchiya , Hiroki Tanaka , Masato Koyama
发明人： Reika Ichihara , Yoshinori Tsuchiya , Hiroki Tanaka , Masato Koyama
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823864
摘要： A semiconductor device has an n-channel MIS transistor and a p-channel MIS transistor on a substrate. The n-channel MIS transistor includes a p-type semiconductor region formed on the substrate, a lower layer gate electrode which is formed via a gate insulating film above the p-type semiconductor region and which is one monolayer or more and 3 nm or less in thickness, and an upper layer gate electrode which is formed on the lower layer gate electrode, whose average electronegativity is 0.1 or more smaller than the average electronegativity of the lower layer gate electrode. The p-channel MIS transistor includes an n-type semiconductor region formed on the substrate and a gate electrode which is formed via a gate insulating film above the n-type semiconductor region and is made of the same metal material as that of the upper layer gate electrode.
摘要翻译：半导体器件在衬底上具有n沟道MIS晶体管和p沟道MIS晶体管。 n沟道MIS晶体管包括形成在基板上的p型半导体区域，通过p型半导体区域上方的栅极绝缘膜形成并且为单层以上且3nm以下的下层栅电极以及形成在下层栅电极上的上层栅电极，其平均电负性比下层栅电极的平均电负性小0.1或更小。 p沟道MIS晶体管包括形成在衬底上的n型半导体区域和通过n型半导体区域上方的栅极绝缘膜形成并由与上层相同的金属材料制成的栅电极栅电极。

73. 发明授权

US07612413B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07612413B2
公开(公告)日：2009-11-03
申请号：US11461646
申请日：2006-08-01
申请人： Masato Koyama , Reika Ichihara , Yoshinori Tsuchiya , Yuuichi Kamimuta , Akira Nishiyama
发明人： Masato Koyama , Reika Ichihara , Yoshinori Tsuchiya , Yuuichi Kamimuta , Akira Nishiyama
IPC分类号： H01L27/092
CPC分类号： H01L21/823842 , H01L21/823835
摘要： A semiconductor device includes a substrate, a p-channel MIS transistor formed on the substrate, the p-channel MIS transistor having a first gate electrode, and an n-channel MIS transistor formed on the substrate separately from the p-channel MIS transistor, the n-channel MIS transistor having a second gate electrode. Each of the first gate electrode and the second gate electrode is formed of an alloy of Ta and C in which a mole ratio of C to Ta (C/Ta) is from 2 to 4.
摘要翻译：半导体器件包括衬底，形成在衬底上的p沟道MIS晶体管，具有第一栅电极的p沟道MIS晶体管和与p沟道MIS晶体管分开形成在衬底上的n沟道MIS晶体管，该n沟道MIS晶体管具有第二栅电极。第一栅极电极和第二栅极电极由Ta和C的合金形成，其中C与Ta（C / Ta）的摩尔比为2〜4。

74. 发明申请

US20090267134A1 NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20090267134A1
公开(公告)日：2009-10-29
申请号：US12233023
申请日：2008-09-18
申请人： Masahiro Koike , Yuuichiro Mitani , Yasushi Nakasaki , Masato Koyama
发明人： Masahiro Koike , Yuuichiro Mitani , Yasushi Nakasaki , Masato Koyama
IPC分类号： H01L29/792
CPC分类号： H01L27/11521 , H01L27/11568
摘要： A nonvolatile semiconductor memory apparatus includes: a memory element including: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the semiconductor substrate located between the source region and the drain region, having sites that perform electron trapping and releasing and are formed by adding an element different from a base material, and including insulating layers having different dielectric constants, the sites having a higher level than a Fermi level of a material forming the semiconductor substrate; a charge storage film formed on the first insulating film; a second insulating film formed on the charge storage film; and a control gate electrode formed on the second insulating film.
摘要翻译：一种非易失性半导体存储装置，包括：存储元件，包括：半导体衬底; 在半导体衬底中形成为彼此间隔一定距离的源极区域和漏极区域; 形成在位于源极区域和漏极区域之间的半导体衬底的一部分上的第一绝缘膜，具有进行电子俘获和释放的位置，并且通过添加不同于基底材料的元件形成，并且包括具有不同电介质的绝缘层常数，具有比形成半导体衬底的材料的费米能级高的位置; 形成在所述第一绝缘膜上的电荷存储膜; 形成在电荷存储膜上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制栅电极。

75. 发明授权

US07573065B2 Semiconductor device evaluation method 失效
标题翻译：半导体器件评估方法
公开(公告)号：US07573065B2
公开(公告)日：2009-08-11
申请号：US11472449
申请日：2006-06-22
申请人： Ryosuke Iijima , Masato Koyama
发明人： Ryosuke Iijima , Masato Koyama
IPC分类号： H01L23/58
CPC分类号： G01R31/2621 , H01L2924/0002 , H01L2924/00
摘要： An apparatus for evaluating a field-effect transistor includes a pulse generator, a current/voltage converter, a switch and a first constant-voltage source. The pulse generator can be electrically connected to a gate electrode of a field-effect transistor. The current/voltage converter includes an input terminal. The input terminal can be electrically connected to a first source/drain region of the field-effect transistor. The switch can be electrically connected to a second source/drain region of the field-effect transistor. The switch switches between a connection state and a disconnection state. The first constant-voltage source can be electrically connected to the second source/drain region through the switch.
摘要翻译：用于评估场效应晶体管的装置包括脉冲发生器，电流/电压转换器，开关和第一恒压源。脉冲发生器可以电连接到场效应晶体管的栅电极。电流/电压转换器包括输入端子。输入端子可以电连接到场效应晶体管的第一源极/漏极区域。开关可以电连接到场效应晶体管的第二源/漏区。交换机在连接状态和断开状态之间切换。第一恒压源可以通过开关电连接到第二源极/漏极区域。

76. 发明授权

US07563678B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US07563678B2
公开(公告)日：2009-07-21
申请号：US11812839
申请日：2007-06-22
申请人： Masato Koyama , Yoshinori Tsuchiya , Reika Ichihara
发明人： Masato Koyama , Yoshinori Tsuchiya , Reika Ichihara
IPC分类号： H01L21/8234
CPC分类号： H01L21/823835 , H01L21/823842
摘要： It is possible to provide a semiconductor device including a CMOS device having a gate electrode, in which the variation in threshold voltage is little. There are a p-channel MIS transistor and a n-channel MIS transistor which are provided in a semiconductor substrate, and in a region of a gate electrode of the p-channel MIS transistor at least 1 nm or less apart from the interface with a gate insulating film, the oxygen concentration is 1020 cm−3 or more and 1022 cm−3 or less.

77. 发明授权

US07541657B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07541657B2
公开(公告)日：2009-06-02
申请号：US12133583
申请日：2008-06-05
申请人： Masato Koyama , Akira Nishiyama , Yoshinori Tsuchiya , Reika Ichihara
发明人： Masato Koyama , Akira Nishiyama , Yoshinori Tsuchiya , Reika Ichihara
IPC分类号： H01L29/78
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/28088 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate insulating layer formed on the P-type semiconductor layer, and a second gate electrode formed on the second gate insulating layer.
摘要翻译：公开了一种包括P沟道MIS晶体管的半导体器件，其包括N型半导体层，形成在N型半导体层上并含有金属的碳化合物的第一栅极绝缘层和N沟道MIS 晶体管，其包括P型半导体层，形成在P型半导体层上的第二栅极绝缘层和形成在第二栅极绝缘层上的第二栅电极。

78. 发明申请

US20080237699A1 NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20080237699A1
公开(公告)日：2008-10-02
申请号：US12050427
申请日：2008-03-18
申请人： Tatsuo SHIMIZU , Koichi Muraoka , Masato Koyama , Shoko Kikuchi
发明人： Tatsuo SHIMIZU , Koichi Muraoka , Masato Koyama , Shoko Kikuchi
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/66833 , H01L29/785
摘要： A nonvolatile semiconductor memory includes a source area and a drain area provided on a semiconductor substrate with a gap which serves as a channel area, a first insulating layer, a charge accumulating layer, a second insulating layer (block layer) and a control electrode, formed successively on the channel area, and the second insulating layer is formed by adding an appropriate amount of high valence substance into base material composed of substance having a sufficiently higher dielectric constant than the first insulating layer so as to accumulate a large amount of negative charges in the block layer by localized state capable of trapping electrons, so that the high dielectric constant of the block layer and the high electronic barrier are achieved at the same time.
摘要翻译：非易失性半导体存储器包括设置在具有用作沟道区的间隙的半导体衬底上的源区和漏区，第一绝缘层，电荷累积层，第二绝缘层（阻挡层）和控制电极，在通道区域上依次形成，并且通过向具有比第一绝缘层高的介电常数的物质构成的基材中添加适量的高价态物质形成第二绝缘层，以便积累大量的负电荷在阻挡层中通过能够捕获电子的局部状态，从而同时实现阻挡层和高电子势垒的高介电常数。

79. 发明申请

US20080224226A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20080224226A1
公开(公告)日：2008-09-18
申请号：US11858408
申请日：2007-09-20
申请人： Masamichi Suzuki , Masato Koyama
发明人： Masamichi Suzuki , Masato Koyama
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/28079 , H01L21/28097 , H01L21/28194 , H01L21/823842 , H01L29/165 , H01L29/47 , H01L29/4958 , H01L29/4975 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66636 , H01L29/7843 , H01L29/7845
摘要： A semiconductor device includes a semiconductor substrate, p-type first and n-type second semiconductor regions formed on the substrate so as to be insulated with each other, n-channel and p-channel MOS transistors formed on the first and second semiconductor regions, the n-channel transistor including a first pair of source/drain regions formed on the first semiconductor region, a first gate insulator formed in direct contact with the first semiconductor region and formed as an amorphous insulator containing at least La, and a first gate electrode formed on the first gate insulator, the p-channel MOS transistor including a second pair of source/drain regions formed opposite to each other on the second semiconductor region, a second gate insulator including a silicon oxide film and the amorphous insulating film formed thereon on the second semiconductor region, and a second gate electrode formed on the second gate insulator.
摘要翻译：半导体器件包括半导体衬底，形成在衬底上以彼此绝缘的p型第一和n型第二半导体区，形成在第一和第二半导体区上的n沟道和p沟道MOS晶体管，所述n沟道晶体管包括形成在所述第一半导体区域上的第一对源极/漏极区域，与所述第一半导体区域直接接触形成并形成为至少包含La的非晶绝缘体的第一栅极绝缘体和第一栅极电极形成在所述第一栅极绝缘体上的所述p沟道MOS晶体管，包括在所述第二半导体区域上彼此相对形成的第二对源极/漏极区域，包括氧化硅膜的第二栅极绝缘体和在其上形成的非晶绝缘膜第二半导体区域和形成在第二栅极绝缘体上的第二栅电极。

80. 发明申请

US20070249106A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070249106A1
公开(公告)日：2007-10-25
申请号：US11812839
申请日：2007-06-22
申请人： Masato Koyama , Yoshinori Tsuchiya , Reika Ichihara
发明人： Masato Koyama , Yoshinori Tsuchiya , Reika Ichihara
IPC分类号： H01L21/8238 , H01L21/84
CPC分类号： H01L21/823835 , H01L21/823842
摘要： It is possible to provide a semiconductor device including a CMOS device having a gate electrode, in which the variation in threshold voltage is little. There are a p-channel MIS transistor and a n-channel MIS transistor which are provided in a semiconductor substrate, and in a region of a gate electrode of the p-channel MIS transistor at least 1 nm or less apart from the interface with a gate insulating film, the oxygen concentration is 1020 cm−3 or more and 1022 cm−3 or less.
摘要翻译：可以提供一种包括具有门电极的CMOS器件的半导体器件，其中阈值电压的变化很小。存在设置在半导体衬底中的p沟道MIS晶体管和n沟道MIS晶体管，并且在p沟道MIS晶体管的栅电极的区域中，除了与栅极绝缘膜，氧浓度为10〜30厘米-3以上且10〜22厘米-3以上或减。

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