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71. 发明授权

US08513723B2 Method and structure for forming high performance MOS capacitor along with fully depleted semiconductor on insulator devices on the same chip 有权
标题翻译：在同一芯片上形成高性能MOS电容器以及完全耗尽的绝缘体上半导体器件的方法和结构
公开(公告)号：US08513723B2
公开(公告)日：2013-08-20
申请号：US12689743
申请日：2010-01-19
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
IPC分类号： H01L27/12
CPC分类号： H01L21/845 , H01L27/1211 , H01L28/40
摘要： An integrated circuit is provided that includes a fully depleted semiconductor device and a capacitor present on a semiconductor on insulator (SOI) substrate. The fully depleted semiconductor device may be a finFET semiconductor device or a planar semiconductor device. In one embodiment, the integrated circuit includes a substrate having a first device region and a second device region. The first device region of the substrate includes a first semiconductor layer that is present on a buried insulating layer. The buried insulating layer that is in the first device region is present on a second semiconductor layer of the substrate. The second device region includes the second semiconductor layer, but the first semiconductor layer and the buried insulating layer are not present in the second device region. The first device region includes the fully depleted semiconductor device. A capacitor is present in the second device region.
摘要翻译：提供了一种集成电路，其包括完全耗尽的半导体器件和存在于半导体绝缘体（SOI））衬底上的电容器。完全耗尽的半导体器件可以是finFET半导体器件或平面半导体器件。在一个实施例中，集成电路包括具有第一器件区域和第二器件区域的衬底。衬底的第一器件区域包括存在于掩埋绝缘层上的第一半导体层。在第一器件区域中的掩埋绝缘层存在于衬底的第二半导体层上。第二器件区域包括第二半导体层，但是第二器件区域中不存在第一半导体层和掩埋绝缘层。第一器件区域包括完全耗尽的半导体器件。电容器存在于第二器件区域中。

72. 发明授权

US08994085B2 Integrated circuit including DRAM and SRAM/logic 有权
标题翻译：集成电路包括DRAM和SRAM /逻辑
公开(公告)号：US08994085B2
公开(公告)日：2015-03-31
申请号：US13551714
申请日：2012-07-18
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni , Tenko Yamashita , Chun-Chen Yeh
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119 , H01L21/84 , H01L27/11 , H01L27/12
CPC分类号： H01L21/84 , H01L27/10861 , H01L27/1087 , H01L27/10873 , H01L27/10894 , H01L27/10897 , H01L27/1108 , H01L27/1116 , H01L27/1203 , H01L29/945
摘要： An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.
摘要翻译：一种集成电路，包括N +型层，设置在N +型层上的缓冲层; 形成在缓冲层上的P型区域; 覆盖N +型层的绝缘体层，覆盖绝缘体层的硅层，形成在硅层中并与延伸到N +型层的沟槽电容器的导电节点连接的嵌入式RAM FET，N +型层形成沟槽电容器的平板电极，通过硅层和绝缘层的第一接触并且电连接到N +型层，形成在P型区域上方的硅层中的第一逻辑RAM FET，P型区域用作第一逻辑RAM FET的P型背栅，以及通过硅层和绝缘层的第二接触，并且电连接到P型区域。

73. 发明授权

US08653596B2 Integrated circuit including DRAM and SRAM/logic 有权
标题翻译：集成电路包括DRAM和SRAM /逻辑
公开(公告)号：US08653596B2
公开(公告)日：2014-02-18
申请号：US13344885
申请日：2012-01-06
申请人： Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L21/70 , H01L27/12 , H01L21/762 , H01L21/84
CPC分类号： H01L29/945 , H01L21/84 , H01L27/1052 , H01L27/1087 , H01L27/10873 , H01L27/10894 , H01L27/1116 , H01L27/1203 , H01L27/1207
摘要： An integrated circuit includes an SOI substrate with a unitary N+ layer below the BOX, a P region in the N+ layer, an eDRAM with an N+ plate, and logic/SRAM devices above the P region. The P region functions as a back gate of the logic/SRAM devices. An optional intrinsic (undoped) layer can be formed between the P back gate layer and the N+ layer to reduce the junction field and lower the junction leakage between the P back gate and the N+ layer. In another embodiment an N or N+ back gate can be formed in the P region. The N+ back gate functions as a second back gate of the logic/SRAM devices. The N+ plate of the SOI eDRAM, the P back gate, and the N+ back gate can be electrically biased at the same or different voltage potentials. Methods to fabricate the integrated circuits are also disclosed.
摘要翻译：集成电路包括在BOX下方具有单一N +层的SOI衬底，N +层中的P区，N +板的eDRAM和P区上方的逻辑/ SRAM器件。 P区域用作逻辑/ SRAM器件的后门。可以在P背栅层和N +层之间形成可选的本征（未掺杂）层，以减少结场并降低P背栅与N +层之间的结泄漏。在另一个实施例中，可以在P区中形成N或N +背栅。 N +后门作为逻辑/ SRAM器件的第二个后门。 SOI eDRAM的N +板，P背栅极和N +背栅极可以在相同或不同的电压电位下被电偏置。还公开了制造集成电路的方法。

74. 发明申请

US20140024215A1 DOUBLE PATTERNING METHOD 有权
标题翻译：双重图案方法
公开(公告)号：US20140024215A1
公开(公告)日：2014-01-23
申请号：US13555306
申请日：2012-07-23
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ying Zhang
IPC分类号： B44C1/22 , H01B13/00 , H01L21/308
CPC分类号： H01L21/3086 , H01B13/00 , H01B19/04 , H01L21/0337 , H01L21/3081 , H01L21/32134 , H01L21/32137
摘要： Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.
摘要翻译：公开了一种用于在基板上形成开口（例如，通孔或沟槽）或台面的改进的双重图案化方法。该方法通过确保衬底本身仅经历单次蚀刻工艺来避免现有技术的双重图案化技术中所见到的晶片形貌效应。具体地说，在该方法中，在衬底上形成第一掩模层并进行处理，使得其在掺杂区域内具有掺杂区域和多个未掺杂区域。然后，可以选择性地去除未掺杂区域或掺杂区域，以在衬底上方形成掩模图案。一旦形成掩模图案，就可以执行蚀刻工艺以将掩模图案转印到基板中。取决于未掺杂的区域是去除还是去除掺杂区域，掩模图案将分别在衬底上形成开口（例如，通孔或沟槽）或台面。

75. 发明申请

US20130344677A1 SHALLOW TRENCH ISOLATION STRUCTURES 有权
公开(公告)号：US20130344677A1
公开(公告)日：2013-12-26
申请号：US13531780
申请日：2012-06-25
申请人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
发明人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
IPC分类号： H01L21/762
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/76283
摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

76. 发明申请

US20130341754A1 SHALLOW TRENCH ISOLATION STRUCTURES 有权
公开(公告)号：US20130341754A1
公开(公告)日：2013-12-26
申请号：US13531654
申请日：2012-06-25
申请人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
发明人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
IPC分类号： H01L29/06
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/76283
摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

77. 发明申请

US20130270627A1 FinFET NON-VOLATILE MEMORY AND METHOD OF FABRICATION 失效
标题翻译： FinFET非易失性存储器和制造方法
公开(公告)号：US20130270627A1
公开(公告)日：2013-10-17
申请号：US13444219
申请日：2012-04-11
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L21/823431 , H01L21/28273 , H01L21/28282 , H01L21/845 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L27/1157 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792
摘要： A method of manufacturing a FinFET non-volatile memory device and a FinFET non-volatile memory device structure. A substrate is provided and a layer of semiconductor material is deposited over the substrate. A hard mask is deposited over the semiconductor material and the structure is patterned to form fins. A charge storage layer is deposited over the structure, including the fins and the portions of it are damaged using an angled ion implantation process. The damaged portions are removed and gate structures are formed on either side of the fin, with only one side having a charge storage layer.
摘要翻译：一种制造FinFET非易失性存储器件和FinFET非易失性存储器件结构的方法。提供衬底并且在衬底上沉积半导体材料层。在半导体材料上沉积硬掩模，并且将该结构图案化以形成翅片。电荷存储层沉积在结构上，包括鳍片，并且其部分使用成角度的离子注入工艺被损坏。损坏的部分被去除并且栅极结构形成在翅片的任一侧，只有一侧具有电荷存储层。

78. 发明申请

US20130175595A1 INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC 有权
标题翻译：集成电路，包括DRAM和SRAM /逻辑
公开(公告)号：US20130175595A1
公开(公告)日：2013-07-11
申请号：US13344885
申请日：2012-01-06
申请人： Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L27/108 , H01L21/336
CPC分类号： H01L29/945 , H01L21/84 , H01L27/1052 , H01L27/1087 , H01L27/10873 , H01L27/10894 , H01L27/1116 , H01L27/1203 , H01L27/1207
摘要： An integrated circuit includes an SOI substrate with a unitary N+ layer below the BOX, a P region in the N+ layer, an eDRAM with an N+ plate, and logic/SRAM devices above the P region. The P region functions as a back gate of the logic/SRAM devices. An optional intrinsic (undoped) layer can be formed between the P back gate layer and the N+ layer to reduce the junction field and lower the junction leakage between the P back gate and the N+ layer. In another embodiment an N or N+ back gate can be formed in the P region. The N+ back gate functions as a second back gate of the logic/SRAM devices. The N+ plate of the SOI eDRAM, the P back gate, and the N+ back gate can be electrically biased at the same or different voltage potentials. Methods to fabricate the integrated circuits are also disclosed.
摘要翻译：集成电路包括在BOX下方具有单一N +层的SOI衬底，N +层中的P区，N +板的eDRAM和P区上方的逻辑/ SRAM器件。 P区域用作逻辑/ SRAM器件的后门。可以在P背栅层和N +层之间形成可选的本征（未掺杂）层，以减少结场并降低P背栅与N +层之间的结泄漏。在另一个实施例中，可以在P区中形成N或N +背栅。 N +后门作为逻辑/ SRAM器件的第二个后门。 SOI eDRAM的N +板，P背栅极和N +背栅极可以在相同或不同的电压电位下被电偏置。还公开了制造集成电路的方法。

79. 发明申请

US20130146975A1 SEMICONDUCTOR DEVICE AND INTEGRATED CIRCUIT WITH HIGH-K/METAL GATE WITHOUT HIGH-K DIRECT CONTACT WITH STI 审中-公开
标题翻译：具有高K /金属栅的半导体器件和集成电路，与高K直接接触STI
公开(公告)号：US20130146975A1
公开(公告)日：2013-06-13
申请号：US13316677
申请日：2011-12-12
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L27/088 , H01L21/762
CPC分类号： H01L29/66545 , H01L21/76224 , H01L21/823462 , H01L21/823481 , H01L29/7833
摘要： A method, semiconductor device, and integrated circuit with a high-k/metal gate without high-k direct contact with STI. A high-k dielectric and a pad film are deposited directly onto a semiconductor substrate. Shallow trench isolation is performed, with shallow trenches etched directly into the pad film, the high-k material, and the substrate. The shallow trench is lined with an oxygen diffusion barrier and is subsequently filled with an insulating dielectric material. Thereafter the pad film and the insulating dielectric are recessed to a point where the oxygen diffusion barrier still remains between the insulating dielectric and the high-k material, preventing any contact there between. Afterwards a conductive gate is formed overlying the device.
摘要翻译：具有高k /金属栅极的方法，半导体器件和集成电路，无需与STI直接接触。将高k电介质和焊盘膜直接沉积到半导体衬底上。执行浅沟槽隔离，其中浅沟槽直接蚀刻到衬垫膜，高k材料和衬底中。浅沟槽衬有氧扩散阻挡层，随后填充有绝缘介电材料。此后，衬垫膜和绝缘电介质凹陷到氧扩散阻挡层仍然保留在绝缘电介质和高k材料之间的点，防止其间的任何接触。之后形成覆盖该器件的导电栅极。

80. 发明授权

US08455932B2 Local interconnect structure self-aligned to gate structure 有权
标题翻译：局部互连结构自对准到门结构
公开(公告)号：US08455932B2
公开(公告)日：2013-06-04
申请号：US13102073
申请日：2011-05-06
申请人： Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Wilfried E. Haensch , Balasubramanian S. Haran , Pranita Kulkarni
发明人： Ali Khakifirooz , Kangguo Cheng , Bruce B. Doris , Wilfried E. Haensch , Balasubramanian S. Haran , Pranita Kulkarni
IPC分类号： H01L21/336
CPC分类号： H01L27/0207 , H01L21/28518 , H01L21/76802 , H01L21/76895 , H01L21/76897 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L27/1104 , H01L29/41783 , H01L29/66545 , H01L29/6659 , H01L29/7834
摘要： A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other.
摘要翻译：采用公共切割掩模来限定栅极图案和局部互连图案，使得局部互连结构和栅极结构相对于彼此形成为零覆盖变化。局部互连结构可以在第一水平方向上与栅极结构横向间隔开，并且在与第一水平方向不同的第二水平方向上接触另一个栅极结构。此外，栅极结构可以形成为与邻接栅极结构的局部互连结构共线。局部互连结构和栅极结构通过公共镶嵌处理步骤形成，使得栅极结构的顶表面和局部互连结构彼此共面。

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