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71. 发明授权

US08675725B2 Integrated circuit, communication unit and method for improved amplitude resolution of an RF-DAC 有权
标题翻译：用于提高RF-DAC幅度分辨率的集成电路，通信单元和方法
公开(公告)号：US08675725B2
公开(公告)日：2014-03-18
申请号：US13018394
申请日：2011-01-31
申请人： Robert Bogdan Staszewski , Min Park
发明人： Robert Bogdan Staszewski , Min Park
IPC分类号： H03K7/08
CPC分类号： H03K7/08 , H03F3/2176 , H03M1/68 , H03M1/747 , H03M1/822 , H04B14/026
摘要： An integrated circuit comprises a digitally-controlled power generation stage (DPA) for converting an input signal to a radio frequency (RF) carrier, the DPA comprising a plurality of selectable switching devices capable of adjusting an envelope of the RF carrier; and a pulse width modulator (PWM) generator arranged to generate a PWM control signal and operably coupleable to the plurality of selectable switching devices of the DPA. The PWM generator inputs the PWM control signal to a subset of the plurality of the selectable switching devices such that a PWM signal adjusts the envelope RF carrier output from the DPA.
摘要翻译：集成电路包括用于将输入信号转换为射频（RF）载波的数字控制发电级（DPA），DPA包括能够调整RF载波的包络的多个可选开关装置; 以及脉冲宽度调制器（PWM）发生器，其布置成产生PWM控制信号并且可操作地耦合到DPA的多个可选开关装置。 PWM发生器将PWM控制信号输入到多个可选切换装置的子集，使得PWM信号调整从DPA输出的包络RF载波。

72. 发明授权

US08593182B2 Frequency synthesizer and associated method 有权
标题翻译：频率合成器及相关方法
公开(公告)号：US08593182B2
公开(公告)日：2013-11-26
申请号：US13450208
申请日：2012-04-18
申请人： Ang-Sheng Lin , Robert Bogdan Staszewski , Yi-Hsien Cho
发明人： Ang-Sheng Lin , Robert Bogdan Staszewski , Yi-Hsien Cho
IPC分类号： H03B21/00
CPC分类号： H03L7/081 , G06F1/32 , H03L7/16 , H03L7/18 , H03L2207/50
摘要： A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter coupled to said oscillator for providing a shifted RF clock by changing phase of said RF clock, and a time-to-digital converter (TDC) coupled to said phase shifter for quantizing a time difference between a frequency reference clock and said shifted RF clock, wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided.
摘要翻译：频率合成器包括用于提供RF时钟的振荡器，耦合到所述振荡器的移相器，用于通过改变所述RF时钟的相位来提供移位的RF时钟;以及耦合到所述移相器的时间 - 数字转换器（TDC），用于量化频率参考时钟和所述移位的RF时钟之间的时间差，其中所述TDC的范围明显小于所述RF时钟周期的整个范围。还提供了相关联的方法。

73. 发明申请

US20110267127A1 Integrated circuit, communication unit and method for improved amplitude resolution of an RF-DAC 有权
标题翻译：用于提高RF-DAC幅度分辨率的集成电路，通信单元和方法
公开(公告)号：US20110267127A1
公开(公告)日：2011-11-03
申请号：US13018394
申请日：2011-01-31
申请人： Robert Bogdan Staszewski , Min Park
发明人： Robert Bogdan Staszewski , Min Park
IPC分类号： H03L5/00
CPC分类号： H03K7/08 , H03F3/2176 , H03M1/68 , H03M1/747 , H03M1/822 , H04B14/026
摘要： An integrated circuit comprises a digitally-controlled power generation stage (DPA) for converting an input signal to a radio frequency (RF) carrier, the DPA comprising a plurality of selectable switching devices capable of adjusting an envelope of the RF carrier; and a pulse width modulator (PWM) generator arranged to generate a PWM control signal and operably coupleable to the plurality of selectable switching devices of the DPA. The PWM generator inputs the PWM control signal to a subset of the plurality of the selectable switching devices such that a PWM signal adjusts the envelope RF carrier output from the DPA.
摘要翻译：集成电路包括用于将输入信号转换为射频（RF）载波的数字控制发电级（DPA），DPA包括能够调整RF载波的包络的多个可选开关装置; 以及脉冲宽度调制器（PWM）发生器，其布置成产生PWM控制信号并且可操作地耦合到DPA的多个可选开关装置。 PWM发生器将PWM控制信号输入到多个可选切换装置的子集，使得PWM信号调整从DPA输出的包络RF载波。

74. 发明授权

US08045662B2 Binary ripple counter sampling with adjustable delays 有权
标题翻译：具有可调延迟的二进制纹波计数器采样
公开(公告)号：US08045662B2
公开(公告)日：2011-10-25
申请号：US12143008
申请日：2008-06-20
申请人： Jingcheng Zhuang , Robert Bogdan Staszewski
发明人： Jingcheng Zhuang , Robert Bogdan Staszewski
IPC分类号： H04L7/00
CPC分类号： H03K23/58 , H03K23/662
摘要： The output bits of a binary ripple counter are used to control the sampling of those output bits, thereby ensuring accurate sampling. A sampler is provided with adjustable delay elements that permit accurate sampling regardless of: delay mismatch between the sampler and a data path of the counter; the length of the counter; operating speed; or PVT variations.
摘要翻译：二进制纹波计数器的输出位用于控制这些输出位的采样，从而确保精确的采样。采样器具有可调延迟元件，允许精确采样，而不管采样器与计数器的数据通路之间的延迟不匹配：柜台的长度; 运行速度; 或PVT变化。

75. 发明授权

US07920081B2 Digital phase locked loop with dithering 有权
标题翻译：数字锁相环与抖动
公开(公告)号：US07920081B2
公开(公告)日：2011-04-05
申请号：US12841354
申请日：2010-07-22
申请人： Khurram Waheed , Mahbuba Sheba , Robert Bogdan Staszewski , Socrates Vamvakos
发明人： Khurram Waheed , Mahbuba Sheba , Robert Bogdan Staszewski , Socrates Vamvakos
IPC分类号： H03M1/06
CPC分类号： H03M1/0639 , G04F10/005 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/12 , H04L5/0007 , H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0051 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0097
摘要： An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.
摘要翻译：本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。频率参考输入提供参考时钟。可控振荡器产生RF时钟信号。相位检测电路对参考时钟进行操作，以提供指示参考时钟和RF时钟之间的相位差的数字相位误差样本。抖动电路耦合到参考信号，并将短序列抖动信号注入到参考信号中，以便克服量化噪声，从而改进整数信道的RMS相位误差检测。

76. 发明申请

US20100283654A1 DIGITAL PHASE LOCKED LOOP WITH DITHERING 有权
标题翻译：数字相位锁定环
公开(公告)号：US20100283654A1
公开(公告)日：2010-11-11
申请号：US12841354
申请日：2010-07-22
申请人： Khurram Waheed , Mahbuba Sheba , Robert Bogdan Staszewski , Socrates Vamvakos
发明人： Khurram Waheed , Mahbuba Sheba , Robert Bogdan Staszewski , Socrates Vamvakos
IPC分类号： H03M1/50 , H03M1/12
CPC分类号： H03M1/0639 , G04F10/005 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/12 , H04L5/0007 , H04L27/0014 , H04L27/2657 , H04L2027/0016 , H04L2027/0051 , H04L2027/0055 , H04L2027/0067 , H04L2027/0069 , H04L2027/0097
摘要： An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.
摘要翻译：本发明的一个实施例提供了一种锁相环，其对由锁相环产生的RF时钟信号导出的时钟信号进行操作。频率参考输入提供参考时钟。可控振荡器产生RF时钟信号。相位检测电路对参考时钟进行操作，以提供指示参考时钟和RF时钟之间的相位差的数字相位误差样本。抖动电路耦合到参考信号，并将短序列抖动信号注入到参考信号中，以便克服量化噪声，从而改进整数信道的RMS相位误差检测。

77. 发明授权

US07777572B2 Integrated power amplifier 有权
标题翻译：集成功率放大器
公开(公告)号：US07777572B2
公开(公告)日：2010-08-17
申请号：US12563528
申请日：2009-09-21
申请人： Robert Bogdan Staszewski , See Taur Lee
发明人： Robert Bogdan Staszewski , See Taur Lee
IPC分类号： H03F3/68
CPC分类号： H03F3/189 , H03F3/211 , H03F3/602 , H03F2200/541
摘要： Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high power and high efficiency radio frequency power amplifier to be realized using multiple low voltage CMOS transistors or micro power amplifiers. The power combiner may be printed on a package substrate and realized either using single layer substrate through edge coupling or multiple layers substrate through broadside coupling. The micro power amplifiers may be fabricated using low voltage CMOS technology and electrical connections between the outputs from the micro power amplifiers and the power combiner may be provided through stud bumps in a flip chip technology. With the tunable matching circuits, the present invention allows the narrow band power combiner to be tuned to different frequencies.
摘要翻译：公开了实现具有新型匹配电路的低成本，高效率，低损耗功率组合器的方法。窄带功率组合器使得能够使用多个低电压CMOS晶体管或微功率放大器实现高功率和高效率的射频功率放大器。功率组合器可以印刷在封装衬底上，并且通过边缘耦合使用单层衬底或通过宽边耦合实现多层衬底。微功率放大器可以使用低电压CMOS技术制造，并且来自微功率放大器的输出之间的电连接和功率组合器可以通过倒装芯片技术中的凸块凸块来提供。利用可调匹配电路，本发明允许将窄带功率组合器调谐到不同的频率。

78. 发明申请

US20100007423A1 INTEGRATED POWER AMPLIFIER 有权
标题翻译：集成功率放大器
公开(公告)号：US20100007423A1
公开(公告)日：2010-01-14
申请号：US12563528
申请日：2009-09-21
申请人： Robert Bogdan Staszewski , See Taur Lee
发明人： Robert Bogdan Staszewski , See Taur Lee
IPC分类号： H03F3/68
CPC分类号： H03F3/189 , H03F3/211 , H03F3/602 , H03F2200/541
摘要： Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high power and high efficiency radio frequency power amplifier to be realized using multiple low voltage CMOS transistors or micro power amplifiers. The power combiner may be printed on a package substrate and realized either using single layer substrate through edge coupling or multiple layers substrate through broadside coupling. The micro power amplifiers may be fabricated using low voltage CMOS technology and electrical connections between the outputs from the micro power amplifiers and the power combiner may be provided through stud bumps in a flip chip technology. With the tunable matching circuits, the present invention allows the narrow band power combiner to be tuned to different frequencies.
摘要翻译：公开了实现具有新型匹配电路的低成本，高效率，低损耗功率组合器的方法。窄带功率组合器使得能够使用多个低电压CMOS晶体管或微功率放大器实现高功率和高效率的射频功率放大器。功率组合器可以印刷在封装衬底上，并且通过边缘耦合使用单层衬底或通过宽边耦合实现多层衬底。微功率放大器可以使用低电压CMOS技术制造，并且来自微功率放大器的输出之间的电连接和功率组合器可以通过倒装芯片技术中的凸块凸块来提供。利用可调匹配电路，本发明允许将窄带功率组合器调谐到不同的频率。

79. 发明申请

US20090325494A1 Transmitter PLL with Bandwidth on Demand 有权
标题翻译：发射器PLL带宽带宽
公开(公告)号：US20090325494A1
公开(公告)日：2009-12-31
申请号：US12412790
申请日：2009-03-27
申请人： Robert Bogdan Staszewski , Khurram Waheed , Sudheer K. Vemulapalli , Manouchehr Entezari , Imran Bashir
发明人： Robert Bogdan Staszewski , Khurram Waheed , Sudheer K. Vemulapalli , Manouchehr Entezari , Imran Bashir
IPC分类号： H04B7/00
CPC分类号： H03L7/085 , H03L7/093 , H03L7/0991 , H03L2207/50 , H04L27/361
摘要： An embodiment of the present invention provides transmitter having a phase locked loop that has a dynamically controllable loop bandwidth. A transmit modulator is coupled to the PLL for performing vector modulation in response to transmission symbols. Each transmission symbol comprises an amplitude signal and a phase signal. A controller is coupled to the PLL and to the transmit modulator and is operable to detect when a criteria of the transmission symbols crosses a threshold and to adjust loop bandwidth in response to crossing the threshold. The criteria of the transmission symbols may be a function of the amplitude signal or a function of the phase signal, and may be the amplitude signal, a first derivative of the amplitude signal, a second derivative of the amplitude signal, a square of the amplitude signal, a derivative of the amplitude signal squared, the phase signal, or a derivative of the phase signal.
摘要翻译：本发明的一个实施例提供具有锁相环的发射机，其具有动态可控的环路带宽。发射调制器耦合到PLL以响应于发射符号执行矢量调制。每个发送符号包括振幅信号和相位信号。控制器耦合到PLL和发射调制器，并且可操作以检测发射符号的标准何时跨越阈值并响应于跨越阈值来调整环路带宽。传输符号的标准可以是振幅信号或相位信号的函数的函数，并且可以是振幅信号，振幅信号的一阶导数，振幅信号的二阶导数，幅度的平方信号，幅度信号平方的导数，相位信号或相位信号的导数。

80. 发明申请

US20090175378A1 System and Method for Impedance Mismatch Compensation in Digital Communications Systems 审中-公开
标题翻译：数字通信系统中阻抗不匹配补偿的系统与方法
公开(公告)号：US20090175378A1
公开(公告)日：2009-07-09
申请号：US12185920
申请日：2008-08-05
申请人： Robert Bogdan Staszewski , Daquan Huang , Chih-Ming Hung
发明人： Robert Bogdan Staszewski , Daquan Huang , Chih-Ming Hung
IPC分类号： H04L27/00
CPC分类号： H03H7/40 , H01P3/026 , H01P5/04 , H03F1/56 , H03F3/245 , H03F3/601 , H03F2200/387 , H03F2200/423
摘要： A system and method for digitally providing impedance mismatch compensation for a communications medium in a communications device. A method comprises producing a power amplifier (PA) output signal, providing the PA output signal to a digitally-controlled transmission line (DCTL), transforming a first load impedance to a second load impedance producing a DCTL output, and coupling the DCTL output to an antenna. The PA having the first load impedance and the transforming is controlled by a digital control word provided to the DCTL.
摘要翻译：一种用于数字地为通信设备中的通信介质提供阻抗失配补偿的系统和方法。一种方法包括产生功率放大器（PA）输出信号，将PA输出信号提供给数字控制传输线（DCTL），将第一负载阻抗变换到产生DCTL输出的第二负载阻抗，以及将DCTL输出耦合到天线。具有第一负载阻抗和变换的PA由提供给DCTL的数字控制字来控制。

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