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71. 发明申请

US20100293512A1 CHIP DESIGN AND FABRICATION METHOD OPTIMIZED FOR PROFIT 有权
标题翻译：芯片设计和优化方法优化
公开(公告)号：US20100293512A1
公开(公告)日：2010-11-18
申请号：US12467326
申请日：2009-05-18
申请人： Nathan Buck , Howard H. Chen , James P. Eckhardt , Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Susan K. Lichtensteiger , Chandramouli Visweswariah , Tad J. Wilder
发明人： Nathan Buck , Howard H. Chen , James P. Eckhardt , Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Susan K. Lichtensteiger , Chandramouli Visweswariah , Tad J. Wilder
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031
摘要： Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated. Based on this profit model, changes to the chip design can be made in order to optimize yield as a function of all of the diverse metrics (e.g., performance, power consumption, etc.) and further to maximize the profit potential of the resulting chips.
摘要翻译：公开了一种计算机实现的方法，用于设计芯片以优化不同仓中的产量部分作为多个不同度量的函数，并进一步最大化所得到的芯片仓的利润潜力。该方法分别计算联合概率分布（JPD），每个JPD是不同度量（例如，性能，功耗等）的函数。基于JPD，生成相应的收益率曲线。利润函数然后将所有这些度量（例如，绩效值，功耗值等）的值减小到公共利润分母（例如，指示可能与给定度量值相关联的利润的货币值）。更具体地说，利润函数，尤其是货币价值可用于将各种收益率曲线组合成基于利润的收益率曲线，从中可以产生利润模型。基于这种利润模型，可以对芯片设计进行改变，以便根据所有不同的指标（例如性能，功耗等）来优化产量，并进一步最大化所得芯片的利润潜力。

72. 发明授权

US07823115B2 Method of generating wiring routes with matching delay in the presence of process variation 有权
标题翻译：在存在过程变化的情况下生成具有匹配延迟的布线路线的方法
公开(公告)号：US07823115B2
公开(公告)日：2010-10-26
申请号：US12108629
申请日：2008-04-24
申请人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.
摘要翻译：电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且在第一布线路径和第二布线路径横越的各布线层内。此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。

73. 发明授权

US07555740B2 Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis 失效
标题翻译：基于路径的混合多角静态时序分析中统计灵敏度信用评估的方法和系统
公开(公告)号：US07555740B2
公开(公告)日：2009-06-30
申请号：US11679251
申请日：2007-02-27
申请人： Nathan C. Buck , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Kerim Kalafala , Peihua Qi , Chandramouli Visweswariah , Xiaoyue Wang
发明人： Nathan C. Buck , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Kerim Kalafala , Peihua Qi , Chandramouli Visweswariah , Xiaoyue Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an integrated circuit comprises: providing an initial static timing analysis of the integrated circuit; selecting a static timing test with respect to a static timing test point based on the initial static timing analysis; selecting a timing path leading to the static timing test point for the static timing test; determining an integrated slack path variability for the timing path based on a joint probability distribution of at least one statistically independent parameter; and analyzing the timing design based on the integrated slack path variability.
摘要翻译：公开了用于分析集成电路的时序设计的方法，系统和计算机程序产品。根据实施例，用于分析集成电路的定时设计的方法包括：提供集成电路的初始静态时序分析; 基于初始静态时序分析，选择静态定时测试点的静态定时测试; 选择通过静态定时测试的静态定时测试点的定时路径; 基于至少一个统计学独立参数的联合概率分布来确定所述定时路径的综合松弛路径可变性; 并基于综合的松弛路径变异性分析时序设计。

74. 发明申请

US20080313590A1 METHOD AND SYSTEM FOR EVALUATING TIMING IN AN INTEGRATED CIRCUIT 有权
标题翻译：用于评估集成电路中的时序的方法和系统
公开(公告)号：US20080313590A1
公开(公告)日：2008-12-18
申请号：US12183549
申请日：2008-07-31
申请人： Eric A. FOREMAN , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： Eric A. FOREMAN , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G01R31/3016
摘要： Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.
摘要翻译：用于分析集成电路中的定时并减少静态时序分析（STA）中定时松弛计算中的悲观情况的方法。该方法涉及分组和消除在早期和晚期电路路径中具有类似延迟的元件的延迟贡献。使用具有不同延迟的元件的延迟贡献来计算调整的定时松弛。在一些实施例中，具有不同延迟的元件的延迟贡献是根和平方。本发明的实施例提供了用于减少由于基于单元和线依赖的延迟引起的悲观的方法。在本发明的实施例中考虑的延迟可以包括由于路径中的元件的位置而导致的延迟。

75. 发明申请

US20080209375A1 Variable Threshold System and Method For Multi-Corner Static Timing Analysis 失效
标题翻译：多角度静态时序分析的可变阈值系统和方法
公开(公告)号：US20080209375A1
公开(公告)日：2008-08-28
申请号：US11679834
申请日：2007-02-27
申请人： Nathan C. Buck , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Kerim Kalafala , Peihua Qi , Chandramouli Visweswariah , Xiaoyue Wang
发明人： Nathan C. Buck , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Kerim Kalafala , Peihua Qi , Chandramouli Visweswariah , Xiaoyue Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and system for decreasing processing time in multi-corner static timing analysis. In one embodiment, slack cutoff values are assigned across a parameter process space. For example, a slack cutoff value is assigned to each parameter in a process space by determining an estimated maximum slack change between a starting corner and any other corner in a corresponding process sub-space. In another embodiment, parameters are ordered in a parameter order by decreasing magnitude of impact on variability of timing.
摘要翻译：一种用于减少多角静态时序分析中处理时间的方法和系统。在一个实施例中，在参数处理空间上分配松弛截止值。例如，通过确定起始角和对应的处理子空间中的任何其他角之间的估计的最大松弛变化，将一个松弛截止值分配给处理空间中的每个参数。在另一个实施例中，通过减小对定时可变性的影响的大小，以参数顺序排列参数。

76. 发明申请

US20080209374A1 Parameter Ordering For Multi-Corner Static Timing Analysis 失效
标题翻译：多角静态时序分析的参数排序
公开(公告)号：US20080209374A1
公开(公告)日：2008-08-28
申请号：US11679831
申请日：2007-02-27
申请人： Nathan C. Buck , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Kerim Kalafala , Peihua Qi , Chandramouli Visweswariah , Xiaoyue Wang
发明人： Nathan C. Buck , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Kerim Kalafala , Peihua Qi , Chandramouli Visweswariah , Xiaoyue Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and system for decreasing processing time in multi-corner static timing analysis. In one embodiment, parameters are ordered in a parameter order by decreasing magnitude of impact on variability of timing. In one example, a decreasing parameter order is utilized to order slack cutoff values that are assigned across a parameter process space. In another example, a decreasing parameter order is utilized to perform a multi-corner timing analysis on one or more dependent parameters in an independent fashion.
摘要翻译：一种用于减少多角静态时序分析中处理时间的方法和系统。在一个实施例中，通过减小对定时可变性的影响的大小，以参数顺序排列参数。在一个示例中，使用递减参数顺序来排序跨越参数处理空间分配的松弛截止值。在另一示例中，使用递减参数顺序来以独立方式对一个或多个依赖参数执行多角定时分析。

77. 发明申请

US20080201683A1 Method of Generating Wiring Routes with Matching Delay in the Presence of Process Variation 有权
公开(公告)号：US20080201683A1
公开(公告)日：2008-08-21
申请号：US12108629
申请日：2008-04-24
申请人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.

78. 发明授权

US07266474B2 Ring oscillator structure and method of separating random and systematic tolerance values 失效
标题翻译：环形振荡器结构和分离随机和系统容差值的方法
公开(公告)号：US07266474B2
公开(公告)日：2007-09-04
申请号：US11162197
申请日：2005-08-31
申请人： Peter A. Habitz , Jerry D. Hayes
发明人： Peter A. Habitz , Jerry D. Hayes
IPC分类号： G06F11/30 , H03K3/03 , G01R23/00
CPC分类号： G05B23/0221 , G01R31/2648
摘要： A ring oscillator test structure comprises at least two overlapping rings that are switchable between different numbers of stages. A delay distribution is measured for various numbers of stages in a set of oscillators formed in different locations subject to different systematic delay effects. The delay distributions are analyzed to isolate the systematic and the random contributions to the standard deviation of the distributions.
摘要翻译：环形振荡器测试结构包括可在不同数量级之间切换的至少两个重叠环。测量在不同位置处形成的一组振荡器中的不同数量的级的延迟分布，其受到不同的系统延迟效应的影响。分析延迟分布，分析系统和随机贡献与分布的标准偏差。

79. 发明授权

US06477686B1 Method of calculating 3-dimensional fringe characteristics using specially formed extension shapes 失效
标题翻译：使用特殊形状的延伸形状计算3维条纹特征的方法
公开(公告)号：US06477686B1
公开(公告)日：2002-11-05
申请号：US09560577
申请日：2000-04-27
申请人： L. William Dewey, III , Peter A. Habitz
发明人： L. William Dewey, III , Peter A. Habitz
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A structure and method for performing a capacitance extraction on an integrated circuit, includes determining a parallel-plate capacitance between devices on different levels within the integrated circuit, adding extension shapes around each of the devices, reducing an area of overlapping extension shapes, multiplying a remaining area of the extension shapes by a constant to produce a fringe capacitance; and summing the parallel-plate capacitance and the fringe capacitance.
摘要翻译：一种用于在集成电路上执行电容提取的结构和方法，包括：确定集成电路内不同级别的器件之间的平行板电容，在每个器件周围增加扩展形状，减少重叠扩展形状的面积，将延伸形状的剩余面积为常数以产生边缘电容; 并且平行板电容和边缘电容相加。

80. 发明授权

US06473887B1 Inclusion of global wires in capacitance extraction 失效
标题翻译：将全局线插入电容提取中
公开(公告)号：US06473887B1
公开(公告)日：2002-10-29
申请号：US09560065
申请日：2000-04-27
申请人： L. William Dewey, III , Peter A. Habitz , Edward W. Seibert
发明人： L. William Dewey, III , Peter A. Habitz , Edward W. Seibert
IPC分类号： G06F945
CPC分类号： G06F17/5036
摘要： A method and structure for performing capacitance extraction during the design of an integrated circuit includes inputting a specified wiring density and design requirements, determining a minimum spacing for wire segments based on the design requirements, calculating a transparency factor based on the wiring density, calculating a lateral capacitance assuming virtual wires are present in the integrated circuit, and calculating a vertical capacitance based on the transparency factor.
摘要翻译：在集成电路设计期间进行电容提取的方法和结构包括输入指定的布线密度和设计要求，根据设计要求确定线段的最小间距，根据布线密度计算透明度因子，计算出在集成电路中存在假想虚线的横向电容，并且基于透明度因子计算垂直电容。

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