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71. 发明授权

US08993407B2 Compact localized RRAM cell structure realized by spacer technology 有权
标题翻译：通过间隔技术实现紧凑的局部RRAM单元结构
公开(公告)号：US08993407B2
公开(公告)日：2015-03-31
申请号：US13683779
申请日：2012-11-21
申请人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek
发明人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/146 , H01L27/2445 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/1675 , H01L45/1691
摘要： An RRAM is disclosed with a vertical BJT selector. Embodiments include defining a STI region in a substrate, implanting dopants in the substrate to form a first polarity well around and below a bottom portion of the STI region, a second polarity channel over the well on opposite sides of the STI region, and a first polarity active area over each channel at the surface of the substrate, forming an RRAM liner on the active area and STI region, forming a sacrificial top electrode on the RRAM liner, forming spacers on opposite sides of the sacrificial top electrode, implanting a second polarity dopant in the active area on opposite sides of the sacrificial top electrode, forming a silicon oxide adjacent the spacers, removing at least a portion of the sacrificial top electrode forming a cavity, forming in the cavity inner spacers adjacent the spacers and a top electrode.
摘要翻译：公开了一种具有垂直BJT选择器的RRAM。实施例包括在衬底中限定STI区域，在衬底中注入掺杂剂以在STI区域的底部周围和下方形成第一极性，在STI区域的相对侧上的阱上的第二极性沟道，以及第一在衬底的表面上的每个通道上的极性有源区域，在有源区域和STI区域上形成RRAM衬垫，在RRAM衬垫上形成牺牲顶部电极，在牺牲顶部电极的相对侧上形成间隔物，注入第二极性在牺牲顶部电极的相对侧上的有源区域中形成掺杂剂，在间隔物附近形成氧化硅，去除形成空腔的牺牲顶部电极的至少一部分，在空腔中形成邻近间隔物的内部间隔物和顶部电极。

72. 发明授权

US08889494B2 Finfet 有权
公开(公告)号：US08889494B2
公开(公告)日：2014-11-18
申请号：US12980371
申请日：2010-12-29
申请人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
IPC分类号： H01L21/84 , H01L21/00 , H01L29/78 , H01L29/66
CPC分类号： H01L29/785 , H01L29/0847 , H01L29/66795 , H01L29/78603
摘要： A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduce height variations across the wafer. The fin type transistor may also include a counter doped region at least below the S/D regions to reduce parasitic capacitance to improve its performance.
摘要翻译：翅片型晶体管包括在衬底表面上的用于将晶体管的栅极与衬底隔离的介质层。电介质层包括非选择性蚀刻的表面，以产生翅片结构的顶部，其具有减小横跨晶片的高度变化。翅片型晶体管还可以包括至少低于S / D区的反掺杂区域，以减小寄生电容以改善其性能。

73. 发明申请

US20140167161A1 FLOATING BODY CELL 有权
标题翻译：浮动体细胞
公开(公告)号：US20140167161A1
公开(公告)日：2014-06-19
申请号：US13713393
申请日：2012-12-13
申请人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek
发明人： Shyue Seng Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7841 , H01L29/66545 , H01L29/78654
摘要： Methods of forming a floating body cell (FBC) with faster programming and lower refresh rate and the resulting devices are disclosed. Embodiments include forming a silicon on insulator (SOI) layer on a substrate; forming a band-engineered layer surrounding and/or on the SOI layer; forming a source region and a drain region with at least one of the source region and the drain region being on the band-engineered layer; and forming a gate on the SOI layer, between the source and drain regions.
摘要翻译：公开了具有更快编程和更低刷新率的浮体单元（FBC）的形成方法以及所得到的器件。实施例包括在基板上形成绝缘体上硅（SOI）层; 形成围绕和/或在SOI层上的带工程层; 形成源极区域和漏极区域，所述源极区域和漏极区域中的至少一个在所述带状工程化层上; 以及在SOI层上，在源区和漏区之间形成栅极。

74. 发明授权

US08674457B2 Methods to reduce gate contact resistance for AC reff reduction 有权
标题翻译：减少AC降低栅极接触电阻的方法
公开(公告)号：US08674457B2
公开(公告)日：2014-03-18
申请号：US12806354
申请日：2010-08-11
申请人： Eng Huat Toh , Elgin Quek , Chunshan Yin , Chung Foong Tan , Jae Gon Lee
发明人： Eng Huat Toh , Elgin Quek , Chunshan Yin , Chung Foong Tan , Jae Gon Lee
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/517
摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced gate contact resistance (and series resistance) for improved device performance. An impurity is implanted or deposited in the gate stack in an impurity region between the metal gate electrode and the gate contact layer. An anneal process is performed that converts the impurity region into a segregation layer which lowers the schottky barrier height (SBH) of the interface between the metal gate electrode (e.g., silicide) and gate contact layer (e.g., amorphous silicon). This results in lower gate contact resistance and effectively lowers the device's AC Reff.
摘要翻译：制造半导体器件的方法（和半导体器件）提供具有降低的栅极接触电阻（和串联电阻）的场效应晶体管（FET），以提高器件性能。在金属栅极电极和栅极接触层之间的杂质区域中将杂质注入或沉积在栅极堆叠中。执行退火处理，其将杂质区域转换成偏析层，其降低金属栅电极（例如，硅化物）和栅极接触层（例如非晶硅）之间的界面的肖特基势垒高度（SBH）。这导致较低的栅极接触电阻并有效降低器件的AC Reff。

75. 发明申请

US20130292756A1 METHOD AND APPARATUS FOR UTILIZING CONTACT-SIDEWALL CAPACITANCE IN A SINGLE POLY NON-VOLATILE MEMORY CELL 审中-公开
标题翻译：在单一非易失性存储器单元中使用接触式电容器的方法和装置
公开(公告)号：US20130292756A1
公开(公告)日：2013-11-07
申请号：US13463514
申请日：2012-05-03
申请人： Yan Zhe Tang , Elgin Quek
发明人： Yan Zhe Tang , Elgin Quek
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7883 , H01L27/11524 , H01L27/11558
摘要： An approach for utilizing electrical capacitance between a plurality of contacts and sidewalls to provide voltage coupling between a floating gate (FG) and a control gate (CG) is disclosed. Embodiments include providing an FG and a CG laterally separated from each other; coupling a plurality of parallel polysilicon lines to the FG; providing a plurality of contacts between the plurality of the parallel polysilicon lines and coupling the contacts to the CG; and forming an electrical capacitance between the plurality of contacts and sidewalls of the plurality of parallel polysilicon lines to provide voltage coupling between the CG and the FG.
摘要翻译：公开了一种利用多个触点和侧壁之间的电容来提供浮动栅极（FG）和控制栅极（CG）之间的电压耦合的方法。实施例包括提供彼此横向分离的FG和CG; 将多条平行多晶硅线耦合到FG; 在所述多个并行多晶硅线路之间提供多个触点，并将所述触点耦合到所述CG; 以及在多个并联多晶硅线的多个触点和侧壁之间形成电容，以提供CG与FG之间的电压耦合。

76. 发明授权

US08536558B1 RRAM structure with improved memory margin 有权
标题翻译： RRAM结构具有改善的记忆余量
公开(公告)号：US08536558B1
公开(公告)日：2013-09-17
申请号：US13562646
申请日：2012-07-31
申请人： Shyue Seng (Jason) Tan , Eng Huat Toh , Elgin Quek
发明人： Shyue Seng (Jason) Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L47/00
CPC分类号： H01L45/146 , H01L45/04 , H01L45/124 , H01L45/1683
摘要： Resistive random-access memory (RRAM) structures are formed with ultra-thin RRAM-functional layers, thereby improving memory margins. Embodiments include forming an interlayer dielectric (ILD) over a bottom electrode, forming a sacrificial layer over the ILD, removing a portion of the ILD and a portion of the sacrificial layer vertically contiguous with the portion of the ILD, forming a cell area, forming a metal layer within the cell area, forming an interlayer dielectric structure above or surrounded by and protruding above the metal layer, a top surface of the interlayer dielectric structure being coplanar with a top surface of the sacrificial layer, removing the sacrificial layer, forming a memory layer on the ILD and/or on side surfaces of the interlayer dielectric structure, and forming a dielectric layer surrounding at least a portion of the interlayer dielectric structure.
摘要翻译：电阻随机存取存储器（RRAM）结构由超薄的RRAM功能层组成，从而提高存储容量。实施例包括在底部电极上形成层间电介质（ILD），在ILD上形成牺牲层，去除ILD的一部分和与ILD的部分垂直邻接的部分牺牲层，形成细胞区域，形成细胞区域在所述电池区域内的金属层，在所述金属层的上方或之上形成层间电介质结构，所述层间电介质结构与所述牺牲层的顶表面共平面，去除所述牺牲层，形成在层间电介质结构的ILD和/或侧表面上的存储层，以及形成围绕至少一部分层间电介质结构的电介质层。

77. 发明授权

US08530310B2 Memory cell with improved retention 有权
标题翻译：记忆单元具有改善的保留
公开(公告)号：US08530310B2
公开(公告)日：2013-09-10
申请号：US12650561
申请日：2009-12-31
申请人： Lee Wee Teo , Chunshan Yin , Shyue Seng Tan , Chung Foong Tan , Jae Gon Lee , Elgin Quek , Purakh Raj Verma
发明人： Lee Wee Teo , Chunshan Yin , Shyue Seng Tan , Chung Foong Tan , Jae Gon Lee , Elgin Quek , Purakh Raj Verma
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： B82Y10/00 , H01L21/28273 , H01L27/11521
摘要： A method for forming a device is presented. A substrate prepared with a feature having first and second adjacent surfaces is provided. A device layer is formed on the first and second adjacent surfaces of the feature. A first portion of the device layer over the first adjacent surface includes nano-crystals, whereas a second portion of the device layer over the second adjacent surface is devoid of nano-crystals.
摘要翻译：提出了一种形成装置的方法。提供了具有具有第一和第二相邻表面的特征的基底。器件层形成在特征的第一和第二相邻表面上。第一相邻表面上的器件层的第一部分包括纳米晶体，而第二相邻表面上的器件层的第二部分没有纳米晶体。

78. 发明申请

US20130221308A1 COMPACT RRAM DEVICE AND METHODS OF MAKING SAME 有权
标题翻译：紧凑的RRAM设备及其制造方法
公开(公告)号：US20130221308A1
公开(公告)日：2013-08-29
申请号：US13408221
申请日：2012-02-29
申请人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
发明人： Eng Huat Toh , Elgin Quek , Shyue Seng Tan
IPC分类号： H01L45/00
CPC分类号： H01L45/04 , H01L27/2436 , H01L27/2463 , H01L45/1206 , H01L45/1226 , H01L45/146 , H01L45/147
摘要： Disclosed herein is a compact RRAM (Resistance Random Access Memory) device structure and various methods of making such an RRAM device. In one example, a device disclosed herein includes a gate electrode, a conductive sidewall spacer and at least one variable resistance material layer positioned between the gate electrode and the conductive sidewall spacer.
摘要翻译：这里公开了紧凑的RRAM（电阻随机存取存储器）装置结构和制造这种RRAM装置的各种方法。在一个示例中，本文公开的器件包括栅极，导电侧壁隔离物和位于栅电极和导电侧壁间隔物之间的至少一个可变电阻材料层。

79. 发明授权

US08440533B2 Self-aligned contact for replacement metal gate and silicide last processes 有权
标题翻译：用于替换金属栅极和硅化物最后工艺的自对准触点
公开(公告)号：US08440533B2
公开(公告)日：2013-05-14
申请号：US13041134
申请日：2011-03-04
申请人： Eng Huat Toh , Elgin Quek
发明人： Eng Huat Toh , Elgin Quek
IPC分类号： H01L21/336
CPC分类号： H01L27/088 , H01L21/28518 , H01L21/76801 , H01L21/76816 , H01L21/76834 , H01L21/76897 , H01L21/823475 , H01L29/78
摘要： A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on an STI region, and a first ILD between the metal gate stacks, forming an etch stop layer and a second ILD sequentially over the substrate, with openings in the second ILD over the metal gate stacks, forming spacers on the edges of the openings, forming a third ILD over the second ILD and the spacers, removing the first ILD over the source/drain regions, removing the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the spacers, and over a portion of the spacers, forming first trenches, removing the third ILD over the second high-k metal gate stack and over a portion of the spacers, forming second trenches, and forming contacts in the first and second trenches.
摘要翻译：高K /金属栅极半导体器件具有较大的自对准触点，电阻降低。实施例包括在源极/漏极区域之间的衬底上形成第一高k金属栅极堆叠，在STI区域上形成第二高k金属栅极堆叠以及在金属栅极堆叠之间形成第一ILD，形成蚀刻停止层和在衬底上顺序地具有第二ILD，在金属栅堆叠上的第二ILD中具有开口，在开口的边缘上形成间隔物，在第二ILD和间隔物上形成第三ILD，在源/漏区上去除第一ILD 在邻近间隔物的源极/漏极区域上以及在间隔物的一部分上方去除蚀刻停止层，第二ILD和第三ILD，形成第一沟槽，在第二高k金属栅极上去除第三ILD 堆叠和一部分间隔物，形成第二沟槽，并在第一和第二沟槽中形成接触。

80. 发明申请

US20130037877A1 DOUBLE GATED FLASH MEMORY 有权
标题翻译：双重放置闪存
公开(公告)号：US20130037877A1
公开(公告)日：2013-02-14
申请号：US13206780
申请日：2011-08-10
申请人： Shyue Seng (Jason) Tan , Eng Huat Toh , Elgin Quek
发明人： Shyue Seng (Jason) Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/0425 , G11C16/14 , G11C16/26 , H01L21/28273 , H01L29/42328 , H01L29/66795 , H01L29/66825 , H01L29/7851 , H01L29/7881
摘要： A split gate memory cell is fabricated with a fin structure between a memory gate stack and a select gate. Embodiments include a first channel region under the memory gate stack and a second channel region under the select gate.
摘要翻译：在存储器栅极堆叠和选择栅极之间制造具有鳍结构的分离栅极存储器单元。实施例包括存储器栅极堆叠下方的第一沟道区域和选择栅极下方的第二沟道区域。

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