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    • 71. 发明授权
    • Switched-capacitor sigma-delta analog-to-digital converter with input
voltage overload protection
    • 具有输入电压过载保护的开关电容Σ-Δ模数转换器
    • US06040793A
    • 2000-03-21
    • US40620
    • 1998-03-18
    • Paul F. Ferguson, Jr.James Wilson
    • Paul F. Ferguson, Jr.James Wilson
    • H03M3/02H03M3/00H03M1/12
    • H03M3/44H03M3/43
    • A sigma-delta analog-to-digital converter includes an integrator having an input and an output and an integrator capacitor connected between the input and output. A switched-capacitor input circuit includes at least one input capacitor, an input sampling switching circuit and an input delivery switching circuit. The input sampling switching circuit includes at least one input sampling switch operable to connect the input capacitor to be charged by an input voltage at a sampling rate. The input delivery switching circuit includes at least one input delivery switch operable to connect the input capacitor to transfer charge to the integrator capacitor at a first transfer rate. A switched-capacitor feedback circuit is connected in a feedback path between the input and output of the integrator. The feedback circuit includes at least one feedback capacitor, a feedback sampling switching circuit and a feedback delivery switching circuit. The feedback sampling switching circuit includes at least one feedback sampling switch operable to connect the feedback capacitor to be charged by a feedback reference voltage at the sampling rate. The feedback delivery switching circuit includes at least one feedback delivery switch operable to connect the feedback capacitor to transfer charge to the integrator capacitor at a second transfer rate. The second transfer rate is a predetermined factor greater than the first transfer rate such that the sampled feedback reference voltage charge is transferred to the integrator capacitor at a greater rate than the transfer of the sampled input voltage charge to prevent modulator instability due to an input overload condition.
    • Σ-Δ模数转换器包括具有输入和输出的积分器以及连接在输入和输出之间的积分电容器。 开关电容器输入电路包括至少一个输入电容器,输入采样开关电路和输入输出切换电路。 输入采样开关电路包括至少一个输入采样开关,其可操作以以采样率将输入电容器连接到输入电压。 输入传送切换电路包括至少一个输入传送开关,其可操作以连接输入电容器,以第一传送速率将电荷传送到积分器电容器。 开关电容反馈电路连接在积分器的输入和输出之间的反馈路径中。 反馈电路包括至少一个反馈电容器,反馈采样开关电路和反馈传递切换电路。 反馈采样开关电路包括至少一个反馈采样开关,其可操作以以采样率将反馈电容器连接到反馈参考电压。 反馈传送切换电路包括至少一个反馈传递开关,其可操作以连接反馈电容器以以第二传送速率将电荷传递到积分器电容器。 第二传送速率是大于第一传送速率的预定因子,使得采样的反馈参考电压电荷以比采样的输入电压电荷的传送更大的速率传送到积分器电容器,以防止调制器由于输入过载引起的不稳定 条件。
    • 72. 发明授权
    • Digital to analog conversion using nonuniform sample rates
    • 使用不均匀采样率进行数模转换
    • US5712635A
    • 1998-01-27
    • US612944
    • 1996-08-29
    • James WilsonRonald A. CelliniJames M. Sobol
    • James WilsonRonald A. CelliniJames M. Sobol
    • H03M1/66H03H17/06H03L7/08H03L7/093H03L7/099H03M3/02H03M7/36
    • H03H17/06H03H17/0614H03H17/0628H03L7/08H03L7/093H03L7/0992H03M3/372H03L2207/50H03M3/50
    • A method and apparatus for digital to analog conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that errors produced by nonuniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques In one embodiment, the digital data is interpolated by a fixed ratio and then decimated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the incoming digital data stream. In another embodiment, the digital data is interpolated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the incoming digital data stream and then decimated by a fixed ratio. The frequency signal selection number is modulated using an n-th order m-bit sigma-delta modulator. Data thus emerges from the interpolation/decimation process at the clock rate of the n-th order m-bit sigma-delta modulator. The method and apparatus converts the data rate of the incoming digital data stream to the data rate of the n-th order m-bit sigma-delta modulator.
    • PCT No.PCT / US94 / 10269 Sec。 371日期:1996年8月29日 102(e)日期1996年8月29日PCT 1994年9月13日PCT公布。 公开号WO95 / 08221 日期1995年3月23日一种使用Σ-Δ调制数字样本之间的时间间隔进行数模转换的方法和装置。 本发明的方法和装置提供了时基的Σ-Δ调制,使得由不均匀采样产生的误差是频率形状的区域(即,转移到较高频率),其中它们可以通过常规滤波技术 在一个实施例中,数字数据以固定比例内插,然后在Σ-Δ调制频率选择信号的控制下抽取,该Σ-Δ调制频率选择信号平均表示输入数字数据流的数据速率。 在另一个实施例中,数字数据在Σ-Δ调制频率选择信号的控制下进行内插,该Σ-Δ调制频率选择信号平均表示输入数字数据流的数据速率,然后以固定比率抽取。 使用第n级m位Σ-Δ调制器来调制频率信号选择数。 因此,数据因此在第n级m位Σ-Δ调制器的时钟速率下从内插/抽取处理中出现。 该方法和装置将输入的数字数据流的数据速率转换为第n阶m位Σ-Δ调制器的数据速率。
    • 73. 发明授权
    • Variable sample rate ADC
    • US5619202A
    • 1997-04-08
    • US343713
    • 1994-11-22
    • James WilsonRonald A. CelliniJames M. Sobol
    • James WilsonRonald A. CelliniJames M. Sobol
    • H03M3/02H03M1/00
    • H03M3/372H03M3/50
    • A method and apparatus for analog-to-digital conversion using sigma-delta modulation of the temporal spacing between digital samples are provided. The method and apparatus include sigma-delta modulation of the time-base such that errors produced by non-uniform sampling are frequency-shaped to a high frequency region where they are reduced by conventional digital filtering techniques. In one embodiment, a sigma-delta ADC receives an analog input signal and converts the analog input signal to digital samples at an oversampling rate. A decimator, coupled to the sigma-delta ADC, receives the digital samples and decimates the digital samples to produce the digital samples at a preselected output sample rate, less than the oversampling rate. An ADC sample rate control circuit, coupled to the ADC, receives a frequency select signal representing the preselected output sample rate, and produces a noise-shaped clock signal for controlling operation of the ADC at the oversampling rate. The control circuit includes a sigma-delta modulator for sigma-delta modulating the frequency select signal. A randomizer/suppressor circuit, under control of the output of the sigma-delta modulator, receives an input clock signal and adjusts the frequency of the clock signal to produce a noise-shaped clock signal for controlling the oversampling rate of the ADC.