专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US09270278B2 Spin transfer torque based memory elements for programmable device arrays 有权
标题翻译：用于可编程器件阵列的基于转移转矩的存储元件
公开(公告)号：US09270278B2
公开(公告)日：2016-02-23
申请号：US13997962
申请日：2012-03-30
申请人： Arijit Raychowdhury , James W. Tschanz , Vivek De
发明人： Arijit Raychowdhury , James W. Tschanz , Vivek De
IPC分类号： H03K19/177 , G11C11/16
CPC分类号： H03K19/17728 , G11C11/16 , H03K19/177
摘要： Disclosed herein are semiconductor device arrays, such as, Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Arrays (CPLAs) that use high-density Spin Transfer Torque (STT)-based memory elements. STT-based memory elements can either be stand-alone FPGAs/CPLAs, or can be embedded in microprocessors and/or digital signal processing (DSP) system-on-chip (SoC) to provide design flexibility for implementing low power, scalable, secure and reconfigurable hardware architecture. Because the configuration is stored on the FPGA/CPLA die itself, the need for loading the configuration from external storage every time is eliminated when the device is powered on. In addition to instant startup, eliminating configuration I/O traffic results in power savings and possible pin count reduction. Security is greatly improved by eliminating the need to store configuration data in an external memory.
摘要翻译：这里公开了使用基于高密度旋转转矩（STT）的存储器元件的半导体器件阵列，诸如现场可编程门阵列（FPGA）和复数可编程逻辑阵列（CPLAs）。基于STT的存储器元件可以是独立的FPGA / CPLAs，或者可以嵌入在微处理器和/或数字信号处理（DSP）片上系统（SoC）中，以提供设计灵活性，以实现低功率，可扩展，安全和可重构硬件架构。由于配置存储在FPGA / CPLA裸片本身，所以每次在外部存储器上加载配置的需求都将在设备通电时被消除。除了即时启动，消除配置I / O流量导致节电和可能的引脚数减少。通过消除将配置数据存储在外部存储器中的需要，安全性大大提高。

72. 发明申请

US20140108733A1 DISABLING CACHE PORTIONS DURING LOW VOLTAGE OPERATIONS 审中-公开
标题翻译：在低电压运行期间禁用高速缓存部分
公开(公告)号：US20140108733A1
公开(公告)日：2014-04-17
申请号：US13652480
申请日：2012-10-16
申请人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
发明人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F1/3243 , G06F12/0804 , G06F2212/1028 , Y02D10/13 , Y02D10/152
摘要： Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
摘要翻译：描述了在低电压操作期间禁用一个或多个高速缓存部分的方法和装置。在一些实施例中，一个或多个额外的比特可以用于高速缓存的一部分，其指示高速缓存的部分是否能够在Vccmin等级或更低的值下运行。还描述和要求保护其他实施例。

73. 发明授权

US08667367B2 Memory cell supply voltage control based on error detection 有权
标题翻译：基于错误检测的存储单元电源电压控制
公开(公告)号：US08667367B2
公开(公告)日：2014-03-04
申请号：US13215949
申请日：2011-08-23
申请人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
发明人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
IPC分类号： G11C29/00
CPC分类号： G11C29/42 , G11C11/4125 , G11C11/417 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C2029/0409 , G11C2029/0411 , G11C2029/5004
摘要： Described herein is an apparatus for adjusting a power supply level for a memory cell to improve stability of a memory unit. The apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error.
摘要翻译：这里描述了一种用于调整存储器单元的电源电平以提高存储器单元的稳定性的装置。该装置包括存储器电路，其包括存储器单元，用于检测由存储器电路的存储器单元存储的数据中的错误的误差检测电路，以及供应电压控制电路，用于至少部分地增加存储器电路的一个或多个存储器单元的电源电压检测到错误。

74. 发明申请

US20110307761A1 MEMORY CELL SUPPLY VOLTAGE CONTROL BASED ON ERROR DETECTION 有权
标题翻译：基于错误检测的存储单元电源电压控制
公开(公告)号：US20110307761A1
公开(公告)日：2011-12-15
申请号：US13215949
申请日：2011-08-23
申请人： Khellah Muhammad , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
发明人： Khellah Muhammad , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
IPC分类号： G11C29/00
CPC分类号： G11C29/42 , G11C11/4125 , G11C11/417 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C2029/0409 , G11C2029/0411 , G11C2029/5004
摘要： For one disclosed embodiment, an apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error. Other embodiments are also disclosed.
摘要翻译：对于一个所公开的实施例，一种装置包括存储器电路，其包括存储器单元，用于检测由存储器电路的存储器单元存储的数据中的错误的错误检测电路，以及用于增加存储器电路的一个或多个存储器单元的电源电压至少部分地基于检测到的错误。还公开了其他实施例。

75. 发明申请

US20100118637A1 Circuts and methods for reducing minimum supply for register file cells 有权
标题翻译：用于减少寄存器文件单元的最小供应的循环和方法
公开(公告)号：US20100118637A1
公开(公告)日：2010-05-13
申请号：US12291433
申请日：2008-11-10
申请人： Vivek De , DiaaElden S. Khalil , Muhammad Kellah , Moty Mehalel , George Shchupak
发明人： Vivek De , DiaaElden S. Khalil , Muhammad Kellah , Moty Mehalel , George Shchupak
IPC分类号： G11C5/14
CPC分类号： G11C5/142 , G11C5/063 , G11C11/412 , G11C11/413
摘要： A register file employing a shared supply structure to improve the minimum supply voltage.
摘要翻译：采用共享供电结构的寄存器文件来提高最小电源电压。

76. 发明授权

US07653846B2 Memory cell bit valve loss detection and restoration 有权
标题翻译：存储单元位阀失效检测和恢复
公开(公告)号：US07653846B2
公开(公告)日：2010-01-26
申请号：US11648490
申请日：2006-12-28
申请人： Nam Sung Kim , Muhammad Kheliah , Yibin Ye , Dinesh Somasekhar , Vivek De
发明人： Nam Sung Kim , Muhammad Kheliah , Yibin Ye , Dinesh Somasekhar , Vivek De
IPC分类号： G11C29/00
CPC分类号： G11C11/419 , G11C11/41 , G11C29/38 , G11C29/50 , G11C2029/0409
摘要： For one embodiment, an apparatus may include a memory cell to store a bit value, wherein the memory cell may lose the bit value in response to a memory access operation. The apparatus may also include first circuitry to detect whether the memory cell loses the bit value in response to the memory access operation and second circuitry to restore the bit value in the memory cell in response to detection that the memory cell loses the bit value. Other embodiments include other apparatuses, methods, and systems.
摘要翻译：对于一个实施例，装置可以包括存储单元以存储位值，其中存储单元可能会响应于存储器访问操作而丢失位值。该装置还可以包括第一电路，用于响应于检测到存储器单元丢失比特值来检测存储器单元是否响应于存储器访问操作而丢失位值以及第二电路来恢复存储器单元中的位值。其他实施例包括其他装置，方法和系统。

77. 发明授权

US07558097B2 Memory having bit line with resistor(s) between memory cells 有权
标题翻译：存储器与存储器单元之间的电阻器具有位线
公开(公告)号：US07558097B2
公开(公告)日：2009-07-07
申请号：US11648399
申请日：2006-12-28
申请人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
发明人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C11/413
摘要： For one disclosed embodiment, an integrated circuit may comprise a memory array on the integrated circuit and access control circuitry on the integrated circuit. The memory array may have a bit line with one or more resistors along the bit line and may have a plurality of memory cells coupled to the bit line at a plurality of locations along the bit line. At least one resistor along the bit line may be between two locations at which memory cells are coupled to the bit line. The access control circuitry may be to select a memory cell coupled to the bit line and to sense a signal on the bit line from the selected memory cell. Other embodiments are also disclosed.
摘要翻译：对于一个公开的实施例，集成电路可以包括集成电路上的存储器阵列和集成电路上的访问控制电路。存储器阵列可以具有沿着位线的一个或多个电阻器的位线，并且可以具有沿着位线的多个位置处耦合到位线的多个存储器单元。沿着位线的至少一个电阻器可以在存储器单元耦合到位线的两个位置之间。访问控制电路可以是选择耦合到位线的存储器单元并且感测来自所选存储单元的位线上的信号。还公开了其他实施例。

78. 发明申请

US20080162986A1 Memory cell bit valve loss detection and restoration 有权
标题翻译：存储单元位阀失效检测和恢复
公开(公告)号：US20080162986A1
公开(公告)日：2008-07-03
申请号：US11648490
申请日：2006-12-28
申请人： Nam Sung Kim , Muhammad Khellah , Yibin Ye , Dinesh Somasekhar , Vivek De
发明人： Nam Sung Kim , Muhammad Khellah , Yibin Ye , Dinesh Somasekhar , Vivek De
IPC分类号： G06F11/00
CPC分类号： G11C11/419 , G11C11/41 , G11C29/38 , G11C29/50 , G11C2029/0409
摘要： For one disclosed embodiment, an apparatus may comprise a memory cell to store a bit value, wherein the memory cell may lose the bit value in response to a memory access operation. The apparatus may also comprise first circuitry to detect whether the memory cell loses the bit value in response to the memory access operation and second circuitry to restore the bit value in the memory cell in response to detection that the memory cell loses the bit value. Other embodiments are also disclosed.
摘要翻译：对于一个所公开的实施例，装置可以包括存储单元以存储位值，其中存储单元可以响应于存储器访问操作而丢失位值。该装置还可以包括第一电路，用于响应于存储器单元丢失比特值的检测，检测存储器单元是否响应于存储器访问操作而丢失比特值以及第二电路来恢复存储器单元中的比特值。还公开了其他实施例。

79. 发明申请

US20080158932A1 Memory having bit line with resistor(s) between memory cells 有权
标题翻译：存储器与存储器单元之间的电阻器具有位线
公开(公告)号：US20080158932A1
公开(公告)日：2008-07-03
申请号：US11648399
申请日：2006-12-28
申请人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
发明人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C11/413
摘要： For one disclosed embodiment, an integrated circuit may comprise a memory array on the integrated circuit and access control circuitry on the integrated circuit. The memory array may have a bit line with one or more resistors along the bit line and may have a plurality of memory cells coupled to the bit line at a plurality of locations along the bit line. At least one resistor along the bit line may be between two locations at which memory cells are coupled to the bit line. The access control circuitry may be to select a memory cell coupled to the bit line and to sense a signal on the bit line from the selected memory cell. Other embodiments are also disclosed.
摘要翻译：对于一个公开的实施例，集成电路可以包括集成电路上的存储器阵列和集成电路上的访问控制电路。存储器阵列可以具有沿着位线的一个或多个电阻器的位线，并且可以具有沿着位线的多个位置处耦合到位线的多个存储器单元。沿着位线的至少一个电阻器可以在存储器单元耦合到位线的两个位置之间。访问控制电路可以是选择耦合到位线的存储器单元并且感测来自所选存储单元的位线上的信号。还公开了其他实施例。

80. 发明授权

US07274250B2 Low-voltage, buffered bandgap reference with selectable output voltage 有权
标题翻译：具有可选输出电压的低电压，缓冲带隙基准
公开(公告)号：US07274250B2
公开(公告)日：2007-09-25
申请号：US11170559
申请日：2005-06-28
申请人： Peter Hazucha , Sung T. Moon , Gerhard Schrom , Fabrice Paillet , Tanay Karnik , Vivek De
发明人： Peter Hazucha , Sung T. Moon , Gerhard Schrom , Fabrice Paillet , Tanay Karnik , Vivek De
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A temperature-independent voltage reference containing two independent bias circuits powered by the reference voltage, each bias circuit containing components with an exponential dependence of current on voltage and one containing a resistive impedance, and further including voltage dividers and an active component.
摘要翻译：独立于温度的电压基准包含由参考电压供电的两个独立偏置电路，每个偏置电路包含电流与电压的指数关系的分量，以及包含电阻阻抗的分量，并且还包括分压器和有源分量。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式