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71. 发明授权

US06728866B1 Partitioned issue queue and allocation strategy 失效
标题翻译：分区问题队列和分配策略
公开(公告)号：US06728866B1
公开(公告)日：2004-04-27
申请号：US09652049
申请日：2000-08-31
申请人： James Allan Kahle , Charles Roberts Moore
发明人： James Allan Kahle , Charles Roberts Moore
IPC分类号： G06F930
CPC分类号： G06F9/384 , G06F9/3828 , G06F9/3838 , G06F9/3891
摘要： A microprocessor and method of processing instructions for addressing timing assymetries are disclosed. A sequence of instructions including a first instruction and a second instruction are received. Dependency logic determines if any dependencies between the first and second instructions. The dependency logic then selects between first and second issue queue partitions for storing the first and second instructions pending issue based upon the dependency determination, wherein the first issue queue partition issues instructions to a first execution unit and the second issue queue partition issues instructions to a second execution unit. The first and second issue queue partitions may be asymmetric with respect to a first register file in which instruction results are stored. The first and second instructions are then stored in the selected partitions. Selecting between the first and second issue queue partitions may include selecting a common issue queue partition for the first and second instructions if there is a dependency between the first and second instructions and selecting between the first and second issue queue partition may be based upon a fairness algorithm if the first and second instructions lack dependencies.
摘要翻译：公开了一种用于处理定时比较的处理指令的微处理器和方法。接收包括第一指令和第二指令的指令序列。依赖逻辑确定第一和第二条指令之间是否有依赖关系。所述依赖性逻辑然后在第一和第二发布队列分区之间选择用于基于所述依赖性确定存储所述第一和第二指令等待发布，其中所述第一问题队列分区向第一执行单元发出指令，并且所述第二发布队列分区向第二执行单元。相对于其中存储指令结果的第一寄存器文件，第一和第二问题队列分区可以是不对称的。然后将第一和第二指令存储在所选择的分区中。在第一和第二发布队列分区之间的选择可以包括为第一和第二指令选择共同的问题队列分区，如果在第一和第二指令之间存在依赖关系，并且在第一和第二发布队列之间的选择可以基于公平性算法如果第一个和第二个指令缺乏依赖关系。

72. 发明授权

US06678820B1 Processor and method for separately predicting conditional branches dependent on lock acquisition 失效
标题翻译：用于单独预测依赖于锁获取的条件分支的处理器和方法
公开(公告)号：US06678820B1
公开(公告)日：2004-01-13
申请号：US09538993
申请日：2000-03-30
申请人： James Allan Kahle , Charles Roberts Moore
发明人： James Allan Kahle , Charles Roberts Moore
IPC分类号： G06F900
CPC分类号： G06F9/30181 , G06F9/3848
摘要： A processor having improved branch prediction accuracy includes at least one execution unit that executes sequential instructions and a plurality of branch prediction circuits including a lock acquisition branch prediction circuit that predicts a speculative execution path for a conditional branch instruction. The processor further includes a selector that selects the speculative execution path predicted by the lock acquisition branch prediction circuit in response to an indication that the conditional branch instruction is dependent upon lock acquisition. In a preferred embodiment, the indication that the conditional branch instruction is dependent upon lock acquisition is encoded within the conditional branch instruction.
摘要翻译：具有改进的分支预测精度的处理器包括执行顺序指令的至少一个执行单元和包括锁定获取分支预测电路的多个分支预测电路，该预测电路预测条件转移指令的推测执行路径。处理器还包括选择器，其响应于条件分支指令取决于锁获取的指示，选择由锁获取分支预测电路预测的推测执行路径。在优选实施例中，条件分支指令依赖于锁获取的指示被编码在条件分支指令内。

73. 发明授权

US06658558B1 Branch prediction circuit selector with instruction context related condition type determining 有权
标题翻译：具有指令上下文相关条件类型确定的分支预测电路选择器
公开(公告)号：US06658558B1
公开(公告)日：2003-12-02
申请号：US09538991
申请日：2000-03-30
申请人： James Allan Kahle , Charles Roberts Moore
发明人： James Allan Kahle , Charles Roberts Moore
IPC分类号： G06F938
CPC分类号： G06F9/3861 , G06F9/30094 , G06F9/30101 , G06F9/3806 , G06F9/3846 , G06F9/3848
摘要： A processor having improved branch prediction accuracy includes at least one execution unit that executes sequential instructions and branch processing circuitry that processes branch instructions. The branch processing circuitry includes a number of branch prediction circuits that are each capable of providing a branch prediction for a conditional branch instruction and a selector that selects a branch prediction of a branch prediction circuit based upon the type of condition upon which the conditional branch instruction depends. The selector preferably includes hardware that determines the type of condition upon which the conditional branch instruction depends by reference to an instruction context defined by one or more instructions adjacent the conditional branch instruction in programmed sequence. The branch processing circuitry further includes path address logic that determines a path address of the selected branch prediction. Thus, branch prediction accuracy can be improved by considering the type of condition upon which a conditional branch instruction depends, rather than just branch history.
摘要翻译：具有改进的分支预测精度的处理器包括执行顺序指令的至少一个执行单元和处理分支指令的分支处理电路。分支处理电路包括多个分支预测电路，每个分支预测电路能够为条件分支指令提供分支预测，以及选择器，其基于条件分支指令的条件类型来选择分支预测电路的分支预测依靠。选择器优选地包括硬件，硬件通过参考由编程序列中的与条件分支指令相邻的一个或多个指令定义的指令上下文来确定条件转移指令所依赖的条件类型。分支处理电路还包括确定所选分支预测的路径地址的路径地址逻辑。因此，通过考虑条件分支指令所依赖的条件的类型而不仅仅是分支历史，可以提高分支预测精度。

74. 发明授权

US06658555B1 Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipeline 有权
公开(公告)号：US06658555B1
公开(公告)日：2003-12-02
申请号：US09435077
申请日：1999-11-04
申请人： James Allan Kahle , Hung Qui Le , Charles Roberts Moore , David James Shippy , Larry Edward Thatcher
发明人： James Allan Kahle , Hung Qui Le , Charles Roberts Moore , David James Shippy , Larry Edward Thatcher
IPC分类号： G06F930
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/3865 , G06F9/3867 , G06F9/3885
摘要： A microprocessor and related method and data processing system are disclosed. The microprocessor includes a dispatch unit suitable for issuing an instruction executable by the microprocessor, an execution pipeline configured to receive the issued instruction, and a pending instruction unit. The pending instruction unit includes a set of pending instruction entries. A copy of the issued instruction is maintained in one of the set of pending instruction entries. The execution pipeline is adapted to record, in response detecting to a condition preventing the instruction from successfully completing one of the stages in the pipeline during a current cycle, an exception status with the copy of the instruction in the pending instruction unit and to advance the instruction to a next stage in the pipeline in the next cycle thereby preventing the condition from stalling the pipeline. Preferably, the dispatch unit, in response to the instruction finishing pipeline execution with an exception status, is adapted to use the copy of the instruction to re-issue the instruction to the execution pipeline in a subsequent cycle. In one embodiment, the dispatch unit is adapted to deallocate the copy of the instruction in the pending instruction unit in response to the instruction successfully completing pipeline execution. The pending instruction unit may detect successful completion of the instruction by detecting when the instruction has been pending for a predetermined number of cycles without recording an exception status. In this embodiment, each entry in the pending instruction unit may include a timer field comprising a set of bits wherein the number of bits in the time field equals the predetermined number of cycles. The pending instruction unit may set, in successive cycles, successive bits in the timer field such that successful completion of an instruction is indicated when a last bit in the time field is set. In one embodiment, pending instruction unit includes a set of copies of instructions corresponding to each of a set of instructions pending in the execution pipeline at any given time. In various embodiments, the execution pipeline may comprise a load/store pipeline, a floating point pipeline, or a fixed point pipeline.

75. 发明授权

US09703516B2 Configurable interface controller 有权
公开(公告)号：US09703516B2
公开(公告)日：2017-07-11
申请号：US13269583
申请日：2011-10-08
申请人： Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle
发明人： Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle
IPC分类号： G06F3/00 , G06F3/14 , G09G5/14
CPC分类号： G06F3/1423 , G06F3/1454 , G09G5/14 , G09G2360/121 , G09G2370/04
摘要： A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization.

76. 发明申请

US20120030386A1 Configurable Interface Controller 审中-公开
标题翻译：可配置接口控制器
公开(公告)号：US20120030386A1
公开(公告)日：2012-02-02
申请号：US13269583
申请日：2011-10-08
申请人： Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle
发明人： Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle
IPC分类号： G06F13/36
CPC分类号： G06F3/1423 , G06F3/1454 , G09G5/14 , G09G2360/121 , G09G2370/04
摘要： A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization.
摘要翻译：灵活的输入/输出控制器逻辑与现有的输入/输出控制器（IOC）进行接口，以便配置向国际奥委会发送和接收的数据量。灵活的I / O接口以特定组件确定的速率从组件接收数据。然后，灵活的I / O接口以适合于I / O控制器的速率将接收的数据馈送到传统的I / O控制器。因此，保持与各个I / O控制器的接口。灵活的I / O逻辑平衡多个独立I / O控制器之间的带宽，以便更好地利用整个系统I / O带宽。在一个实施例中，在系统构建期间确定由灵活I / O逻辑管理的I / O配置，而在另一实施例中，在系统初始化期间设置I / O配置。

77. 发明授权

US08010716B2 Methods and apparatus for supporting multiple configurations in a multi-processor system 有权
标题翻译：在多处理器系统中支持多种配置的方法和装置
公开(公告)号：US08010716B2
公开(公告)日：2011-08-30
申请号：US12858915
申请日：2010-08-18
申请人： Takeshi Yamazaki , Scott Douglas Clark , Charles Ray Johns , James Allan Kahle
发明人： Takeshi Yamazaki , Scott Douglas Clark , Charles Ray Johns , James Allan Kahle
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F12/0815 , G06F12/0835
摘要： Methods and apparatus provide for interconnecting one or more multiprocessors and one or more external devices through one or more configurable interface circuits, which are adapted for operation in: (i) a first mode to provide a coherent symmetric interface; or (ii) a second mode to provide a non-coherent interface.
摘要翻译：方法和装置提供通过一个或多个可配置接口电路来互连一个或多个多处理器和一个或多个外部设备，其适于在以下操作中操作：（i）提供一致对称接口的第一模式; 或（ii）提供非相干界面的第二模式。

78. 发明授权

US07814281B2 Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment 有权
标题翻译：在非对称异构多处理器环境中提供原子更新原语的方法
公开(公告)号：US07814281B2
公开(公告)日：2010-10-12
申请号：US11468317
申请日：2006-08-30
申请人： Michael Norman Day , Charles Ray Johns , James Allan Kahle , Peichum Peter Liu , Thuong Quang Truong
发明人： Michael Norman Day , Charles Ray Johns , James Allan Kahle , Peichum Peter Liu , Thuong Quang Truong
IPC分类号： G06F13/00
CPC分类号： G06F13/28 , G06F9/3004 , G06F9/30087 , G06F12/0831 , G06F2213/0038
摘要： The present invention provides for atomic update primitives in an asymmetric single-chip heterogeneous multiprocessor computer system having a shared memory with DMA transfers. At least one lock line command is generated from a set comprising a get lock line command with reservation, a put lock line conditional command, and a put lock line unconditional command.
摘要翻译：本发明提供了具有具有DMA传输的共享存储器的非对称单芯片异构多处理器计算机系统中的原子更新原语。从包括具有预留的get lock line命令，put lock line条件命令和put lock line无条件命令的集合中生成至少一个lock line命令。

79. 发明授权

US07689783B2 System and method for sharing memory by heterogeneous processors 有权
标题翻译：异构处理器共享内存的系统和方法
公开(公告)号：US07689783B2
公开(公告)日：2010-03-30
申请号：US11840284
申请日：2007-08-17
申请人： Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle
发明人： Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle
IPC分类号： G06F12/06
CPC分类号： G06F12/0284 , G06F13/1652
摘要： A system for sharing memory by heterogeneous processors, each of which is adapted to process its own instruction set, is presented. A common bus is used to couple the common memory to the various processors. In one embodiment, a cache for more than one of the processors is stored in the shared memory. In another embodiment, some of the processors include a local memory area that is mapped to the shared memory pool. In yet another embodiment, local memory included on one or more of the processors is partially shared so that some of the local memory is mapped to the shared memory area, while remaining memory in the local memory is private to the particular processor.
摘要翻译：提出了一种用于通过异构处理器共享存储器的系统，每个处理器适于处理其自己的指令集。公共总线用于将公共存储器耦合到各种处理器。在一个实施例中，用于多于一个处理器的高速缓存存储在共享存储器中。在另一个实施例中，一些处理器包括映射到共享存储器池的本地存储器区域。在另一个实施例中，包括在一个或多个处理器中的本地存储器被部分地共享，使得一些本地存储器被映射到共享存储器区域，而本地存储器中的剩余存储器对于特定处理器是专用的。

80. 发明授权

US07650491B2 Method and system for controlled distribution of application code and content data within a computer network 有权
标题翻译：计算机网络内应用程序代码和内容数据受控分配的方法和系统
公开(公告)号：US07650491B2
公开(公告)日：2010-01-19
申请号：US12325192
申请日：2008-11-29
申请人： David John Craft , Pradeep K. Dubey , Harm Peter Hofstee , James Allan Kahle
发明人： David John Craft , Pradeep K. Dubey , Harm Peter Hofstee , James Allan Kahle
IPC分类号： H04L9/00 , G06F13/00
CPC分类号： H04L63/0823 , H04L63/126 , H04L63/145 , H04L2463/102
摘要： A secure communication methodology is presented. The client device is configured to download application code and/or content data from a server operated by a service provider. Embedded within the client is a client private key, a client serial number, and a copy of a server public key. The client forms a request, which includes the client serial number, encrypts the request with the server public key, and sends the download request to the server. The server decrypts the request with the server's private key and authenticates the client. The received client serial number is used to search for a client public key that corresponds to the embedded client private key. The server encrypts its response, which includes the requested information, with the client public key of the requesting client, and only the private key in the requesting client can be used to decrypt the information downloaded from the server.
摘要翻译：提出了一种安全的通信方法。客户端设备被配置为从由服务提供商操作的服务器下载应用代码和/或内容数据。嵌入在客户端中的是客户端私钥，客户端序列号和服务器公钥的副本。客户端形成请求，其中包括客户端序列号，使用服务器公钥加密请求，并将下载请求发送到服务器。服务器使用服务器的私钥对请求进行解密，并对客户端进行身份验证。接收到的客户端序列号用于搜索与嵌入式客户端私钥对应的客户端公钥。服务器将其响应（包括所请求的信息）与请求客户端的客户端公钥加密，并且只有请求客户端中的私钥可以用于解密从服务器下载的信息。

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