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71. 发明申请

US20080299717A1 METHOD OF FORMING A SEMICONDUCTOR DEVICE FEATURING A GATE STRESSOR AND SEMICONDUCTOR DEVICE 有权
标题翻译：形成栅极压电器和半导体器件的半导体器件特征的方法
公开(公告)号：US20080299717A1
公开(公告)日：2008-12-04
申请号：US11756231
申请日：2007-05-31
申请人： Brian A. Winstead , Konstantin V. Loiko , Voon-Yew Thean
发明人： Brian A. Winstead , Konstantin V. Loiko , Voon-Yew Thean
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823828 , H01L29/7833 , H01L29/7845
摘要： A semiconductor device (10) is formed in a semiconductor layer (12). A gate stack (16,18) is formed over the semiconductor layer and comprises a first conductive layer (22) and a second layer (24) over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species (46) is implanted into the second layer. Source/drain regions (52) are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack.
摘要翻译：半导体器件（10）形成在半导体层（12）中。在半导体层之上形成栅堆叠（16,18），并且包括第一层上的第一导电层（22）和第二层（24）。第一层比第二层更具导电性并且为植入物提供更多的停止力。物种（46）被植入第二层。源极/漏极区域（52）形成在栅极堆叠的相对侧上的半导体层中。栅极堆叠在注入步骤之后被加热，以使栅极堆叠在栅叠层下方的区域中的半导体层中施加应力。

72. 发明申请

US20080188067A1 PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING FORMING A GATE ELECTRODE LAYER AND FORMING A PATTERNED MASKING LAYER 有权
标题翻译：形成电子装置的方法，包括形成门电极层和形成图案掩蔽层
公开(公告)号：US20080188067A1
公开(公告)日：2008-08-07
申请号：US11671748
申请日：2007-02-06
申请人： Leo Mathew , Voon-Yew Thean , Vishal P. Trivedi
发明人： Leo Mathew , Voon-Yew Thean , Vishal P. Trivedi
IPC分类号： H01L21/3205
CPC分类号： H01L21/28123 , H01L21/2652 , H01L21/32139 , H01L29/4966
摘要： A process of forming an electronic device can include forming a gate electrode layer and forming a patterned masking layer. In a first aspect, a process operation is performed before removing substantially all of a lower portion of the gate electrode layer. In a second aspect, a gate dielectric layer is formed prior to forming the gate electrode layer, and a portion of the gate dielectric layer is exposed after removing the patterned masking layer and prior to forming another masking layer. A portion of the gate electrode layer remains covered during a process where some or all of the portion would be otherwise removed or consumed. By forming the electronic device using such a process, damage to the gate electrode structure while performing subsequent processing can be significantly reduced.
摘要翻译：形成电子器件的工艺可以包括形成栅极电极层并形成图案化掩模层。在第一方面，在去除栅极电极层的基本上所有下部之前进行处理操作。在第二方面，在形成栅极电极层之前形成栅极电介质层，并且在去除图案化掩模层之后并且在形成另一个掩模层之前，一部分栅极电介质层被曝光。在其中将部分或全部部分将被去除或消耗的过程中，栅电极层的一部分保持覆盖。通过使用这种处理形成电子器件，可以显着地减少执行后续处理时对栅电极结构的损坏。

73. 发明申请

US20070277728A1 METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE HAVING A STRAINED SILICON LAYER 有权
标题翻译：用于形成具有应变硅层的半导体结构的方法
公开(公告)号：US20070277728A1
公开(公告)日：2007-12-06
申请号：US11421009
申请日：2006-05-30
申请人： Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Ted R. White
发明人： Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Ted R. White
IPC分类号： C30B21/04 , C30B13/00
CPC分类号： C30B29/52 , C30B25/02 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/0262 , H01L21/76254
摘要： A wafer having a silicon layer that is strained is used to form transistors. The silicon layer is formed by first forming a silicon germanium (SiGe) layer of at least 30 percent germanium that has relaxed strain on a donor wafer. A thin silicon layer is epitaxially grown to have tensile strain on the relaxed SiGe layer. The amount tensile strain is related to the germanium concentration. A high temperature oxide (HTO) layer is formed on the thin silicon layer by reacting dichlorosilane and nitrous oxide at a temperature of preferably between 800 and 850 degrees Celsius. A handle wafer is provided with a supporting substrate and an oxide layer that is then bonded to the HTO layer. The HTO layer, being high density, is able to hold the tensile strain of the thin silicon layer. The relaxed SiGe layer is cleaved then etched away to expose the thin silicon layer. A low temperature silicon layer is then epitaxially grown with tensile strain, correlated to the tensile strain of the thin silicon layer, on the thin silicon layer using trisilane at a temperature preferably not in excess of 500 degrees Celsius. The resulting tensile strain, correlated to the strain of the thin silicon layer, is thus also correlated to the germanium concentration of the relaxed SiGe layer. The thickness of the low temperature silicon layer, using the trisilane at low temperature, is significantly greater than what would normally be expected for a silicon layer of that tensile strain.
摘要翻译：具有应变的硅层的晶片用于形成晶体管。通过首先在施主晶片上形成具有松弛应变的至少30％的锗的锗锗（SiGe）层来形成硅层。外延生长薄硅层以在松弛的SiGe层上具有拉伸应变。拉伸应变量与锗浓度有关。优选在800至850摄氏度之间的温度下，通过使二氯硅烷和一氧化二氮反应，在薄硅层上形成高温氧化物（HTO）层。手柄晶片设置有支撑基板和氧化物层，然后将其结合到HTO层。高密度的HTO层能够保持薄硅层的拉伸应变。松弛的SiGe层被切割，然后蚀刻掉以露出薄的硅层。然后在优选不超过500摄氏度的温度下使用丙硅烷在薄硅层上外延生长与低硅薄层的拉伸应变相关的低温硅层。因此，与薄硅层的应变相关的所得拉伸应变也与弛豫SiGe层的锗浓度相关。在低温下使用丙硅烷的低温硅层的厚度明显大于该拉伸应变的硅层通常预期的厚度。

74. 发明授权

US07282402B2 Method of making a dual strained channel semiconductor device 有权
标题翻译：制造双应变通道半导体器件的方法
公开(公告)号：US07282402B2
公开(公告)日：2007-10-16
申请号：US11093801
申请日：2005-03-30
申请人： Mariam G. Sadaka , Alexander L. Barr , Dejan Jovanovic , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White
发明人： Mariam G. Sadaka , Alexander L. Barr , Dejan Jovanovic , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.
摘要翻译：根据本公开的实施例，制造双应变通道半导体器件的过程包括将应变Si和压缩SiGe与沟槽隔离相集成，以实现同时的NMOS和PMOS性能增强。如本文所述，NMOS和PMOS的集成可以以几种方式实现，以实现与浅沟槽隔离兼容的NMOS和PMOS沟道。

75. 发明授权

US07235502B2 Transitional dielectric layer to improve reliability and performance of high dielectric constant transistors 有权
标题翻译：过渡介电层提高高介电常数晶体管的可靠性和性能
公开(公告)号：US07235502B2
公开(公告)日：2007-06-26
申请号：US11096515
申请日：2005-03-31
申请人： Sriram S. Kalpat , Voon-Yew Thean , Hsing H. Tseng , Olubunmi O. Adetutu
发明人： Sriram S. Kalpat , Voon-Yew Thean , Hsing H. Tseng , Olubunmi O. Adetutu
IPC分类号： H01L21/31
CPC分类号： H01L21/022 , H01L21/02175 , H01L21/0228 , H01L21/28194 , H01L21/3141 , H01L29/513 , H01L29/517
摘要： A gate dielectric structure (201) fabrication process includes forming a transitional dielectric film (205) overlying a silicon oxide film (204). A high dielectric constant film (206) is then formed overlying an upper surface of the transitional dielectric film (205). The composition of the transitional dielectric film (205) at the silicon oxide film (204) interface primarily comprises silicon and oxygen. The high K dielectric (206) and the composition of the transitional dielectric film (205) near the upper surface primarily comprise a metal element and oxygen. Forming the transitional dielectric film (205) may include forming a plurality of transitional dielectric layers (207) where the composition of each successive transitional dielectric layer (207) has a higher concentration of the metal element and a lower concentration of silicon. Forming the transitional dielectric layer (205) may include performing multiple cycles of an atomic layer deposition process (500) where a precursor concentration for each cycle differs from the precursor concentration of the preceding cycle.
摘要翻译：栅极电介质结构（201）制造工艺包括形成覆盖氧化硅膜（204）的过渡电介质膜（205）。然后形成覆盖在过渡介电膜（205）的上表面上的高介电常数膜（206）。氧化硅膜（204）界面处的过渡电介质膜（205）的组成主要包括硅和氧。高K电介质（206）和上表面附近的过渡电介质膜（205）的组成主要包括金属元素和氧。形成过渡电介质膜（205）可以包括形成多个过渡介电层（207），其中每个连续的过渡介电层（207）的组成具有较高的金属元素浓度和较低的硅浓度。形成过渡电介质层（205）可以包括执行原子层沉积工艺（500）的多个循环，其中每个循环的前体浓度与先前循环的前体浓度不同。

76. 发明申请

US20070099353A1 Method for forming a semiconductor structure and structure thereof 有权
标题翻译：半导体结构的形成方法及其结构
公开(公告)号：US20070099353A1
公开(公告)日：2007-05-03
申请号：US11263120
申请日：2005-10-31
申请人： Voon-Yew Thean , Jian Chen , Bich-Yen Nguyen , Mariam Sadaka , Da Zhang
发明人： Voon-Yew Thean , Jian Chen , Bich-Yen Nguyen , Mariam Sadaka , Da Zhang
IPC分类号： H01L21/84
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/7842 , H01L29/785 , Y10S438/938
摘要： Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region having a first conductivity type, forming an insulating layer overlying at least an active area of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material overlying at least a portion of the insulating layer.
摘要翻译：形成半导体结构包括提供具有覆盖在绝缘层上的应变半导体层的衬底，提供用于形成具有第一导电类型的第一多个器件的第一器件区域，提供第二器件区域，用于形成具有第第二导电类型，并且使第二器件区域中的应变半导体层变厚，使得第二器件区域中的应变半导体层具有较小的第一器件区域中的应变半导体层的应变。或者，形成半导体结构包括提供具有第一导电类型的第一区域，形成覆盖第一区域的至少有源区域的绝缘层，各向异性地蚀刻绝缘层，以及在各向异性蚀刻绝缘层之后，覆盖绝缘层的至少一部分的材料。

77. 发明授权

US07160769B2 Channel orientation to enhance transistor performance 有权
标题翻译：通道方向增强晶体管性能
公开(公告)号：US07160769B2
公开(公告)日：2007-01-09
申请号：US10969108
申请日：2004-10-20
申请人： Ted R. White , Alexander L. Barr , Dejan Jovanovic , Bich-Yen Nguyen , Mariam G. Sadaka , Voon-Yew Thean
发明人： Ted R. White , Alexander L. Barr , Dejan Jovanovic , Bich-Yen Nguyen , Mariam G. Sadaka , Voon-Yew Thean
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/78 , H01L21/823807 , H01L27/092 , H01L29/045
摘要： P channel transistors are formed in a semiconductor layer that has a (110) surface orientation for enhancing P channel transistor performance, and the N channel transistors are formed in a semiconductor layer that has a (100) surface orientation. To further provide P channel transistor performance enhancement, the direction of their channel lengths is selected based on their channel direction. The narrow width P channel transistors are preferably oriented in the direction. The wide channel width P channel transistors are preferably oriented in the direction.
摘要翻译： P沟道晶体管形成在具有用于增强P沟道晶体管性能的（110）表面取向的半导体层中，并且N沟道晶体管形成在具有（100）表面取向的半导体层中。为了进一步提供P沟道晶体管性能增强，它们的沟道长度的方向根据其沟道方向来选择。窄宽度P沟道晶体管优选地在<100>方向上取向。宽通道宽度P沟道晶体管优选地在<110>方向上取向。

78. 发明授权

US07091071B2 Semiconductor fabrication process including recessed source/drain regions in an SOI wafer 有权
标题翻译：半导体制造工艺包括在SOI晶片中的凹陷源极/漏极区域
公开(公告)号：US07091071B2
公开(公告)日：2006-08-15
申请号：US11028811
申请日：2005-01-03
申请人： Voon-Yew Thean , Brian J. Goolsby , Bich-Yen Nguyen , Thien T. Nguyen , Tab A. Stephens
发明人： Voon-Yew Thean , Brian J. Goolsby , Bich-Yen Nguyen , Thien T. Nguyen , Tab A. Stephens
IPC分类号： H01L21/00
CPC分类号： H01L29/66636 , H01L29/66772 , H01L29/78639
摘要： A method of forming a transistor with recessed source/drains in an silicon-on-insulator (SOI) wafer includes forming isolation structures in an active layer of the wafer, where the isolation structures preferably extend through the active layer to a BOX layer of the wafer. An upper portion of the active layer is removed to form a transistor channel structure. A gate dielectric is formed on the channel structure and a gate structure is formed on the gate dielectric. Etching through exposed portions of the gate dielectric, channel structure, and BOX layer is performed and source/drain structures are then grown epitaxially from exposed portions of the substrate bulk. The isolation structure and the BOX layer are both comprised primarily of silicon oxide and the thickness of the isolation structure prevents portions of the BOX layer from being etched.
摘要翻译：在绝缘体上硅（SOI）晶片中形成具有凹陷源/漏极的晶体管的方法包括在晶片的有源层中形成隔离结构，其中隔离结构优选地延伸穿过有源层到BOX层的BOX层晶圆。去除有源层的上部以形成晶体管沟道结构。在沟道结构上形成栅极电介质，在栅极电介质上形成栅极结构。执行蚀刻通过栅介质，沟道结构和BOX层的暴露部分，然后从衬底体的暴露部分外延生长源极/漏极结构。隔离结构和BOX层主要由氧化硅组成，并且隔离结构的厚度防止BOX层的部分被蚀刻。

79. 发明申请

US20060170016A1 Asymmetric spacers and asymmetric source/drain extension layers 有权
标题翻译：非对称隔离层和不对称源极/漏极延伸层
公开(公告)号：US20060170016A1
公开(公告)日：2006-08-03
申请号：US11047946
申请日：2005-02-01
申请人： Leo Mathew , Yang Du , Bich-Yen Nguyen , Voon-Yew Thean
发明人： Leo Mathew , Yang Du , Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4983 , H01L29/165 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/66659 , H01L29/7843
摘要： A method of forming a semiconductor device is provided in which a substrate (102) is provided which has a gate dielectric layer (106) disposed thereon, and a gate electrode (116) having first and second sidewalls is formed over the gate dielectric layer. First (146) and second (150) extension spacer structures are formed adjacent the first and second sidewalls, respectively. In the resulting device: (a) the first and second extension spacer structures have different dimensions; (b) the first and second extension spacer structures comprise first and second distinct materials; (c) the device has asymmetric source/drain extensions (162); and/or (d) the device has an oxide layer (160) disposed between the first extension spacer structure and the gate electrode, and either (i) the device has no dielectric layer disposed between the second extension spacer structure and the gate electrode, or (ii) the device has a second dielectric layer disposed between the second extension spacer structure and the gate electrode, and the first dielectric layer is substantially thicker than the second dielectric layer.
摘要翻译：提供一种形成半导体器件的方法，其中设置有其上设置有栅介质层（106）的衬底（102），并且在栅极介电层上形成具有第一和第二侧壁的栅电极（116）。分别在第一和第二侧壁附近形成第一（146）和第二（150）延伸间隔结构。在所得装置中：（a）第一和第二延伸间隔结构具有不同的尺寸; （b）第一和第二延伸间隔结构包括第一和第二不同材料; （c）该器件具有不对称的源极/漏极延伸部分（162）; 和/或（d）所述器件具有设置在所述第一延伸间隔物结构和所述栅电极之间的氧化物层（160），以及（i）所述器件在所述第二延伸间隔物结构和所述栅电极之间没有设置介电层，或者（ii）该器件具有设置在第二延伸间隔物结构和栅极之间的第二介电层，并且第一介电层基本上比第二介电层更厚。

80. 发明申请

US20060148196A1 SEMICONDUCTOR FABRICATION PROCESS INCLUDING RECESSED SOURCE/DRAIN REGIONS IN AN SOI WAFER 有权
标题翻译：半导体制造工艺，包括SOI WAFER中的残留源/漏区
公开(公告)号：US20060148196A1
公开(公告)日：2006-07-06
申请号：US11028811
申请日：2005-01-03
申请人： Voon-Yew Thean , Brian Goolsby , Bich-Yen Nguyen , Thien Nguyen , Tab Stephens
发明人： Voon-Yew Thean , Brian Goolsby , Bich-Yen Nguyen , Thien Nguyen , Tab Stephens
IPC分类号： H01L21/76
CPC分类号： H01L29/66636 , H01L29/66772 , H01L29/78639
摘要： A method of forming a transistor with recessed source/drains in an silicon-on-insulator (SOI) wafer includes forming isolation structures in an active layer of the wafer, where the isolation structures preferably extend through the active layer to a BOX layer of the wafer. An upper portion of the active layer is removed to form a transistor channel structure. A gate dielectric is formed on the channel structure and a gate structure is formed on the gate dielectric. Etching through exposed portions of the gate dielectric, channel structure, and BOX layer is performed and source/drain structures are then grown epitaxially from exposed portions of the substrate bulk. The isolation structure and the BOX layer are both comprised primarily of silicon oxide and the thickness of the isolation structure prevents portions of the BOX layer from being etched.
摘要翻译：在绝缘体上硅（SOI）晶片中形成具有凹陷源/漏极的晶体管的方法包括在晶片的有源层中形成隔离结构，其中隔离结构优选地延伸穿过有源层到BOX层的BOX层晶圆。去除有源层的上部以形成晶体管沟道结构。在沟道结构上形成栅极电介质，在栅极电介质上形成栅极结构。执行蚀刻通过栅介质，沟道结构和BOX层的暴露部分，然后从衬底体的暴露部分外延生长源极/漏极结构。隔离结构和BOX层主要由氧化硅组成，并且隔离结构的厚度防止BOX层的部分被蚀刻。

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