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71. 发明申请

US20090197382A1 MULTI-GATED, HIGH-MOBILITY, DENSITY IMPROVED DEVICES 失效
标题翻译：多层，高移动，密度改进的设备
公开(公告)号：US20090197382A1
公开(公告)日：2009-08-06
申请号：US12023347
申请日：2008-01-31
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/26546 , H01L21/26586 , H01L21/845 , H01L29/66803 , H01L29/785
摘要： Disclosed herein are embodiments of an improved method of forming p-type and n-type MUGFETs with high mobility crystalline planes in high-density, chevron-patterned, CMOS devices. Specifically, semiconductor fins are formed in a chevron layout oriented along the centerline of a wafer. Gates are formed adjacent to the semiconductor fins such that they are approximately perpendicular to the centerline. Then, masked implant sequences are performed, during which halo and/or source/drain dopants are implanted into the sidewalls of the semiconductor fins on one side of the chevron layout and then into the sidewalls of the semiconductor fins on the opposite side of the chevron layout. The implant direction used during these implant sequences is substantially orthogonal to the gates in order to avoid mask shadowing, which can obstruct dopant implantation when separation between the semiconductor fins in the chevron layout is scaled (i.e., when device density is increased).
摘要翻译：本文公开了在高密度，人字纹图案化的CMOS器件中形成具有高迁移率晶面的p型和n型MUGFET的改进方法的实施方案。具体地，半导体散热片形成为沿着晶片的中心线定向的人字形布局。门形成在半导体翅片附近，使得它们大致垂直于中心线。然后，进行掩蔽的植入序列，在此期间将卤素和/或源极/漏极掺杂剂注入到人字形布局的一侧上的半导体鳍片的侧壁中，然后进入人字纹相反侧的半导体鳍片的侧壁布局。在这些植入序列期间使用的植入方向基本上与栅极正交，以避免掩模阴影，当阴影布局中的半导体鳍片之间的间隔被缩放时（即，当器件密度增加时），这可能阻碍掺杂剂注入。

72. 发明授权

US07569897B2 Low-capacitance contact for long gate-length devices with small contacted pitch 有权
标题翻译：具有小接触间距的长栅极长度器件的低电容接触
公开(公告)号：US07569897B2
公开(公告)日：2009-08-04
申请号：US11767635
申请日：2007-06-25
申请人： Brent A. Anderson , Edward J. Nowak
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/823431 , H01L21/823456 , H01L27/088 , H01L27/0886 , H01L27/1211 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sections for a planar transistor) connected at opposite ends to source/drain bridges. A gate electrode is patterned on the segmented active devices between the source/drain bridges such that it has a reduced length between the segments (i.e., between the semiconductor fins or sections). Source/drain contacts land on the source/drain bridges such that they are opposite only those portions of the gate electrode with the reduced gate length. These FET structures can be configured to simultaneously maximize the density of the transistor, minimize leakage power and maintain the parasitic capacitance between the source/drain contacts and the gate conductor below a preset level, depending upon the performance and density requirements.
摘要翻译：公开了平面和非平面场效应晶体管（FET）结构和形成结构的方法。这些结构包括在源极/漏极桥两端连接的分段有源器件（例如，用于非平面晶体管的多个半导体鳍片或用于平面晶体管的多个半导体层部分）。在源极/漏极桥之间的分段有源器件上图案化栅电极，使得栅极电极在段之间（即，半导体鳍片或部分之间）具有减小的长度。源极/漏极接触器接地在源/漏极桥上，使得它们仅与具有减小的栅极长度的栅电极的那些部分相对。这些FET结构可以被配置为同时使晶体管的密度最大化，从而使漏极功率最小化，并且将源极/漏极触点和栅极导体之间的寄生电容保持在预定值以下，这取决于性能和密度要求。

73. 发明申请

US20090167420A1 DESIGN STRUCTURE FOR REGULATING THRESHOLD VOLTAGE IN TRANSISTOR DEVICES 审中-公开
标题翻译：用于调节晶体管器件中阈值电压的设计结构
公开(公告)号：US20090167420A1
公开(公告)日：2009-07-02
申请号：US11965787
申请日：2007-12-28
申请人： Edward J. Nowak
发明人： Edward J. Nowak
IPC分类号： G05F3/16
CPC分类号： G05F3/205
摘要： A circuit and a design structure including the circuit embodied in a machine readable medium are disclosed. The circuit is for regulating a desired value of threshold voltage, Vt, for a given FET transistor device. The circuit is coupled to the FET for regulating the desired value of Vt, by providing a device body voltage, and, that additionally enables control of the voltage at the drain of the FET device independent of the applied body bias voltage. The coupled circuit includes an operational amplifier, or, a second MOS transistor, or, a Zener diode.
摘要翻译：公开了包括机器可读介质中实现的电路的电路和设计结构。电路用于调节给定FET晶体管器件的阈值电压Vt的期望值。该电路通过提供器件体电压而耦合到FET以调节所需的Vt值，并且另外能够独立于所施加的体偏置电压来控制FET器件的漏极处的电压。耦合电路包括运算放大器，或第二MOS晶体管或齐纳二极管。

74. 发明申请

US20090108320A1 TUNABLE CAPACITOR 有权
标题翻译： TUNABLE电容器
公开(公告)号：US20090108320A1
公开(公告)日：2009-04-30
申请号：US11923864
申请日：2007-10-25
申请人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
发明人： Corey K. Barrows , Joseph A. Iadanza , Edward J. Nowak , Douglas W. Stout , Mark S. Styduhar
IPC分类号： H01L29/94
CPC分类号： H01L29/94
摘要： Disclosed are embodiments of a design structure transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.
摘要翻译：公开了作为电容器操作的设计结构晶体管的实施例以及在这种电容器内调谐电容的相关方法。电容器的实施例包括分别在半导体层上方和下方具有前栅极和后栅极的场效应晶体管。通过改变晶体管的源极/漏极区域中的电压条件，例如使用源极/漏极区域和电压源之间的开关或电阻器，可以通过改变晶体管的源极/ 或者，可以通过改变在晶体管内侧面有多个源极/漏极区域的多个沟道区域中的一个或多个中的电压条件来选择性地在多个不同值之间变化由电容器呈现的电容值。根据每个通道区域中的电导率，电容器将呈现不同的电容值。

75. 发明申请

US20090101978A1 FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE 有权
标题翻译：具有合并源/排水硅酸盐的FIN型场效应晶体管结构及形成结构的方法
公开(公告)号：US20090101978A1
公开(公告)日：2009-04-23
申请号：US11873521
申请日：2007-10-17
申请人： Brent A. Anderson , Andres Bryant , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66795
摘要： Disclosed herein are embodiments of a design structure of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.
摘要翻译：这里公开了多鳍片式场效应晶体管（即，多鳍式双栅极或三栅极场效应晶体管）的设计结构的实施例，其中多个散热片部分或完全由高导电材料（例如，金属硅化物）。以这种方式合并散热片使串联电阻最小化，栅极和源极/漏极区之间的寄生电容几乎不增加。以这种方式合并半导体散热片也允许每个源极/漏极区域通过单个触点通孔接触，以及该触点通孔的更灵活的放置。

76. 发明授权

US07517806B2 Integrated circuit having pairs of parallel complementary FinFETs 失效
标题翻译：具有成对的并联互补FinFET的集成电路
公开(公告)号：US07517806B2
公开(公告)日：2009-04-14
申请号：US11186748
申请日：2005-07-21
申请人： Andres Bryant , William F. Clark, Jr. , David M. Fried , Mark D. Jaffe , Edward J. Nowak , John J. Pekarik , Christopher S. Putnam
发明人： Andres Bryant , William F. Clark, Jr. , David M. Fried , Mark D. Jaffe , Edward J. Nowak , John J. Pekarik , Christopher S. Putnam
IPC分类号： H01L21/302
CPC分类号： H01L21/84 , H01L21/3086 , H01L21/3088 , H01L21/823821 , H01L27/1203 , H01L29/66795 , H01L29/785 , Y10S438/947
摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.
摘要翻译：公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。第一鳍片和第二鳍片具有大致相同的宽度。

77. 发明申请

US20090065834A1 IMAGERS HAVING ELECTRICALLY ACTIVE OPTICAL ELEMENTS 有权
标题翻译：具有电动活性光学元件的图像
公开(公告)号：US20090065834A1
公开(公告)日：2009-03-12
申请号：US11850798
申请日：2007-09-06
申请人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L27/146
CPC分类号： H01L27/14636 , H01L27/14625
摘要： A CMOS image sensor comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting charge carriers in response to incident light; and, one or more light transmissive conductive wire structures formed above the photosensing device, the one or more conductive wire structures being located in an optical path above the photosensing device. The formed light transmissive conductive wire structures provide both an electrical and optical functions. An optical function is provided by tailoring the thickness of the conductive wire layer to filter light according to a pixel color scheme. Alternately, the light transmissive conductive wire structures may be formed as a microlens structure providing a light focusing function. Electrical functions for the conductive wire layer include use as a capacitor plate, as a resistor or as an interconnect.
摘要翻译：一种包括有源像素单元阵列的CMOS图像传感器。每个有源像素单元包括衬底; 形成在基板表面处或下方的光敏装置，用于响应于入射光收集电荷载体; 以及形成在光敏器件上方的一个或多个透光导线结构，所述一个或多个导电线结构位于光敏器件上方的光路中。形成的透光导线结构提供电和光学功能。通过根据像素配色方案调整导线层的厚度以过滤光，提供光学功能。或者，透光导线结构可以形成为提供光聚焦功能的微透镜结构。用于导线层的电气功能包括用作电容器板，电阻器或互连件。

78. 发明授权

US07498208B2 Chevron CMOS trigate structure 有权
标题翻译：雪佛龙CMOS触发结构
公开(公告)号：US07498208B2
公开(公告)日：2009-03-03
申请号：US11689549
申请日：2007-03-22
申请人： Brent A. Anderson , Edward J. Nowak
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/823821 , H01L21/823842 , H01L21/823857 , H01L21/845 , H01L27/1211 , H01L29/045 , H01L29/42384 , H01L29/785
摘要： Disclosed herein is a structure with two different type tri-gate MOSFETs formed on the same substrate. Each MOSFET comprises a fin with optimal mobility for the particular type of MOSFET. Due to the processes used to form fins with different crystalline orientations on the same substrate, one of the MOSFETs has a fin with a lower mobility top surface. To inhibit inversion of the top surface, this MOSFET has a gate dielectric layer with a thicker region on the top surface than it does on the opposing sidewall surfaces. Additionally, several techniques for forming the thicker region of the gate dielectric layer are also disclosed.
摘要翻译：这里公开了在同一衬底上形成有两个不同类型的三栅极MOSFET的结构。每个MOSFET包括对于特定类型的MOSFET具有最佳移动性的鳍。由于用于在相同衬底上形成具有不同结晶取向的鳍片的工艺，所以MOSFET中的一个具有具有较低迁移率顶表面的翅片。为了抑制顶表面的反转，该MOSFET具有栅极电介质层，在顶表面上具有比在相对侧壁表面上更厚的区域。此外，还公开了用于形成栅极电介质层的较厚区域的几种技术。

79. 发明申请

US20090020806A1 ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD 有权
标题翻译：不对称场效应晶体管结构与方法
公开(公告)号：US20090020806A1
公开(公告)日：2009-01-22
申请号：US11778185
申请日：2007-07-16
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
IPC分类号： H01L29/78 , H01L21/336 , H01L29/76
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7834 , H01L29/7835
摘要： Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).
摘要翻译：公开了非对称场效应晶体管结构的实施例和形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（即提供改进的驱动电流，电路延迟最小）。具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定电容值）。

80. 发明申请

US20080315264A1 STRAIN-COMPENSATED FIELD EFFECT TRANSISTOR AND ASSOCIATED METHOD OF FORMING THE TRANSISTOR 有权
标题翻译：应变补偿场效应晶体管和相关的形成晶体管的方法
公开(公告)号：US20080315264A1
公开(公告)日：2008-12-25
申请号：US11764948
申请日：2007-06-19
申请人： Alberto Escobar , Brian J. Greene , Edward J. Nowak
发明人： Alberto Escobar , Brian J. Greene , Edward J. Nowak
IPC分类号： H01L29/00 , H01L21/336
CPC分类号： H01L29/78 , H01L21/823807 , H01L29/66575 , H01L29/7849
摘要： Disclosed are embodiments of a field effect transistor (FET) having decreased drive current temperature sensitivity. Specifically, any temperature-dependent carrier mobility change in the FET channel region is simultaneously counteracted by an opposite strain-dependent carrier mobility change to ensure that drive current remains approximately constant or at least within a predetermined range in response to temperature variations. This opposite strain-dependent carrier mobility change is provided by a straining structure that is configured to impart a temperature-dependent amount of a pre-selected strain type on the channel region. Also disclosed are embodiments of an associated method of forming the field effect transistor.
摘要翻译：公开了具有降低的驱动电流温度灵敏度的场效应晶体管（FET）的实施例。具体地说，通过与应变相关的载流子迁移率变化相反的FET通道区域中任何温度依赖的载流子迁移率变化被同时抵消，以确保驱动电流响应于温度变化保持近似恒定或至少在预定范围内。这种相反的应变依赖性载流子迁移率变化由应变结构提供，该应变结构被配置为在通道区域上赋予预选的应变类型的温度相关量。还公开了形成场效应晶体管的相关方法的实施例。

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