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71. 发明申请

US20130020578A1 Semiconductor Device and Method for Manufacturing the Same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20130020578A1
公开(公告)日：2013-01-24
申请号：US13521998
申请日：2011-11-30
申请人： Qingqing Liang , Huilong Zhu , Huicai Zhong
发明人： Qingqing Liang , Huilong Zhu , Huicai Zhong
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/7856
摘要： The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: an active fin region which is arranged on an insulating layer; a threshold voltage adjusting layer arranged on top of the active fin region, which threshold voltage adjusting layer is used to adjust the threshold voltage of the semiconductor device; a gate stack which is arranged on the threshold voltage adjusting layer, on the sidewalls of the active fin region and on the insulating layer, and comprises a gate dielectric and a gate electrode formed on the gate dielectric; and a source region and a drain region formed in the active fin region on both sides of the gate stack respectively. The semiconductor device according to the invention comprises the threshold voltage adjusting layer which may adjust the threshold voltage of the semiconductor device. This provides a simple and convenient way capable of adjusting the threshold voltage of a semiconductor device comprising an active fin region.
摘要翻译：本发明涉及半导体器件及其制造方法。根据本发明的实施例的半导体器件可以包括：布置在绝缘层上的有源鳍片区域; 设置在有源鳍片区域顶部的阈值电压调整层，该阈值电压调整层用于调整半导体器件的阈值电压; 栅极堆叠，其布置在阈值电压调节层上，在有源鳍片区域的侧壁和绝缘层上，并且包括形成在栅极电介质上的栅极电介质和栅电极; 以及分别形成在栅极堆叠两侧的有源鳍片区域中的源极区域和漏极区域。根据本发明的半导体器件包括可调节半导体器件的阈值电压的阈值电压调节层。这提供了能够调整包括有源鳍片区域的半导体器件的阈值电压的简单且方便的方式。

72. 发明申请

US20120319185A1 NAND STRUCTURE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译： NAND结构及其制造方法
公开(公告)号：US20120319185A1
公开(公告)日：2012-12-20
申请号：US13063653
申请日：2010-06-25
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： The present invention provides a NAND gate structure, comprising: a substrate; a gate insulation layer formed on the substrate; a source/drain region formed in the substrate; a middle gate formed on the gate insulator layer, a first gate and a second gate on each side of the middle gate, first sidewall spacers between the first gate and the middle gate and between the second gate and the middle gate, and second sidewall spacers outside the first gate and the second gate, wherein, a first contact hole region is provided on the middle gate, second contact hole regions are provided respectively on the first gate and the second gate, and the first contact hole region and the second contact hole regions are in staggered arrangement. The present invention proposes a new NAND structure and a method of manufacturing the same. With the NAND structure, about 30-50% area of the chip may be effectively reduced.
摘要翻译：本发明提供了一种NAND门结构，包括：衬底; 形成在所述基板上的栅极绝缘层; 形成在所述基板中的源极/漏极区域; 形成在栅极绝缘体层上的中间栅极，在中间栅极的每一侧上的第一栅极和第二栅极，第一栅极和中间栅极之间以及第二栅极和中间栅极之间的第一侧壁间隔物，以及第二侧壁间隔物在第一栅极和第二栅极之外，其中，第一接触孔区域设置在中间栅极上，第二接触孔区域分别设置在第一栅极和第二栅极上，第一接触孔区域和第二接触孔地区交错排列。本发明提出了一种新的NAND结构及其制造方法。利用NAND结构，芯片面积的30-50％可以有效降低。

73. 发明申请

US20120286373A1 GATE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：门结构及其制造方法
公开(公告)号：US20120286373A1
公开(公告)日：2012-11-15
申请号：US13376501
申请日：2011-04-26
申请人： Huicai Zhong , Zhijiong Luo , Qingqing Liang
发明人： Huicai Zhong , Zhijiong Luo , Qingqing Liang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , H01L29/6653
摘要： Gates structures and methods for manufacturing the same are disclosed. In an example, the gate structure comprises a gate stack formed on a semiconductor substrate, the gate stack comprising a high-K dielectric layer and a metal gate electrode from bottom to top; a first dielectric layer on sidewalls of the gate stack, the first dielectric layer serving as first sidewall spacers; and a sacrificial metal layer on the first dielectric layer, the sacrificial metal layer serving as second sidewall spacers. The sacrificial metal layer in the gate structure reduces a thickness of an interfacial oxide layer in the step of annealing. The gate structure may be applied to a semiconductor device having a small size because the gate dielectric layer has a low EOT value.
摘要翻译：公开了用于制造其门的结构和方法。在一个示例中，栅极结构包括形成在半导体衬底上的栅极堆叠，栅堆叠包括从底部到顶部的高K电介质层和金属栅电极; 位于所述栅极叠层的侧壁上的第一介电层，所述第一介电层用作第一侧壁间隔物; 以及在所述第一电介质层上的牺牲金属层，所述牺牲金属层用作第二侧壁间隔物。栅极结构中的牺牲金属层在退火步骤中减小界面氧化物层的厚度。栅极结构可以应用于具有小尺寸的半导体器件，因为栅极介电层具有低的EOT值。

74. 发明申请

US20120286337A1 FIN FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： FIN场效应晶体管及其制造方法
公开(公告)号：US20120286337A1
公开(公告)日：2012-11-15
申请号：US13377141
申请日：2011-08-10
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L27/1211 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L29/66545
摘要： Embodiments of the present invention disclose a method for manufacturing a Fin Field-Effect Transistor. When a fin is formed, a dummy gate across the fin is formed on the fin, a spacer is formed on sidewalls of the dummy gate, and a cover layer is formed on the first dielectric layer and on the fin outside the dummy gate and the spacer, then, an self-aligned and elevated source/drain region is formed at both sides of the dummy gate by the spacer, wherein the upper surfaces of the gate and the source/drain region are in the same plane. The upper surfaces of the gate and the source/drain region are in the same plane, making alignment of the contact plug easier; and the gate and the source/drain region are separated by the spacer, thereby improving alignment accuracy, solving inaccurate alignment of the contact plug, and improving device AC performance.
摘要翻译：本发明的实施例公开了一种制造Fin场效应晶体管的方法。当形成翅片时，在翅片上形成跨鳍片的虚拟栅极，在虚拟栅极的侧壁上形成间隔物，并且在第一介电层上形成覆盖层，并在模拟栅极外部形成覆盖层，然后，通过间隔物在伪栅极的两侧形成自对准和升高的源/漏区，其中栅极和源极/漏极区的上表面在同一平面内。栅极和源极/漏极区域的上表面位于相同的平面中，使接触插塞的对准更容易; 并且栅极和源极/漏极区域被间隔物分开，从而提高对准精度，解决接触插塞的不准确的对准以及提高器件AC性能。

75. 发明授权

US08278721B2 Contact hole, semiconductor device and method for forming the same 有权
标题翻译：接触孔，半导体器件及其形成方法
公开(公告)号：US08278721B2
公开(公告)日：2012-10-02
申请号：US13119513
申请日：2011-02-24
申请人： Huicai Zhong , Qingqing Liang
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L21/02
CPC分类号： H01L21/76897 , H01L21/76831 , H01L29/41783 , H01L29/6653 , H01L29/6656
摘要： The invention provides a method for forming a contact plug, comprising: forming a gate, a sidewall spacer, a sacrificial sidewall spacer, a source region and a drain region on a substrate, wherein the sidewall spacer is formed around the gate, the sacrificial sidewall spacer is formed over the sidewall spacer, and the source region and the drain region are formed within the substrate and on respective sides of the gate; forming an interlayer dielectric layer, with the gate, the sidewall spacer and the sacrificial sidewall spacer being exposed; removing the sacrificial sidewall spacer to form a contact space, the sacrificial sidewall spacer material being different from that of the gate, the sidewall spacer and the interlayer dielectric layer; forming a conducting layer to fill the contact space; and cutting off the conducting layer, to form at least two conductors connected to the source region and the drain region respectively.
摘要翻译：本发明提供一种用于形成接触塞的方法，包括：在基底上形成栅极，侧壁间隔物，牺牲侧壁间隔物，源极区和漏极区，其中侧壁间隔物围绕栅极形成，牺牲侧壁间隔物形成在侧壁间隔物上，并且源极区和漏极区形成在衬底内和栅极的相应侧上; 形成层间电介质层，其中所述栅极，所述侧壁间隔物和所述牺牲侧壁间隔物被暴露; 去除所述牺牲侧壁间隔物以形成接触空间，所述牺牲侧壁间隔物材料与所述牺牲侧壁间隔物材料不同于所述牺牲侧壁间隔物，形成导电层以填充接触空间; 并切断导电层，形成分别连接到源区和漏区的至少两个导体。

76. 发明申请

US20120187496A1 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20120187496A1
公开(公告)日：2012-07-26
申请号：US13266555
申请日：2011-04-19
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Huilong Zhu
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L27/088 , H01L21/302
CPC分类号： H01L29/66636 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/517 , H01L29/66545 , H01L29/78 , H01L29/7848
摘要： A method for forming a semiconductor device comprises: forming at least one gate stack structure and an interlayer material layer between the gate stack structures on a semiconductor substrate; defining isolation regions and removing a portion of the interlayer material layer and a portion of the semiconductor substrate which has a certain height in the regions, so as to form trenches; removing portions of the semiconductor substrate which carry the gate stack structures, in the regions; and filling the trenches with an insulating material. A semiconductor device is also provided. The area of the isolation regions may be reduced.
摘要翻译：一种用于形成半导体器件的方法包括：在半导体衬底上的栅堆叠结构之间形成至少一个栅叠层结构和层间材料层; 限定隔离区域并去除在该区域中具有一定高度的层间材料层和半导体衬底的一部分，以形成沟槽; 在所述区域中移除携带所述栅堆叠结构的所述半导体衬底的部分; 并用绝缘材料填充沟槽。还提供了半导体器件。可以减小隔离区域的面积。

77. 发明申请

US20120043624A1 ULTRA-THIN BODY TRANSISTOR AND METHOD FOR MANUFCTURING THE SAME 审中-公开
标题翻译：超薄体晶体管及其制造方法
公开(公告)号：US20120043624A1
公开(公告)日：2012-02-23
申请号：US13132535
申请日：2011-01-27
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/78654 , H01L21/28123 , H01L29/165 , H01L29/66545 , H01L29/66636 , H01L29/66772 , H01L29/7834
摘要： An ultra-thin body transistor and a method for manufacturing an ultra-thin body transistor are disclosed. The ultra-thin body transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source region and a drain region in the semiconductor substrate and on either side of the gate structure; in which the gate structure comprises a gate dielectric layer, a gate embedded in the gate dielectric layer, and a spacer on both sides of the gate; the ultra-thin body transistor further comprises: a body region and a buried insulated region located sequentially under the gate structure and in a well region; two ends of the body region and the buried insulated region are connected with the source region and the drain region respectively; and the body region is isolated from other regions in the well region by the buried insulated region under the body region. The ultra-thin body transistor has a thinner body region, which decreases the short channel effect. In the method for manufacturing an ultra-thin body transistor together with the replacement-gate process, the forming of the buried insulated region is self-aligned with the gate, which reduces the parasitic resistance under the spacer.
摘要翻译：公开了一种超薄体晶体管和制造超薄体晶体管的方法。超薄体晶体管包括：半导体衬底; 半导体衬底上的栅极结构; 以及半导体衬底中的栅极结构的任一侧上的源极区和漏极区; 其中栅极结构包括栅极电介质层，嵌入栅极电介质层中的栅极和栅极两侧的间隔物; 所述超薄体晶体管还包括：主体区域和位于所述栅极结构之下且位于阱区域中的掩埋绝缘区域; 主体区域和埋入绝缘区域的两端分别与源极区域和漏极区域连接; 并且身体区域通过身体区域下的埋入绝缘区域与阱区域中的其它区域隔离。超薄体晶体管具有较薄的体区，从而降低了短沟道效应。在与替换栅极工艺一起制造超薄体晶体管的方法中，掩埋绝缘区域的形成与栅极自对准，这降低了间隔物下的寄生电阻。

78. 发明申请

US20110233722A1 CAPACITOR STRUCTURE AND METHOD OF MANUFACTURE 有权
标题翻译：电容器结构及其制造方法
公开(公告)号：US20110233722A1
公开(公告)日：2011-09-29
申请号：US12993048
申请日：2010-09-21
申请人： Qingqing Liang , Huicai Zhong
发明人： Qingqing Liang , Huicai Zhong
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L28/90 , H01G4/232 , H01G4/30 , H01G4/33 , H01L28/86
摘要： The presented application discloses a capacitor structure and a method for manufacturing the same. The capacitor structure comprises a plurality of sub-capacitors formed on a substrate, each of which comprises a top capacitor plate, a bottom capacitor plate and a dielectric layer sandwiched therebetween; and a first capacitor electrode and a second capacitor electrode connecting the plurality of sub-capacitors in parallel, wherein the plurality of sub-capacitors includes a plurality of first sub-capacitors and a plurality of second sub-capacitors stacked in an alternate manner, each of the first sub-capacitors has a bottom capacitor plate overlapping with a top capacitor plate of an underlying second sub-capacitor, with the overlapping plate being a first electrode layer; and each of the second sub-capacitors has a bottom capacitor plate overlapping with a top capacitor plate of an underlying first sub-capacitor, with the overlapping plate being a second electrode layer, the capacitor structure is characterized in that the first electrode layer and the second electrode layers are made of different conductive materials. The capacitor structure has a small footprint on the chip and a large capacitance value, and can be used as an integrated capacitor in an analogous circuit, an RF circuit, an embedded memory, and the like.
摘要翻译：本申请公开了一种电容器结构及其制造方法。电容器结构包括形成在基板上的多个子电容器，每个子电容器包括顶部电容器板，底部电容器板和夹在其间的电介质层; 以及并联连接多个副电容器的第一电容电极和第二电容电极，其中，所述多个副电容器包括多个第一子电容器和以交替方式堆叠的多个第二子电容器，的第一子电容器具有与下面的第二子电容器的顶部电容器板重叠的底部电容器板，其中重叠板是第一电极层，并且每个第二子电容器具有与电容器结构的特征在于，第一电极层和第二电极层由不同的导电材料制成。电容器结构在芯片上具有小的占地面积和大的电容值，并且可以用作模拟电路，RF电路，嵌入式存储器等中的集成电容器。

79. 发明申请

US20090073758A1 SRAM CELLS WITH ASYMMETRIC FLOATING-BODY PASS-GATE TRANSISTORS 审中-公开
标题翻译：具有不对称浮动体态栅极晶体管的SRAM电池
公开(公告)号：US20090073758A1
公开(公告)日：2009-03-19
申请号：US11857757
申请日：2007-09-19
申请人： Gregory G. Freeman , Qingqing Liang , Mario M. Pelella , Carl J. Radens , Huicai Zhong , Huilong Zhu
发明人： Gregory G. Freeman , Qingqing Liang , Mario M. Pelella , Carl J. Radens , Huicai Zhong , Huilong Zhu
IPC分类号： G11C11/34 , H01L21/00
CPC分类号： G11C11/412
摘要： The embodiments of the invention provide SRAM cells with asymmetric floating-body pass-gate transistors. More specifically, a semiconductor device includes an SRAM cell, a first pass-gate transistor, and a second pass-gate transistor. The first pass-gate transistor is connected to a first side of the SRAM cell, wherein the first pass-gate transistor comprises a first drain region and a first source region. The second pass-gate transistor is connected to a second side of the SRAM cell, wherein the second side is opposite the first side. The second pass-gate transistor comprises a second source region and a second drain region. Furthermore, the first source region and/or the second source region comprise a xenon implant. The first drain region and the second drain region each lack a xenon implant.
摘要翻译：本发明的实施例提供具有非对称浮体通过栅极晶体管的SRAM单元。更具体地，半导体器件包括SRAM单元，第一通过栅极晶体管和第二通过栅极晶体管。第一栅极晶体管连接到SRAM单元的第一侧，其中第一栅极晶体管包括第一漏极区域和第一源极区域。第二通栅晶体管连接到SRAM单元的第二侧，其中第二侧与第一侧相对。第二通栅晶体管包括第二源区和第二漏区。此外，第一源区和/或第二源区包括氙植入物。第一漏区和第二漏区各自缺少氙植入物。

80. 发明授权

US07485521B2 Self-aligned dual stressed layers for NFET and PFET 有权
标题翻译：用于NFET和PFET的自对准双应力层
公开(公告)号：US07485521B2
公开(公告)日：2009-02-03
申请号：US11160676
申请日：2005-07-05
申请人： Huilong Zhu , Brian L. Tessier , Huicai Zhong
发明人： Huilong Zhu , Brian L. Tessier , Huicai Zhong
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823828 , H01L29/7843 , Y10S438/938
摘要： Methods are disclosed for forming self-aligned dual stressed layers for enhancing the performance of NFETs and PFETs. In one embodiment, a sacrificial layer is used to remove a previously deposited stressed layer. A mask position used to pattern the sacrificial layer is adjusted such that removal of the latter deposited stressed layer, using the sacrificial layer, leaves the dual stress layers in an aligned form. The methods result in dual stressed layers that do not overlap or underlap, thus avoiding processing problems created by those issues. A semiconductor device including the aligned dual stressed layers is also disclosed.
摘要翻译：公开了用于形成用于增强NFET和PFET的性能的自对准双应力层的方法。在一个实施例中，牺牲层用于去除先前沉积的应力层。调整用于图案化牺牲层的掩模位置，使得使用牺牲层去除后者沉积的应力层以对准的形式离开双应力层。这种方法导致双重应力层不重叠或不重叠，从而避免了由这些问题产生的处理问题。还公开了包括对准的双重应力层的半导体器件。

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