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    • 71. 发明申请
    • Thin film transistor array panel
    • 薄膜晶体管阵列面板
    • US20060033871A1
    • 2006-02-16
    • US11254134
    • 2005-10-18
    • Hyun-Wuk KimJae-Jin LyuYoon-Sung UmChang-Hun Lee
    • Hyun-Wuk KimJae-Jin LyuYoon-Sung UmChang-Hun Lee
    • G02F1/1343
    • G02F1/134309G02F1/136286G02F2001/134345
    • A thin film transistor array panel according to one embodiment of the invention comprises: first, second, and third pixel electrodes arranged sequentially, the second pixel electrode including first and second sub-pixel electrodes, the second pixel electrode occupying an area comprising a first area and a second area that is disposed closer to the third pixel electrode than the first area; first, second, and third thin film transistors connected to the first, the second, and the third pixel electrodes, respectively; first, second, and third gate lines connected to the first, the second, and the third thin film transistors, respectively; and a data line connected to the first, the second, and the third thin film transistors, wherein the second sub-pixel electrode is capacitively coupled to the third pixel electrode, and the second sub-pixel electrode is present in both the first and the second areas.
    • 根据本发明的一个实施例的薄膜晶体管阵列面板包括:顺序布置的第一,第二和第三像素电极,第二像素电极包括第一和第二子像素电极,第二像素电极占据包括第一区域 以及比所述第一区域更靠近所述第三像素电极设置的第二区域; 分别连接到第一,第二和第三像素电极的第一,第二和第三薄膜晶体管; 分别连接到第一,第二和第三薄膜晶体管的第一,第二和第三栅极线; 以及连接到第一,第二和第三薄膜晶体管的数据线,其中第二子像素电极电容耦合到第三像素电极,并且第二子像素电极存在于第一和第三薄膜晶体管的第一和第三薄膜晶体管中, 第二区。
    • 72. 发明授权
    • Liquid crystal display and thin film transistor array panel therefor
    • 液晶显示器和薄膜晶体管阵列面板
    • US06999134B2
    • 2006-02-14
    • US10445849
    • 2003-05-28
    • Jung-Hee LeeYoon-Sung UmJong-Ho SonJae-Jin Lyu
    • Jung-Hee LeeYoon-Sung UmJong-Ho SonJae-Jin Lyu
    • G02F1/1343
    • G02F1/1368G02F1/13624G02F2001/134345H01L27/1255
    • A thin film transistor array panel is provided, which includes: an insulating substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer opposite the gate electrode; a data line formed on the gate insulating layer and including a first source electrode located on the semiconductor layer; first and second drain electrodes formed on the semiconductor layer, separated from each other and overlapping the gate electrode; a passivation layer formed on the data line and the first and the second drain electrodes; and first and second pixel electrodes electrically connected to the first and the second drain electrodes, respectively, wherein an overlapping area between the gate electrode and the first drain electrode is different from an overlapping area between the gate electrode and the second drain electrode.
    • 提供薄膜晶体管阵列面板,其包括:绝缘基板; 形成在所述基板上并包括栅电极的栅极线; 栅极绝缘层,形成在栅极线上; 形成在与栅电极相对的栅极绝缘层上的半导体层; 形成在所述栅绝缘层上并且包括位于所述半导体层上的第一源电极的数据线; 形成在半导体层上的第一和第二漏极彼此分离并与栅电极重叠; 形成在数据线和第一和第二漏电极上的钝化层; 以及分别与第一和第二漏电极电连接的第一和第二像素电极,其中栅电极和第一漏电极之间的重叠区域与栅电极和第二漏电极之间的重叠区域不同。
    • 78. 发明授权
    • Vertically aligned mode liquid crystal display with differentiated B cell gap
    • 具有差异化B细胞间隙的垂直对准模式液晶显示
    • US08253895B2
    • 2012-08-28
    • US12533895
    • 2009-07-31
    • Jang-Kun SongKyeong-Hyeon KimJae-Jin LyuSeung-Hee LeeSeung-Beom ParkYong-Woo Choi
    • Jang-Kun SongKyeong-Hyeon KimJae-Jin LyuSeung-Hee LeeSeung-Beom ParkYong-Woo Choi
    • G02F1/1335
    • G02F1/133707G02F1/134336G02F1/136213G02F1/1393G02F2201/121
    • A thin film transistor array substrate is provided with a gate line assembly, a data line assembly, and thin film transistors. The data line assembly crosses over the gate line assembly while defining pixel regions. A pixel electrode is formed at each pixel region. A color filter substrate is provided with a black matrix, and color filters of red, green and blue are formed at the black matrix at the pixel regions. An overcoat layer covers the color filters, and a common electrode is formed on the overcoat layer with an opening pattern. The thin film transistor array substrate, and the color filter substrates face each other, and a liquid crystal material is injected between the thin film transistor array substrate, and the color filter substrate. The blue color filter has a thickness smaller than the red color filter or the green color filter such that the liquid crystal cell gap at the blue color filter is larger than the liquid crystal cell gap at the red or green color filter.
    • 薄膜晶体管阵列基板设置有栅极线组件,数据线组件和薄膜晶体管。 数据线组件在限定像素区域的同时跨越栅极线组件。 在每个像素区域形成像素电极。 滤色器基板设置有黑矩阵,并且在像素区域处的黑矩阵处形​​成红色,绿色和蓝色的滤色器。 覆盖层覆盖滤色器,并且在外涂层上形成有开口图案的公共电极。 薄膜晶体管阵列基板和滤色器基板彼此面对,并且在薄膜晶体管阵列基板和滤色器基板之间注入液晶材料。 蓝色滤色器的厚度小于红色滤色器或绿色滤色器,使得蓝色滤色器处的液晶单元间隙大于红色或绿色滤色器处的液晶单元间隙。
    • 79. 发明授权
    • Display substrate and liquid crystal display device having the same
    • 显示基板和具有该基板的液晶显示装置
    • US08194216B2
    • 2012-06-05
    • US12173370
    • 2008-07-15
    • Yoon-Sung UmJae-Jin LyuSeung-Beom Park
    • Yoon-Sung UmJae-Jin LyuSeung-Beom Park
    • G02F1/1343
    • G09G3/3659G02F1/13624G02F1/136286G09G2300/0439
    • A display substrate includes an insulation substrate, an (n)-th gate line, a data line, first and second source electrodes, first and second drain electrodes, a pixel electrode, a third drain electrode, and a storage line. The first source electrode overlaps a first portion of the (n)-th gate line and is electrically connected to the data line. The first and second drain electrodes overlap a second portion of the (n)-th gate line. The pixel electrode is connected to the first drain electrode. The second source electrode overlaps a first portion of an (n+1)-th gate line, while the third drain electrode overlaps a second portion thereof. The storage line overlaps a portion of each of the pixel electrode and the second and third drain electrodes. The second source electrode is formed by extending the second drain electrode in a direction substantially from the (n)-th gate line towards the (n+1)-th gate line.
    • 显示基板包括绝缘基板,第(n)栅极线,数据线,第一和第二源极,第一和第二漏极,像素电极,第三漏极和存储线。 第一源电极与第(n)栅极线的第一部分重叠,并与数据线电连接。 第一和第二漏电极与第(n)栅极线的第二部分重叠。 像素电极连接到第一漏电极。 第二源电极与第(n + 1)栅极线的第一部分重叠,而第三漏电极与第二部分重叠。 存储线与像素电极和第二和第三漏电极中的每一个的一部分重叠。 第二源电极通过在大致从第(n)栅极线向第(n + 1)栅极线的方向延伸第二漏电极而形成。