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71. 发明授权

US06541169B1 Methods for charged-particle-beam microlithography including correction of deflection aberrations, and device-manufacturing methods comprising same 失效
标题翻译：包括偏转像差校正的带电粒子束微光刻的方法以及包括其的器件制造方法
公开(公告)号：US06541169B1
公开(公告)日：2003-04-01
申请号：US09638200
申请日：2000-08-11
申请人： Teruaki Okino , Shinichi Kojima
发明人： Teruaki Okino , Shinichi Kojima
IPC分类号： G03C500
CPC分类号： B82Y10/00 , B82Y40/00 , H01J37/153 , H01J37/3174 , H01J2237/30455 , Y10S430/143
摘要： Methods and apparatus are provided for performing charged-particle-beam microlithography at improved accuracy. A pattern is formed on a substrate (wafer) by repeated shot exposure of respective areas on a wafer substrate mounted on a wafer stage. Exposure of the wafer is made while the wafer stage is undergoing continuous motion and the charged particle beam making the exposure is being deflected continuously. As the magnitude of the beam deflection changes according to the motion of the stage, correction data for deflecting the beam are updated appropriately so as to correct deflection aberrations continuously.
摘要翻译：提供了以提高的精度进行带电粒子束微光刻的方法和装置。通过在安装在晶片台上的晶片衬底上的各个区域重复地曝光，在衬底（晶片）上形成图案。在晶片台进行连续运动时进行晶片的曝光，并且使曝光的带电粒子束被连续偏转。随着光束偏转的大小根据舞台的运动而变化，用于偏转光束的校正数据被适当地更新，以便连续校正偏转像差。

72. 发明授权

US6087821A Reference-voltage generating circuit 失效
标题翻译：基准电压发生电路
公开(公告)号：US6087821A
公开(公告)日：2000-07-11
申请号：US412983
申请日：1999-10-06
申请人： Shinichi Kojima
发明人： Shinichi Kojima
IPC分类号： G05F3/24 , G05F3/26 , H03F1/30 , H03F3/343 , G05F3/16
CPC分类号： G05F3/262 , G05F3/242
摘要： Saturation connection is performed between the gate and source of a depletion-type n-channel MOS transistor, and the depletion-type n-channel MOS transistor generates a first constant current. A current-mirror circuit is connected to the depletion-type n-channel MOS transistor, and mirrors the first constant current. A first enhancement-type n-channel MOS transistor generates a first constant voltage which depends on the first constant current, when receiving the first constant current mirrored by the current-mirror circuit and being activated. A first resistance element is connected between the first enhancement-type n-channel MOS transistor and ground. A second enhancement-type n-channel MOS transistor is connected to the first enhancement-type n-channel MOS transistor and the first resistance element, and controls generation of a second constant current in the first resistance element in accordance with activation of the first enhancement-type n-channel MOS transistor. A second resistance element is connected between a power-supply line and the second enhancement-type n-channel MOS transistor, and generates a second constant voltage which depends on the second constant current.
摘要翻译：在耗尽型n沟道MOS晶体管的栅极和源极之间进行饱和连接，而耗尽型n沟道MOS晶体管产生第一恒定电流。电流镜电路连接到耗尽型n沟道MOS晶体管，并反射第一恒定电流。第一增强型n沟道MOS晶体管当接收到由电流镜电路镜像并被激活的第一恒定电流时，产生取决于第一恒定电流的第一恒定电压。第一电阻元件连接在第一增强型n沟道MOS晶体管和地之间。第二增强型n沟道MOS晶体管连接到第一增强型n沟道MOS晶体管和第一电阻元件，并且根据第一增强的激活来控制第一电阻元件中的第二恒定电流的产生型n沟道MOS晶体管。第二电阻元件连接在电源线和第二增强型n沟道MOS晶体管之间，并产生依赖于第二恒定电流的第二恒定电压。

73. 发明授权

US6077186A Internal combustion engine starting drive control system for hybrid vehicle 有权
标题翻译：混合动力汽车内燃机起动驱动控制系统
公开(公告)号：US6077186A
公开(公告)日：2000-06-20
申请号：US206305
申请日：1998-12-07
申请人： Shinichi Kojima , Hidehiro Oba , Kazumi Hoshiya
发明人： Shinichi Kojima , Hidehiro Oba , Kazumi Hoshiya
IPC分类号： F02D29/02 , B60K6/20 , B60K6/48 , B60K6/54 , B60L11/12 , B60L11/14 , B60W10/02 , B60W10/06 , B60W10/08 , B60W10/10 , B60W20/00 , F16H61/00 , F16H61/06 , F16H61/20 , B60K1/02
CPC分类号： B60W20/00 , B60K6/48 , B60K6/54 , B60L11/12 , B60W10/02 , B60W10/06 , B60W10/08 , B60W10/10 , B60L2240/423 , B60L2240/441 , B60L2240/80 , B60W2510/0638 , B60W2510/0652 , B60W2510/0657 , B60W2510/0695 , B60W2510/244 , B60W2540/10 , B60W2710/0666 , B60W2710/083 , F16H2061/0087 , F16H2061/0477 , F16H2312/14 , F16H61/061 , F16H61/20 , Y02T10/6221 , Y02T10/6286 , Y02T10/642 , Y02T10/7005 , Y02T10/7077 , Y10S903/903 , Y10S903/917 , Y10S903/945 , Y10S903/946 , Y10T477/23 , Y10T477/26 , Y10T477/32
摘要： A drive control system for starting an internal combustion engine of a hybrid vehicle running while transmitting the output of an electric motor to a power transmission line for the run, by coupling the internal combustion engine to the power transmission line. The drive control system comprises: a start demand deciding unit for deciding a demand for the start of the internal combustion engine; and an assist setting unit for raising the output torque of the electric motor, when the demand for starting the internal combustion engine is decided by the start demand deciding unit, by a torque corresponding to either a motoring torque necessary for rotating the internal combustion engine or a summed torque of the motoring torque and an inertia torque according to the changing rate of the revolution speed of the internal combustion engine.
摘要翻译：一种驱动控制系统，用于通过将内燃机耦合到输电线路来启动混合动力车辆的内燃机，同时将电动机的输出传递到用于运行的输电线路。驱动控制系统包括：开始需求决定单元，用于决定对内燃机启动的需求; 以及辅助设定单元，用于当由起动需求决定单元决定启动内燃机的需求时，通过与旋转内燃机所需的电机转矩或转矩相对应的转矩来提高电动机的输出转矩，根据内燃机的转速的变化率，求出电动转矩和惯性转矩的总和转矩。

74. 发明授权

US6048401A Method and apparatus for immersion-process 失效
标题翻译：浸渍法的方法和装置
公开(公告)号：US6048401A
公开(公告)日：2000-04-11
申请号：US922151
申请日：1997-09-02
申请人： Hideaki Hayashi , Norio Kikukawa , Shinichi Kojima
发明人： Hideaki Hayashi , Norio Kikukawa , Shinichi Kojima
IPC分类号： C25D19/00 , C23C2/00 , B05C11/00
CPC分类号： C23C2/00
摘要： In a method and an apparatus for plating a plurality of kinds of works, an unattended route-free vehicle transports the works to a number of processing tanks to immerse the works in the processing tanks. A controller calculates a processing time of the processing tanks and a transporting time needed for the vehicle to transport the works to the processing tanks and renders the vehicle to transport one kind of the works during the immersion-processing of another kind of the works, thereby performing the plating process of a plurality of kinds of works one after another.
摘要翻译：在一种用于电镀多种工程的方法和装置中，无人值守的无路线车辆将工件运输到多个处理槽以将工件浸入处理槽中。控制器计算处理罐的处理时间和车辆将工程运送到处理罐所需的运输时间，并使车辆在另一种工件的浸入处理期间运输一种工件，从而一个接一个地进行多种作品的电镀处理。

75. 发明授权

US5999353A Magnetic disk storage apparatus with phase sync circuit having controllable response characteristic 失效
公开(公告)号：US5999353A
公开(公告)日：1999-12-07
申请号：US826972
申请日：1997-04-09
申请人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akihiko Hirano , Akira Uragami
发明人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akihiko Hirano , Akira Uragami
IPC分类号： G11B5/012 , G11B20/14 , H03K3/282 , H03L7/089 , H03L7/093 , H03L7/095 , H03L7/099 , H03L7/107 , H04L7/033 , G11B5/09 , G11B15/04
CPC分类号： H03L7/093 , G11B20/1403 , G11B5/012 , H03K3/2821 , H03L7/089 , H03L7/0895 , H03L7/0898 , H03L7/095 , H03L7/099 , H03L7/107 , G11B2020/10916 , H03L2207/06 , H04L7/033
摘要： A magnetic disk storage apparatus provides with a phase locked loop or a phase sync circuit including a phase comparator, a charge pump, a filter and a voltage-controlled oscillator. The phase sync circuit includes a register which is connected to an information processing system and adapted to store therein the response characteristics of the phase comparator, the charge pump, the filter and the voltage-controlled oscillator as instructed from the information processing system. In this way, in accordance with the information on the response characteristics from the information processing system, the phase sync circuit is controlled thereby to assure a stable operation even in the case of the data transfer speed varying between inner and outer track such as occurs in a magnetic disk.

76. 发明授权

US5892958A Peripheral equipment control device 失效
标题翻译：外围设备控制装置
公开(公告)号：US5892958A
公开(公告)日：1999-04-06
申请号：US757318
申请日：1996-11-27
申请人： Yukari Nagashige , Shoichi Miyazawa , Kunio Watanabe , Kouji Shida , Shinichi Kojima
发明人： Yukari Nagashige , Shoichi Miyazawa , Kunio Watanabe , Kouji Shida , Shinichi Kojima
IPC分类号： G06F1/32 , G06F13/10 , G06F15/78
CPC分类号： G06F1/3215 , G06F1/325 , G06F1/3268 , Y02B60/1246 , Y02B60/32
摘要： A peripheral equipment control LSI interposed between an SCSI bus connected to a main CPU and peripheral equipment such as a file device. The LSI is divided into two major blocks. One block recognizes an SCSI protocol ID signal sent over the SCSI bus. The other block generates a signal that causes the other block to leave a sleep state (low power dissipation mode). In a state in which a command is awaited from the main CPU, the peripheral equipment control LSI allows the block containing the ID recognition part to remain active while the other block is kept in the sleep state. On receiving an ID-based selected (access) signal from the main CPU, the LSI detects the start of an access operation and causes the other block to leave its sleep state and to become active.
摘要翻译：插入在连接到主CPU的SCSI总线和诸如文件装置的外围设备之间的外围设备控制LSI。 LSI分为两大块。一个块识别通过SCSI总线发送的SCSI协议ID信号。另一个块产生一个信号，导致另一个块离开睡眠状态（低功耗模式）。在从主CPU等待命令的状态下，外围设备控制LSI允许包含ID识别部分的块保持活动，而另一个块保持在睡眠状态。在从主CPU接收到基于ID的选择（访问）信号时，LSI检测到访问操作的开始，并使其他块离开其休眠状态并变为活动状态。

77. 发明授权

US5515068A One-chip semiconductor integrated circuit device capable of outputting analog color signal or digital color signal 失效
标题翻译：能够输出模拟彩色信号或数字彩色信号的单芯片半导体集成电路器件
公开(公告)号：US5515068A
公开(公告)日：1996-05-07
申请号：US300065
申请日：1994-09-02
申请人： Akira Uragami , Shinichi Kojima
发明人： Akira Uragami , Shinichi Kojima
IPC分类号： G09G5/04 , G06F1/32 , G06F3/14 , G09G3/36 , G09G5/00 , G09G5/06 , G09G5/36
CPC分类号： G09G5/06 , G09G5/366 , G06F3/1431
摘要： A semiconductor device (CPLT) of the invention comprises a first terminal (R) to which analog data is to be supplied, a digital/analog converter (DAC1) with its output coupled to the first terminal, a second terminal (R'0) to which digital data is to be supplied, a digital output circuit (DOB) with its output coupled to the second terminal, and a preparation means (PLM, SEL) which is coupled to respective inputs of the digital/analog converter and the digital output circuit, and prepares digital data to be processed (RR) for any one of input of the digital/analog converter and input of the digital output circuit.
摘要翻译：本发明的半导体器件（CPLT）包括：要向其提供模拟数据的第一端子（R），其输出耦合到第一端子的数模转换器（DAC1），第二端子（R'0）要向其提供数字数据的数字输出电路（DOB），其输出耦合到第二终端;以及准备装置（PLM，SEL），其耦合到数字/模拟转换器的相应输入端和数字输出端电路，并为数字/模拟转换器的输入和数字输出电路的输入中的任何一个准备待处理的数字数据（RR）。

78. 发明授权

US4975857A Graphic processing apparatus utilizing improved data transfer to reduce memory size 失效
标题翻译：利用改进的数据传输来减少存储器大小的图形处理装置
公开(公告)号：US4975857A
公开(公告)日：1990-12-04
申请号：US302332
申请日：1989-01-27
申请人： Koyo Katsura , Shinichi Kojima , Noriyuki Kurakami
发明人： Koyo Katsura , Shinichi Kojima , Noriyuki Kurakami
IPC分类号： G06F12/00 , G06F12/02 , G06F12/04 , G06F12/06 , G06F13/36 , G06T1/20 , G06T1/60 , G09G5/393
CPC分类号： G09G5/393 , G06T1/60
摘要： A Memory Interface and Video Attribute Controller (MIVAC) is inserted between a dynamic RAM (DRAM) capable of a consecutive data read operation, such as the operation associated with the static column mode, page mode, or nibble mode, and a graphic processor to provide a parallel data processing. A serial data transfer is executed on each data bus between the MIVAC and the DRAM, whereas parallel data transfer is conducted between the MIVAC and the graphic processor. As a result, the graphic processor can be configured with a reduced number of DRAMs so that the graphic processor operates without paying attention to the consecutive data read mode of the DRAM.
摘要翻译：存储器接口和视频属性控制器（MIVAC）插入在能够进行连续数据读取操作的动态RAM（DRAM）之间，诸如与静态列模式，页面模式或半字节模式相关联的操作，以及图形处理器提供并行数据处理。在MIVAC和DRAM之间的每个数据总线上执行串行数据传输，而在MIVAC和图形处理器之间进行并行数据传输。结果，图形处理器可以被配置为具有减少数量的DRAM，使得图形处理器在不关注DRAM的连续数据读取模式的情况下操作。

79. 发明授权

US4348386A Protease inhibitors 失效
标题翻译：蛋白酶抑制剂
公开(公告)号：US4348386A
公开(公告)日：1982-09-07
申请号：US249984
申请日：1981-04-01
申请人： Shinichi Kojima , Ten Koide , Shigeo Ogino , Toshiro Tsuchiya , Yoshito Kameno
发明人： Shinichi Kojima , Ten Koide , Shigeo Ogino , Toshiro Tsuchiya , Yoshito Kameno
IPC分类号： C07K7/02 , A61K33/06 , A61K35/74 , A61K38/55 , A61P1/04 , C07K5/02 , C07K14/81 , A61K37/00 , C07C103/52
CPC分类号： C07K5/0205
摘要： An acidic protease inhibitor obtained by allowing a compound of ##STR1## wherein X and Y are L-leucine or L-valine, or its salt, to react with an aluminum compound in a medium containing water and/or an alcohol, and further continuing the reaction after adjusting the pH of the system within a range of 4.5 to 7. The protease can stay long in stomach, have an action to protect ulcerated areas and retain the antiulcer effect for a long period of time.
摘要翻译：通过使其中X和Y是L-亮氨酸或L-缬氨酸或其盐的化合物与含有水和/或其盐的介质中的铝化合物反应获得的酸性蛋白酶抑制剂酒精，并且在4.5至7的范围内将系统的pH调节后进一步继续反应。蛋白酶可以在胃中保持长时间，具有保护溃疡区域并长时间保持抗溃疡作用的作用。

80. 发明授权

US09562792B2 Angle detector, motor drive controller, and motor device 有权
标题翻译：角度检测器，电机驱动控制器和电机装置
公开(公告)号：US09562792B2
公开(公告)日：2017-02-07
申请号：US14693247
申请日：2015-04-22
申请人： Shinichi Kojima , Katsuhisa Furuse
发明人： Shinichi Kojima , Katsuhisa Furuse
IPC分类号： H02K29/12 , G01B7/00 , G01D5/244 , G01D5/14 , G01D5/247 , G01D3/024
CPC分类号： G01D5/24485 , G01D3/024 , G01D5/145 , G01D5/247
摘要： An angle detector includes an intersection phase detector to compare each pair of multiple sensor signals or multiple sensor processed signals generate and output each intersection phase detection signal indicating a phase at which the signal level difference of the each pair is a first maximum hysteresis error after signal levels of signals of the each pair match, an intersection level detector to detect each intersection level and generate and output multiple intersection level signals indicating the detected intersection level, a signal selector to single out a selection signal of the either of the multiple sensor signals or the multiple sensor processed signals; a phase detector to detect that a signal level of the selection signal selected by the signal selector has reached a threshold level and a threshold level adjuster to adjust the threshold level based on the intersection level signal and the first maximum hysteresis error.
摘要翻译：角度检测器包括交叉相位检测器，用于比较每对多个传感器信号，或者多个传感器处理信号产生并输出每个交点相位检测信号，每个相位检测信号指示每一对的信号电平差是信号后的第一最大滞后误差每对信号的电平匹配，交叉点电平检测器，用于检测每个交叉电平，并产生并输出指示所检测的交叉电平的多个交叉电平信号;信号选择器，用于单独选择多个传感器信号的选择信号; 多传感器处理信号; 相位检测器，用于检测由信号选择器选择的选择信号的信号电平已经达到阈值电平;以及阈值电平调节器，基于交点电平信号和第一最大滞后误差来调整阈值电平。

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