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71. 发明申请

US20120039113A1 THREE DIMENSIONALLY STACKED NON VOLATILE MEMORY UNITS 失效
标题翻译：三维尺寸非易失性存储单元
公开(公告)号：US20120039113A1
公开(公告)日：2012-02-16
申请号：US13280395
申请日：2011-10-25
申请人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
发明人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： H01L27/228 , G11C11/161 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/142 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
摘要： A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.
摘要翻译：存储单元，包括跨越存储器单元的第一层中的第一晶体管区域的第一晶体管; 跨越存储器单元的第二层中的第二晶体管区域的第二晶体管; 跨越存储器单元的第三层中的第一存储器区域的第一电阻读出存储器（RSM）单元; 以及跨越存储器单元的第三层中的第二存储器区域的第二RSM单元，其中第一晶体管电耦合到第一RSM单元，并且第二晶体管电耦合到第二RSM单元，其中第二层是在第一和第三层之间，其中第一和第二晶体管具有晶体管重叠区域，并且其中第一存储区域和第二存储器区域不延伸超过第一晶体管区域和第二晶体管区域。

72. 发明申请

US20100265749A1 THREE DIMENSIONALLY STACKED NON VOLATILE MEMORY UNITS 有权
标题翻译：三维尺寸非易失性存储单元
公开(公告)号：US20100265749A1
公开(公告)日：2010-10-21
申请号：US12425084
申请日：2009-04-16
申请人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
发明人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
IPC分类号： G11C5/02 , H01L45/00 , G11C11/56
CPC分类号： H01L27/228 , G11C11/161 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/142 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
摘要： A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.
摘要翻译：存储单元，包括跨越存储器单元的第一层中的第一晶体管区域的第一晶体管; 跨越存储器单元的第二层中的第二晶体管区域的第二晶体管; 跨越存储器单元的第三层中的第一存储器区域的第一电阻读出存储器（RSM）单元; 以及跨越存储器单元的第三层中的第二存储器区域的第二RSM单元，其中第一晶体管电耦合到第一RSM单元，并且第二晶体管电耦合到第二RSM单元，其中第二层是在第一和第三层之间，其中第一和第二晶体管具有晶体管重叠区域，并且其中第一存储区域和第二存储器区域不延伸超过第一晶体管区域和第二晶体管区域。

73. 发明授权

US08482957B2 Three dimensionally stacked non volatile memory units 失效
标题翻译：三维堆叠的非易失性存储单元
公开(公告)号：US08482957B2
公开(公告)日：2013-07-09
申请号：US13280395
申请日：2011-10-25
申请人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
发明人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
IPC分类号： G11C11/00 , G11C11/14 , G11C11/22 , H01L23/52 , H01L23/02
CPC分类号： H01L27/228 , G11C11/161 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/142 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
摘要： A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.
摘要翻译：存储单元，包括跨越存储器单元的第一层中的第一晶体管区域的第一晶体管; 跨越存储器单元的第二层中的第二晶体管区域的第二晶体管; 跨越存储器单元的第三层中的第一存储器区域的第一电阻读出存储器（RSM）单元; 以及跨越存储器单元的第三层中的第二存储器区域的第二RSM单元，其中第一晶体管电耦合到第一RSM单元，并且第二晶体管电耦合到第二RSM单元，其中第二层是在第一和第三层之间，其中第一和第二晶体管具有晶体管重叠区域，并且其中第一存储区域和第二存储器区域不延伸超过第一晶体管区域和第二晶体管区域。

74. 发明申请

US20100097841A1 Multi-Stage Parallel Data Transfer 有权
标题翻译：多级并行数据传输
公开(公告)号：US20100097841A1
公开(公告)日：2010-04-22
申请号：US12487165
申请日：2009-06-18
申请人： Yong Lu , Harry Hongyue Liu , Hai Li , Andrew John Carter , Daniel Reed
发明人： Yong Lu , Harry Hongyue Liu , Hai Li , Andrew John Carter , Daniel Reed
IPC分类号： G11C11/00 , G11C7/10
CPC分类号： G11C13/0064 , G11C11/1675 , G11C11/56 , G11C13/0069 , G11C2013/0078 , G11C2013/0088 , G11C2211/5622 , G11C2211/5642 , G11C2211/5643 , G11C2213/79
摘要： Apparatus and associated method for transferring data to memory, such as resistive sense memory (RSM). In accordance with some embodiments, input data comprising a sequence of logical states are transferred to a block of memory by concurrently writing a first logical state from the sequence to each of a first plurality of unit cells during a first write step, and concurrently writing a second logical state from the sequence to each of a second non-overlapping plurality of unit cells during a second write step.
摘要翻译：用于将数据传送到存储器的装置和相关方法，例如电阻读出存储器（RSM）。根据一些实施例，包括逻辑状态序列的输入数据通过在第一写入步骤期间同时向第一多个单位单元中的每个单元写入第一逻辑状态而将第一逻辑状态写入存储器块，并且同时写入在第二写入步骤期间从序列到第二非重叠多个单位单元中的每一个的第二逻辑状态。

75. 发明申请

US20110205788A1 Spin-Torque Bit Cell With Unpinned Reference Layer and Unidirectional Write Current 有权
标题翻译：具有未引脚参考层和单向写入电流的自旋转矩位单元
公开(公告)号：US20110205788A1
公开(公告)日：2011-08-25
申请号：US13100953
申请日：2011-05-04
申请人： Daniel Seymour Reed , Yong Lu , Song S. Xue , Dimitar V. Dimitrov , Paul E. Anderson
发明人： Daniel Seymour Reed , Yong Lu , Song S. Xue , Dimitar V. Dimitrov , Paul E. Anderson
IPC分类号： G11C11/15
CPC分类号： H01F10/329 , B82Y25/00 , G01R33/098 , G01R33/1284 , G11C11/1659 , G11C11/1673 , G11C11/1675 , H01F10/3254
摘要： Method and apparatus for using a uni-directional write current to store different logic states in a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, the memory cell has an unpinned ferromagnetic reference layer adjacent a cladded conductor, a ferromagnetic storage layer and a tunneling barrier between the reference layer and the storage layer. Passage of a current along the cladded conductor induces a selected magnetic orientation in the reference layer, which is transferred through the tunneling barrier for storage by the storage layer. Further, the orientation of the applying step is provided by a cladding layer adjacent a conductor along which a current is passed and the current induces a magnetic field in the cladding layer of the selected magnetic orientation.
摘要翻译：用于使用单向写入电流来存储非易失性存储器单元（诸如修改的STRAM单元）中的不同逻辑状态的方法和装置。在一些实施例中，存储器单元具有与包层导体相邻的未固定的铁磁参考层，铁磁存储层和参考层与存储层之间的隧道势垒。沿着包层导体的电流的通过在参考层中引入选定的磁取向，该参考层通过隧道势垒传递，以通过存储层进行存储。此外，施加步骤的取向由邻近导体的包层提供，电流通过该导体，并且电流在所选择的磁方向的包层中感应出磁场。

76. 发明授权

US08098538B2 Spin-torque bit cell with unpinned reference layer and unidirectional write current 有权
标题翻译：具有未固定参考层和单向写入电流的自旋转矩位单元
公开(公告)号：US08098538B2
公开(公告)日：2012-01-17
申请号：US13100953
申请日：2011-05-04
申请人： Daniel Seymour Reed , Yong Lu , Song S. Xue , Dimitar V. Dimitrov , Paul E. Anderson
发明人： Daniel Seymour Reed , Yong Lu , Song S. Xue , Dimitar V. Dimitrov , Paul E. Anderson
IPC分类号： G11C7/00
CPC分类号： H01F10/329 , B82Y25/00 , G01R33/098 , G01R33/1284 , G11C11/1659 , G11C11/1673 , G11C11/1675 , H01F10/3254
摘要： Method and apparatus for using a uni-directional write current to store different logic states in a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, the memory cell has an unpinned ferromagnetic reference layer adjacent a cladded conductor, a ferromagnetic storage layer and a tunneling barrier between the reference layer and the storage layer. Passage of a current along the cladded conductor induces a selected magnetic orientation in the reference layer, which is transferred through the tunneling barrier for storage by the storage layer. Further, the orientation of the applying step is provided by a cladding layer adjacent a conductor along which a current is passed and the current induces a magnetic field in the cladding layer of the selected magnetic orientation.
摘要翻译：用于使用单向写入电流来存储非易失性存储器单元（诸如修改的STRAM单元）中的不同逻辑状态的方法和装置。在一些实施例中，存储器单元具有与包层导体相邻的未固定的铁磁参考层，铁磁存储层和参考层与存储层之间的隧道势垒。沿着包层导体的电流的通过在参考层中引入选定的磁取向，该参考层通过隧道势垒传递，以通过存储层进行存储。此外，施加步骤的取向由邻近导体的包层提供，电流通过该导体，并且电流在所选择的磁方向的包层中感应出磁场。

77. 发明申请

US20100135072A1 Spin-Torque Bit Cell With Unpinned Reference Layer and Unidirectional Write Current 有权
标题翻译：具有未引脚参考层和单向写入电流的自旋转矩位单元
公开(公告)号：US20100135072A1
公开(公告)日：2010-06-03
申请号：US12326314
申请日：2008-12-02
申请人： Daniel Seymour Reed , Yong Lu , Song S. Xue , Dimitar V. Dimitrov , Paul E. Anderson
发明人： Daniel Seymour Reed , Yong Lu , Song S. Xue , Dimitar V. Dimitrov , Paul E. Anderson
IPC分类号： G11C11/14 , G11C11/416
CPC分类号： H01F10/329 , B82Y25/00 , G01R33/098 , G01R33/1284 , G11C11/1659 , G11C11/1673 , G11C11/1675 , H01F10/3254
摘要： Method and apparatus for using a uni-directional write current to store different logic states in a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, the memory cell has an unpinned ferromagnetic reference layer adjacent a cladded conductor, a ferromagnetic storage layer and a tunneling barrier between the reference layer and the storage layer. Passage of a current along the cladded conductor induces a selected magnetic orientation in the reference layer, which is transferred through the tunneling barrier for storage by the storage layer. Further, the orientation of the applying step is provided by a cladding layer adjacent a conductor along which a current is passed and the current induces a magnetic field in the cladding layer of the selected magnetic orientation.
摘要翻译：用于使用单向写入电流来存储非易失性存储器单元（诸如修改的STRAM单元）中的不同逻辑状态的方法和装置。在一些实施例中，存储器单元具有与包层导体相邻的未固定的铁磁参考层，铁磁存储层和参考层与存储层之间的隧道势垒。沿着包层导体的电流的通过在参考层中引入选定的磁取向，该参考层通过隧道势垒传递，以通过存储层进行存储。此外，施加步骤的取向由邻近导体的包层提供，电流通过该导体，并且电流在所选择的磁方向的包层中感应出磁场。

78. 发明授权

US08363449B2 Floating source line architecture for non-volatile memory 有权
标题翻译：用于非易失性存储器的浮动源线架构
公开(公告)号：US08363449B2
公开(公告)日：2013-01-29
申请号：US13206550
申请日：2011-08-10
申请人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
发明人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C7/12 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C13/0069
摘要： A method and apparatus for writing data to a non-volatile memory cell, such as an STRAM memory cell or an RRAM memory cell. In some embodiments, a plurality of N non-volatile memory cells, where N is a greater than two, are connected to a common floating source line. A write circuit is adapted to program a selected memory cell of the plurality to a selected data state by passing a write current of selected magnitude through the selected memory cell and concurrently passing a portion of the write current in parallel through each of the remaining N−1 memory cells of the plurality via the common floating source line.
摘要翻译：用于将数据写入诸如STRAM存储器单元或RRAM存储器单元的非易失性存储单元的方法和装置。在一些实施例中，其中N大于2的多个N个非易失性存储器单元连接到公共的浮动源线。写入电路适于通过将所选择的大小的写入电流通过所选择的存储器单元来编程所选择的数据状态的所选择的存储单元，并且并行地通过所述剩余的N- 1个存储单元经由公共浮动源线。

79. 发明授权

US08004872B2 Floating source line architecture for non-volatile memory 有权
标题翻译：用于非易失性存储器的浮动源线架构
公开(公告)号：US08004872B2
公开(公告)日：2011-08-23
申请号：US12272507
申请日：2008-11-17
申请人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
发明人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
IPC分类号： G11C11/10
CPC分类号： G11C13/0002 , G11C7/12 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C13/0069
摘要： A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a bit line while the switching device of a plurality of memory cells is connected to a word line and operated to select a memory cell. A source line is connected to the switching device and connects a series of memory cells together. Further, a driver circuit is connected to the bit line and writes a selected RSE of a selected source line to a selected resistive state by passing a write current along a write current path that passes through the selected RSE and through at least a portion of the remaining RSE connected to the selected source line.
摘要翻译：一种将数据写入诸如RRAM存储单元的非易失性存储单元的方法和装置。在一些实施例中，非易失性存储单元的半导体阵列包括电阻感测元件（RSE）和开关器件。多个存储单元的RSE连接到位线，而多个存储单元的开关器件连接到字线并被操作以选择存储器单元。源极线连接到开关器件，并将一系列存储器单元连接在一起。此外，驱动器电路连接到位线，并且通过使写入电流沿着通过所选择的RSE的写入电流路径并且通过至少一部分所述选择的RSE而将所选择的源极线的选定RSE写入所选择的电阻状态剩余的RSE连接到所选择的源线。

80. 发明授权

US07830708B1 Compensating for variations in memory cell programmed state distributions 有权
标题翻译：补偿存储单元编程状态分布的变化
公开(公告)号：US07830708B1
公开(公告)日：2010-11-09
申请号：US12428002
申请日：2009-04-22
申请人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
发明人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
IPC分类号： G11C16/00
CPC分类号： G11C11/5642 , G11C16/0483 , G11C2211/5631 , G11C2211/5632
摘要： Method and apparatus for compensating for variations in memory cell programmed state distributions, such as but not limited to a non-volatile memory formed of NAND configured Flash memory cells. In accordance with various embodiments, a memory block is formed from a plurality of memory cells that are arranged into rows and columns within the memory block, each memory cell configured to have a programmed state. A selected row of the memory block is read by concurrently applying a stepped sequence of threshold voltages to each memory cell along the selected row while sequentially decoupling read current from groups of memory cells along the selected row as the programmed states of said groups of cells are successively determined.
摘要翻译：用于补偿存储器单元编程状态分布的变化的方法和装置，例如但不限于由NAND配置的闪存单元形成的非易失性存储器。根据各种实施例，存储器块由多个存储器单元形成，多个存储器单元被布置成存储器块内的行和列，每个存储器单元被配置为具有编程状态。存储器块的选定行通过沿着所选择的行并行地向每个存储器单元施加阶梯式序列来读取，同时沿着所选行的顺序地将读取电流与存储器单元组分离，因为所述单元组的编程状态为先后确定。

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