专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US08225183B2 Methods and apparatus for selective data retention decoding in a hard disk drive 有权
标题翻译：用于在硬盘驱动器中进行选择性数据保存解码的方法和装置
公开(公告)号：US08225183B2
公开(公告)日：2012-07-17
申请号：US12241919
申请日：2008-09-30
申请人： Jingfeng Liu , Shaohua Yang , Hongwei Song , Yuan Xing Lee
发明人： Jingfeng Liu , Shaohua Yang , Hongwei Song , Yuan Xing Lee
IPC分类号： H03M13/00
CPC分类号： G11B20/18 , G11B2020/183 , G11B2220/2516 , H03M13/1105 , H03M13/2948 , H03M13/2957 , H03M13/6343
摘要： Methods and apparatus are provided for improved physical re-read operations in a hard disk drive. The disclosed methods and apparatus selectively retain data in a hard disk drive. A signal is read in an iterative read channel by assigning a reliability metric to each of a plurality of segments in a read signal; repeating the assigning step for a plurality of read operations; and selectively retaining the segments based on the assigned reliability metric. The read signal can be obtained by positioning a transducer over a storage media. The reliability metric may be based on soft bit decisions; log likelihood ratios or a noise estimation of a given segment.
摘要翻译：提供了用于改进硬盘驱动器中物理重读操作的方法和装置。所公开的方法和设备选择性地将数据保留在硬盘驱动器中。通过将读取信号中的多个段中的每一个分配可靠度度量，在迭代读取通道中读取信号; 重复多个读取操作的分配步骤; 并且基于所分配的可靠性度量选择性地保留段。可以通过将传感器定位在存储介质上来获得读取信号。可靠性度量可以基于软比特决策; 对数似然比或给定段的噪声估计。

72. 发明授权

US08176400B2 Systems and methods for enhanced flaw scan in a data processing device 有权
标题翻译：用于在数据处理设备中增强缺陷扫描的系统和方法
公开(公告)号：US08176400B2
公开(公告)日：2012-05-08
申请号：US12556180
申请日：2009-09-09
申请人： Weijun Tan , Shaohua Yang , Hongwei Song , Richard Rauschmayer
发明人： Weijun Tan , Shaohua Yang , Hongwei Song , Richard Rauschmayer
IPC分类号： H03M13/00
CPC分类号： H04L1/0057 , H04L1/0045
摘要： Various embodiments of the present invention provide systems and methods for flaw scan in a data processing system. As one example, a data processing system is disclosed that includes a data detector circuit, a bit sign inverting circuit, and an LDPC decoder circuit. The data detector circuit receives a verification data set that is an invalid LDPC codeword, and applies a data detection algorithm to the verification data set to yield a detected output. The bit sign inverting circuit modifies the sign of one or more elements of a first derivative of the detected output to yield a second derivative of the detected output. The second derivative of the detected output is an expected valid LDPC codeword. The LDPC decoder circuit applies a decoding algorithm to the second derivative of the detected output to yield a decoded output.
摘要翻译：本发明的各种实施例提供了在数据处理系统中的缺陷扫描的系统和方法。作为一个示例，公开了包括数据检测器电路，位符号反相电路和LDPC解码器电路的数据处理系统。数据检测器电路接收作为无效LDPC码字的验证数据集，并将数据检测算法应用于验证数据集以产生检测到的输出。位符号反相电路修改检测输出的一阶导数的一个或多个元素的符号，以产生检测到的输出的二阶导数。所检测的输出的二阶导数是期望的有效LDPC码字。 LDPC解码器电路将解码算法应用于检测输出的二阶导数，以产生解码输出。

73. 发明授权

US07990642B2 Systems and methods for storage channel testing 有权
标题翻译：存储通道测试的系统和方法
公开(公告)号：US07990642B2
公开(公告)日：2011-08-02
申请号：US12425757
申请日：2009-04-17
申请人： Yuan Xing Lee , George Mathew , Shaohua Yang , Hongwei Song , Weijun Tan , Hao Zhong
发明人： Yuan Xing Lee , George Mathew , Shaohua Yang , Hongwei Song , Weijun Tan , Hao Zhong
IPC分类号： G11B27/36
CPC分类号： G11B20/182 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for validating elements of storage devices. A an example, various embodiments of the present invention provide semiconductor devices that include a write path circuit, a read path circuit and a validation circuit. The write path circuit is operable to receive a data input and to convert the data input into write data suitable for storage to a storage medium. The read path circuit is operable to receive read data and to convert the read data into a data output. The validation circuit is operable to: receive the write data, augment the write data with a first noise sequence to yield a first augmented data series; and augment a derivative of the first augmented data series with a second noise sequence to yield the read data.
摘要翻译：本发明的各种实施例提供用于验证存储设备的元件的系统和方法。作为示例，本发明的各种实施例提供包括写入路径电路，读取路径电路和验证电路的半导体器件。写入路径电路可操作用于接收数据输入并将数据输入转换成适合于存储的写数据到存储介质。读路径电路可操作以接收读数据并将读数据转换为数据输出。验证电路可操作以：接收写入数据，用第一噪声序列增加写入数据以产生第一增强数据序列; 并且用第二噪声序列来增加第一增强数据序列的导数以产生读取的数据。

74. 发明申请

US20100226033A1 Systems and Methods for Enhanced Media Defect Detection 有权
标题翻译：增强介质缺陷检测的系统和方法
公开(公告)号：US20100226033A1
公开(公告)日：2010-09-09
申请号：US12399713
申请日：2009-03-06
申请人： Weijun Tan , Hongwei Song , Shaohua Yang
发明人： Weijun Tan , Hongwei Song , Shaohua Yang
IPC分类号： G11B5/09
CPC分类号： G11B5/09 , G11B20/10009 , G11B20/10046 , G11B20/10055 , H03M13/3905
摘要： Various embodiments of the present invention provide systems and methods for detecting storage medium defects. As one example, a media defect detection system is disclosed that includes a data detector circuit that applies a detection algorithm to the data input and provides a hard output and a soft output. A first circuit combines a first derivative of the hard output with a derivative of the data input to yield a first combined signal. A second circuit combines a second derivative of the hard output with a derivative of the first combined signal to yield a second combined signal. A third circuit combines a derivative of the soft output with the second combined signal and a threshold value to yield a defect signal.
摘要翻译：本发明的各种实施例提供了用于检测存储介质缺陷的系统和方法。作为一个示例，公开了一种媒体缺陷检测系统，其包括将检测算法应用于数据输入并提供硬输出和软输出的数据检测器电路。第一电路将硬输出的一阶导数与数据输入的导数组合以产生第一组合信号。第二电路将硬输出的二阶导数与第一组合信号的导数组合以产生第二组合信号。第三电路将软输出的导数与第二组合信号和阈值组合以产生缺陷信号。

75. 发明申请

US20100091629A1 Method for detecting short burst errors in LDPC system 有权
标题翻译：用于检测LDPC系统中短脉冲串错误的方法
公开(公告)号：US20100091629A1
公开(公告)日：2010-04-15
申请号：US12287959
申请日：2008-10-15
申请人： Weijun Tan , Shaohua Yang , Hongwei Song
发明人： Weijun Tan , Shaohua Yang , Hongwei Song
IPC分类号： G11B27/36
CPC分类号： H03M13/1128 , H03M13/17
摘要： The present invention is a device for detecting short burst errors. The device includes a first signal input, wherein the first signal input is configured to receive a first signal. The device includes a second signal input, wherein the second signal input is configured to receive a second signal. The device includes a logic gate, wherein the logic gate is operable for receiving the first signal vial the first signal input, receiving the second signal via the second signal input, and generating a logic output gate signal based on the received first signal and the second signal. Furthermore, the device includes a filter, wherein the filter is configured for receiving the logic output gate signal from the logic gate and generates a filter output signal based upon the received logic output gate signal, wherein the filter output signal is operable for flagging errors.
摘要翻译：本发明是用于检测短脉冲串错误的装置。该设备包括第一信号输入，其中第一信号输入被配置为接收第一信号。该设备包括第二信号输入，其中第二信号输入被配置为接收第二信号。该装置包括逻辑门，其中逻辑门可操作用于接收第一信号输入端，第一信号输入端，经由第二信号输入端接收第二信号，并根据接收到的第一信号和第二信号产生逻辑输出门信号信号。此外，该器件包括滤波器，其中滤波器被配置为从逻辑门接收逻辑输出门信号，并且基于接收的逻辑输出门信号产生滤波器输出信号，其中滤波器输出信号可用于标记误差。

76. 发明授权

US09019647B2 Systems and methods for conditional positive feedback data decoding 有权
标题翻译：条件正反馈数据解码的系统和方法
公开(公告)号：US09019647B2
公开(公告)日：2015-04-28
申请号：US13596947
申请日：2012-08-28
申请人： Fan Zhang , Shaohua Yang
发明人： Fan Zhang , Shaohua Yang
IPC分类号： G11B5/09 , G11B20/10 , H03M7/00 , H04L27/06 , H03M13/11 , H03M13/37 , H03M13/00 , G11B5/012 , H03M13/15 , H03M13/41
CPC分类号： G11B5/09 , G11B5/012 , G11B20/10268 , G11B20/10509 , H03M7/00 , H03M13/1128 , H03M13/1515 , H03M13/3753 , H03M13/41 , H03M13/6331 , H03M13/6343 , H04L25/03286 , H04L25/03318 , H04L27/06
摘要： The present inventions are related to systems and methods for information data processing included selective decoder message determination. In one example, a data processing system is disclosed that includes a data decoder circuit operable to apply a conditional data decoding algorithm to a data set to yield a decoded output. The conditional decoding algorithm is operable to calculate node messages using an approach selected from a group consisting of: a first message determination mechanism, and a second message determination mechanism; where one of the first message determination mechanism and the second message determination mechanism is selected based upon a condition that includes a global iteration count applied to the data set.
摘要翻译：本发明涉及包括选择性解码器消息确定的信息数据处理的系统和方法。在一个示例中，公开了一种数据处理系统，其包括数据解码器电路，其可操作以将条件数据解码算法应用于数据集以产生解码输出。条件解码算法可操作以使用从由以下组成的组中选择的方法来计算节点消息：第一消息确定机制和第二消息确定机制; 其中基于包括应用于数据集的全局迭代计数的条件来选择第一消息确定机制和第二消息确定机制中的一个。

77. 发明授权

US08972761B2 Systems and methods for idle clock insertion based power control 有权
标题翻译：基于空闲时钟插入的功率控制系统和方法
公开(公告)号：US08972761B2
公开(公告)日：2015-03-03
申请号：US13364217
申请日：2012-02-01
申请人： Shaohua Yang , Changyou Xu , Fan Zhang
发明人： Shaohua Yang , Changyou Xu , Fan Zhang
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3268 , G11B19/02 , G11B19/209 , Y02D10/126 , Y02D10/154
摘要： The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. In one particular case, a system is disclosed that includes a first data processing circuit operable to apply a data detection algorithm to a data input synchronous to a first clock, and a second data processing circuit operable to apply a subsequent data processing algorithm to an output derived from the first data processing circuit synchronous to a second clock, and an idle time enforcement circuit operable to modify an average frequency of at least one of the first clock and the second clock.
摘要翻译：本发明涉及用于数据处理的系统和方法，更具体地涉及用于数据处理系统中的功率治理的系统和方法。在一个具体情况下，公开了一种系统，其包括可操作以将数据检测算法应用于与第一时钟同步的数据输入的第一数据处理电路，以及可操作以将后续数据处理算法应用于输出的第二数据处理电路来自与第二时钟同步的第一数据处理电路，以及空闲时间执行电路，其可操作以修改第一时钟和第二时钟中的至少一个的平均频率。

78. 发明授权

US08947804B2 Systems and methods for combined binary and non-binary data processing 有权
标题翻译：用于组合二进制和非二进制数据处理的系统和方法
公开(公告)号：US08947804B2
公开(公告)日：2015-02-03
申请号：US13316758
申请日：2011-12-12
申请人： Zongwang Li , Chung-Li Wang , Shaohua Yang , Changyou Xu , Lei Chen , Yang Han
发明人： Zongwang Li , Chung-Li Wang , Shaohua Yang , Changyou Xu , Lei Chen , Yang Han
IPC分类号： G11B5/02 , H03M13/11
CPC分类号： G11B5/02 , H03M13/1171
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a combination data decoder circuit. The combination data decoder circuit includes: a non-binary data decoder circuit and a binary data decoder circuit.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了一种包括组合数据解码器电路的数据处理系统。组合数据解码器电路包括：非二进制数据解码器电路和二进制数据解码器电路。

79. 发明授权

US08887034B2 Systems and methods for short media defect detection 有权
标题翻译：用于短介质缺陷检测的系统和方法
公开(公告)号：US08887034B2
公开(公告)日：2014-11-11
申请号：US13088119
申请日：2011-04-15
申请人： Fan Zhang , Shaohua Yang
发明人： Fan Zhang , Shaohua Yang
IPC分类号： G06F7/02 , H03M13/00 , G06F11/07
CPC分类号： G06F11/0754
摘要： Various embodiments of the present invention provide systems and methods for media defect detection. As an example, a data processing circuit is disclosed that includes a defect detector circuit and a comparator circuit. The defect detector circuit is operable to calculate a correlation value combining at least three of a data input derived from a medium, a detector extrinsic output, a detector intrinsic output and a decoder output. The comparator circuit is operable to compare the correlation value to a threshold value and to assert a media defect indicator when the correlation value is less than the threshold value.
摘要翻译：本发明的各种实施例提供了用于介质缺陷检测的系统和方法。作为示例，公开了包括缺陷检测器电路和比较器电路的数据处理电路。缺陷检测器电路可操作以计算组合从介质导出的数据输入，检测器外在输出，检测器本征输出和解码器输出中的至少三个的相关值。比较器电路可操作以将相关值与阈值进行比较，并且当相关值小于阈值时断言介质缺陷指示符。

80. 发明授权

US08880986B2 Systems and methods for improved data detection processing 有权
标题翻译：改进数据检测处理的系统和方法
公开(公告)号：US08880986B2
公开(公告)日：2014-11-04
申请号：US13483105
申请日：2012-05-30
申请人： Xuebin Wu , Wu Chang , Shaohua Yang , Fan Zhang
发明人： Xuebin Wu , Wu Chang , Shaohua Yang , Fan Zhang
IPC分类号： H03M13/00
CPC分类号： G11B20/10046 , G06F11/008 , H04L1/005 , H04L25/03012 , H04L25/067 , H04L2025/03496
摘要： The present invention is related to systems and methods for enhancing data detection in a data processing system. In one embodiment, a data processing system is disclosed that includes a data detector circuit that is governed at least in part based upon selected coefficients. The selected coefficients are selected as either a first set of coefficients or a second set of coefficients where the second set of coefficients has fewer coefficients than the first set of coefficients.
摘要翻译：本发明涉及用于增强数据处理系统中的数据检测的系统和方法。在一个实施例中，公开了一种数据处理系统，其包括至少部分地基于所选择的系数来管理的数据检测器电路。选择的系数被选择为第一组系数或第二组系数，其中第二组系数具有比第一组系数更少的系数。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式