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71. 发明专利

JP2514963B2 失效
公开(公告)号：JP2514963B2
公开(公告)日：1996-07-10
申请号：JP10192187
申请日：1987-04-27
申请人： HITACHI LTD
发明人： BABA SHIRO
IPC分类号： G06F9/42 , G06F9/46 , G06F9/48

72. 发明专利

JPH0250493B2 失效
公开(公告)号：JPH0250493B2
公开(公告)日：1990-11-02
申请号：JP18389980
申请日：1980-12-26
申请人： HITACHI LTD
发明人： BABA SHIRO
IPC分类号： G06F11/28 , G06F9/06 , G06F9/22 , G06F12/16

73. 发明专利

JPH02125380A MICROPROCESSOR 失效
公开(公告)号：JPH02125380A
公开(公告)日：1990-05-14
申请号：JP23279289
申请日：1989-09-11
申请人： HITACHI LTD
发明人： BABA SHIRO
IPC分类号： G06F3/05 , G06F15/78 , H03M1/12
摘要： PURPOSE:To decrease the number of terminals by making at least some of analog input terminals coupled with a multiplexer common to an external terminal coupled with a port. CONSTITUTION:Some of digital signal terminals (e.g. P4 and P5) are used as analog input terminals. When the terminals P4 and P5 which are used in common are used as input/output terminals for digital signals, a multiplexer 13 or A/D converting circuit 14 inhibit input or output. When the terminals P4 and P5 which are used in common are used as analog input terminals, on the other hand, an output circuit corresponding to an input/output port 12 is made high in impedance to input the analog signals from the terminals to the A/D converting circuit 14. Consequently, the number of terminals can be decreased.

74. 发明专利

JPH0283678A DATA PROCESSING SYSTEM DEVELOPING METHOD 失效
公开(公告)号：JPH0283678A
公开(公告)日：1990-03-23
申请号：JP23592088
申请日：1988-09-20
申请人： HITACHI LTD
发明人： AKAO YASUSHI , BABA SHIRO , SAWASE TERUMI , HAGIWARA YOSHIMUNE
IPC分类号： G06F15/78 , G06F17/50
摘要： PURPOSE:To flexibly and easily respond to the change of the operating specification and the function of a data processing system by writing required data on a nonvolatile storage element included in a logic function block corresponding to a function requested to the system. CONSTITUTION:A single chip microcomputer 1 is constituted of a processor 5, a programmable logic array 6, and an input/output port 7, and respective block is connected with a common bus 8. In the case of necessitating the change of the operating specification or the function of the system on the middle way of a developing process when the data processing system is comprised by setting a semiconductor integrated circuit for data processing including an electrically loadable logic function block or a nonvolatile memory block as a key component, information with respect to the hardware-oriented logic function of the logic function block and the nonvolatile memory block are programmed electrically on the nonvolatile storage element corresponding to their change. In such a way, it is possible to respond to the change of the operating specification or the function of the system.

75. 发明专利

JPH01162971A SINGLE-CHIP MICROCOMPUTER 失效
公开(公告)号：JPH01162971A
公开(公告)日：1989-06-27
申请号：JP9156388
申请日：1988-04-15
申请人： HITACHI LTD
发明人： SAWASE TERUMI , NOGUCHI YOSHIKI , NAKAMURA HIDEO , AKAO YASUSHI , BABA SHIRO , HAGIWARA YOSHIMUNE
IPC分类号： G11C29/00 , G06F7/00 , G06F9/22 , G06F9/24 , G06F15/78 , G11C16/02 , G11C17/00
摘要： PURPOSE:To improve universal applicability and to decrease the number of parts of a single-chip microcomputer by adding a logic circuit device including a nonvolatile semiconductor memory element capable of the electrical writing into a chip. CONSTITUTION:A programmable logic array (PLA) 6 set on a semiconductor substrate 1 functions as a logical device to realize the hardware of a single-chip microcomputer. The PLA 6 includes a nonvolatile memory element which is capable of the electrical writing. Thus the logical function of the logical device can be optionally obtained based on the information written from outside. Then this logical function can satisfy the various specifications requested by users. Thus it is possible to improve the universal applicability of the single-chip microcomputer and also to decrease the number of parts forming the periphery of said microcomputer.

76. 发明专利

JPS63268033A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS63268033A
公开(公告)日：1988-11-04
申请号：JP10192187
申请日：1987-04-27
申请人： HITACHI LTD
发明人： BABA SHIRO
IPC分类号： G06F9/42 , G06F9/46 , G06F9/48
摘要： PURPOSE:To improve the switching flexibility for a register set by designating a register when register sets are switched and delivering the contents of the register to the corresponding register in another register via an instruction. CONSTITUTION:A code which increases or decreases the number of a register bank (register set) is put into an operation code designating field OP1 of a register switch instruction. A field R is secured after the field OP1 to show whether the register contents are delivered or not. Thus the contents of a register designated in a register designating field Rn-list following the field R are delivered to the corresponding register of a switched register bank as long as '1' is set in the field R. When '0' is set in the field R, the register banks are switched with no delivery of their banks in a register bank switching mode.

77. 发明专利

JPS61127056A Data processor 失效
标题翻译：数据处理器
公开(公告)号：JPS61127056A
公开(公告)日：1986-06-14
申请号：JP24810984
申请日：1984-11-26
申请人： Hitachi Ltd
发明人： BABA SHIRO
IPC分类号： G11C11/406 , G06F12/00 , G06F12/02 , G06F12/06 , G06F15/78
CPC分类号： G06F12/0653
摘要： PURPOSE: To design easily a system by using a control signal producing circuit which is controlled by the control data written to a register and produces the control signal needed by a memory.
CONSTITUTION: A microprocessor part CPU consists of an executing unit EXCE and a control part CONT, and an oscillation circuit OSC and a clock generating circuit CPG are added for control of the operation timing of the part CPU. A refresh counter RC which produces the refresh address of a dynamic RAM is provided on a semiconductor substrate equal to the part CPU together with an address multiplexer MPX which transmits selectively one of both outputs delivered from the counter RC and the unit EXEC, and a control signal generating circuit SCG which controls the multiplexer MPX.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过使用由写入寄存器的控制数据控制的控制信号产生电路来设计系统，并产生存储器所需的控制信号。构成：微处理器部分CPU由执行单元EXCE和控制部CONT组成，并且添加振荡电路OSC和时钟发生电路CPG以控制部分CPU的操作定时。产生动态RAM的刷新地址的刷新计数器RC与地址复用器MPX一起提供在等于部分CPU的半导体衬底上，地址复用器MPX选择性地传送从计数器RC和单元EXEC传送的两个输出中的一个，以及控制控制复用器MPX的信号发生电路SCG。

78. 发明专利

JPH11102286A CIRCUIT AND METHOD FOR DIVISION 失效
公开(公告)号：JPH11102286A
公开(公告)日：1999-04-13
申请号：JP15814398
申请日：1998-06-05
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F7/537 , G06F7/52 , G06F7/535 , G06F9/30 , G06F9/305 , G06F9/32 , G06F9/38
摘要： PROBLEM TO BE SOLVED: To provide a circuit and a method for division with which a correct quotient can be easily found without detecting whether the partial remainder is '0' or not for each step of division for finding the quotient bit even when a dividend is negative. SOLUTION: When a dividend X is negative in the coded division expressed as Y (quotient) = X (dividend) ÷ 3 (divisor), for example, preprocessing is performed to define a value (X-1) subtracting '1' from the dividend X as a dividend. The preprocessing is processing for conceptionally shifting the coordinate axis of the quotient Y to left for '1'. The processing of division is performed in the shifting state. Thus, it is not necessary to discriminate whether the partial remainder is '0' or not conventionally every time in the middle of arithmetic processing and a hardware for that discrimination is unnecessitated as well. When finding the exact remainder, the found remainder is finally corrected.

79. 发明专利

JPH1196000A CPU AND MICROCOMPUTER 失效
公开(公告)号：JPH1196000A
公开(公告)日：1999-04-09
申请号：JP15814298
申请日：1998-06-05
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F9/30 , G06F9/35
摘要： PROBLEM TO BE SOLVED: To prevent the utilization of immediate data or the designation of an absolute address from being limited even when the number of bits of a fixed length instruction format is less than the data word length, by adopting the fixed length instruction format having bits less than the maximum data word length supplied to an instruction executing means. SOLUTION: IRH and IRL are the instruction buffers of 16 bits respectively, and an instruction is transferred through an internal data bus for the unit of 32 bits while being stored one by one. These instructions are loaded through a multiplexer MPX to an instruction register IR1. The instruction register IR1 has 16 bits. Thus, since the fixed length instruction format of 16 bits is adopted for the data word length of 32 bits, the judgement on where an instruction border exists, can be grasped before the completion of the preceding instruction, and the advantage of the simplification of instruction decode processing or the like is guaranteed. Further, the useless arrangement of bits is decreased and the utilization efficiency of a program memory is improved.

80. 发明专利

JPH09171454A DATA PROCESSOR 失效
公开(公告)号：JPH09171454A
公开(公告)日：1997-06-30
申请号：JP23614096
申请日：1996-09-06
申请人： HITACHI LTD
发明人： KIUCHI ATSUSHI , HATANO YUJI , UMAJI TORU , NOGUCHI YOSHIKI , AKAO YASUSHI , BABA SHIRO
IPC分类号： G06F5/01 , G06F7/00 , G06F7/76 , G06F9/302 , G06F9/312 , G06F9/34 , G06F9/38 , G06F15/78 , G06F17/10
摘要： PROBLEM TO BE SOLVED: To enable more complicated digital signal processing by constituting a digital signal processing unit so as to handle fixed point data. SOLUTION: A CPU 100 and a digital signal processing unit 104 whose operation is controlled by decoding an instruction by this CPU 100 are provided on a semiconductor substrate. This digital signal processing unit 104 has a function processing fixed point data. Namely, the arithmetic logical computing element 105 of this digital signal processing unit 104 executes addition/ subtraction and a logical arithmetic processing. A multiplier 106 multiplies two word data of 16-bit length and outputs the result of a 32-bit length. Further, in the case of an integral multiplication, the low rank word of a source register is inputted as source data, and in the case of a fixed point multiplication, the high rank of the source register is inputted as source data.

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